Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a V RAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.

Description

76 parts

›RELATED APPLICATIONS

The present application claims priority to U.S. Provisional Patent Application No. 61/421,348, filed Dec. 9, 2010.

The present application claims priority to U.S. Provisional Patent Application No. 61/421,475, filed Dec. 9, 2010.

The present application claims priority to U.S. Provisional Patent Application No. 61/469,276, filed Mar. 30, 2011.

The present application claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/089,917, filed Apr. 19, 2011, entitled “PSEUDO-ENVELOPE FOLLOWING POWER MANAGEMENT SYSTEM,” which claims priority to U.S. Provisional Patent Application No. 61/325,659, filed Apr. 19, 2010.

The present application claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/218,400, filed Aug. 25, 2011, entitled “BOOST CHARGE-PUMP WITH FRACTIONAL RATIO AND OFFSET LOOP FOR SUPPLY MODULATION,” which claims priority to U.S. Provisional Patent Application No. 61/376,877, filed Aug. 25, 2010. U.S. patent application Ser. No. 13/218,400, is a continuation-in-part of U.S. patent application Ser. No. 13/089,917, filed Apr. 19, 2011, which claims priority to U.S. Provisional Patent Application No. 61/325,659, filed Apr. 19, 2010.

All of the applications listed above are hereby incorporated herein by reference in their entireties.

›FIELD OF THE DISCLOSURE

The embodiments described herein relate to a power management system for delivering current to a linear RF power amplifier. More particularly, the embodiments relate to the use of a pseudo-envelope tracker in a power management system of mobile communications equipment.

›BACKGROUND

Next-generation mobile devices are morphing from voice-centric telephones to message and multimedia-based “smart” phones that offer attractive new features. As an example, smart phones offer robust multimedia features such as web-browsing, audio and video playback and streaming, email access and a rich gaming environment. But even as manufacturers race to deliver ever more feature rich mobile devices, the challenge of powering them looms large.

In particular, the impressive growth of high bandwidth applications for radio-frequency (RF) hand-held devices has led to increased demand for efficient power saving techniques to increase battery life. Because the power amplifier of the mobile device consumes a large percentage of the overall power budget of the mobile device, various power management systems have been proposed to increase the overall power efficiency of the power amplifier.

As an example, some power managements systems may use a V RAMP power control voltage to control the voltage presented on a power amplifier collector of a linear RF power amplifier. As another example, other power management schemes may use a buck converter power supply and a class AB amplifier in tandem to provide power to the linear RF power amplifier.

Even so, there remains a need to further improve the power efficiency of mobile devices to provide extended battery life. As a result, there is a need to improve the power management system of mobile devices.

›SUMMARY · 1 of 3

A first embodiment of pseudo-envelope follower power management system with high frequency ripple compensation includes a switch mode power supply converter and an open loop high frequency ripple compensation assist circuit. For example, the switch mode power supply converter may be configured to operate as a buck converter. As another example, the switch mode power supply converter may be configured to operate as a multi-level charge pump buck converter. The switch mode power supply may generate a switching output voltage and a switching voltage output estimate. The switching voltage output estimate may provide an early indication of a future voltage level of the switching output voltage. For example, in some embodiments, the switch mode power supply converter may also include programmable delay circuitry, a switcher control circuit, and a buffer scalar. The switcher control circuit may generate a digital switching voltage output signal that represents a state of the switcher control circuit used to control generation of the switching output voltage by the switch mode power supply converter. The programmable delay circuitry may receive the digital switching voltage output signal, and delay the digital switching voltage output signal by a programmable delay period to generate a delayed digital switching voltage output signal. The buffer scalar is configured to receive the delayed digital switching voltage output signal, and generate the switching voltage output estimate based on the delayed digital switching voltage output signal and a buffer scalar.

The open loop high frequency ripple compensation assist circuit is configured to receive the switching voltage output estimate and a V RAMP signal. Based on the based on the switching voltage output estimate and the V RAMP signal, the open loop high frequency ripple compensation assist circuit generates a high frequency ripple compensation current. The open loop high frequency ripple compensation assist circuit applies the high frequency ripple compensation current to a power amplifier supply output to reduce high frequency ripple current at the power amplifier supply output. The power amplifier supply output is configured to power a linear radio frequency power amplifier. The high frequency ripple compensation current is generated in a frequency band located substantially near a transmit to receive duplex offset for a band of operation in a communication network, where the frequency band of the high frequency ripple compensation current has a bandwidth substantially equal to a bandwidth of a receiver channel frequency band for the band of operation.

In some embodiments, the switch mode power supply converter further includes a programmable delay circuitry configured to delay generation of the switching voltage output estimate by a programmable delay period. The programmable delay period may be configured to temporally align the switching voltage output estimate and the V RAMP signal to position a notch in a ripple rejection response of the power amplifier supply output near the transmit to receive duplex offset for the band of operation. In addition, the open loop high frequency ripple compensation assist circuit may generate a scaled high frequency ripple compensation current estimate based on the high frequency ripple compensation current, which can be used as part of a feedback signal to the switch mode power supply converter. As an example, the switch mode power supply converter may receive a feedback signal, wherein the feedback signal is based on the scaled high frequency ripple compensation current estimate, where the switch mode power supply converter adjusts the switching output voltage based on the feedback signal. In some embodiments, the pseudo-envelope follower power management system with high frequency ripple compensation further includes a parallel amplifier. The parallel amplifier receives the V RAMP signal and a power amplifier supply voltage from the power amplifier supply output. Based on a difference between the V RAMP signal and the power amplifier supply voltage, the parallel amplifier generates a parallel amplifier output current. The parallel amplifier applies the parallel amplifier output current to the power amplifier supply output to control the power amplifier supply voltage. In addition, the parallel amplifier may generate a scaled parallel amplifier output current estimate based on the parallel amplifier output current. The scaled parallel amplifier output current estimate may be combined with the scaled high frequency ripple compensation current estimate to create the feedback signal provided to the switch mode power supply converter.

Some embodiments of open loop high frequency ripple compensation assist circuit may include a filter network having a first node and a second node, a feedback network having a first node and a second node, and an operational amplifier including a non-inverting input, an inverting input, and an operational amplifier output. The first node of the filter network may be configured to receive the switching voltage output estimate. The second node of the filter network may be in communication with the inverting input of the operational amplifier. The first node of the feedback network may be in communication with the second node of the filter network and the inverting input of the operational amplifier. In addition, the second node of the feedback network may be in communication with the operational amplifier output. The operational amplifier may be configured to generate the high frequency ripple compensation current. The operational amplifier may also be configured to generate a scaled high frequency ripple compensation current estimate as a function of the high frequency ripple compensation current. The operational amplifier may include a first push-pull output stage in communication with the operational amplifier output, where the first push-pull output stage generates an operational amplifier output current. A bias capacitor having a bias capacitance and a bias resistor may be arranged in series between the operational amplifier output and a reference voltage. For example, the reference voltage may be ground. The first push-pull output stage may have a first stage transconductance. The bias capacitance may be configured such that the first stage transconductance of the first push-pull output stage is substantially equal to a transconductance of the bias resistor in a frequency band located substantially near a transmit to receive duplex offset for a band of operation in a communication network. The open loop high frequency ripple compensation assist circuit may also include an operational amplifier output isolation circuit including a high impedance input in communication with the operational amplifier output and an isolated feedback node in communication with the second node of the feedback network. The operational amplifier may also include a second push-pull output stage configured to generate the high frequency ripple compensation current, where the high frequency ripple compensation current is mirrored to the operational amplifier output current. The second push-pull output stage may include a programmable second output stage transconductance. The programmable second output stage transconductance second output stage transconductance may be a substantially linear function of a programmable transconductance parameter. The open loop high frequency ripple compensation assist circuit may adjust a magnitude of the high frequency ripple compensation current based on the programmable second output stage transconductance. The operational amplifier may also include a third push-pull output stage configured to generate the scaled high frequency ripple compensation current estimate as a function of the high frequency ripple compensation current based on a sense scaling factor.

›SUMMARY · 2 of 3

The filter network may be associated with a first corner frequency of a filter response of the open loop ripple compensation assist circuit. The feedback network may be associated with a second corner frequency of the frequency response of the open loop ripple compensation assist circuit. In some cases, the first corner frequency has a programmable range between 3 MHz and 11.5 MHz and the second corner frequency has a programmable range between 3 MHz and 11.5 MHz. In other cases, the first corner frequency is substantially equal to 6 MHz, and the second corner frequency is substantially equal to 6 MHz.

Another example embodiment includes a method for reducing high frequency ripple currents at a power amplifier supply output. The method may include a first step of generating a switching output voltage and a switching voltage output estimate with a switch mode power supply converter, where the switching voltage output estimate provides an early indication of a future voltage level of the switching output voltage. The method may include the step of receiving the switching voltage output estimate and a V RAMP signal at an open loop high frequency ripple compensation assist circuit. The method may include the step of generating a high frequency ripple compensation current based on the switching voltage output estimate and the V RAMP signal. The method may include the step of applying the high frequency ripple compensation current to a power amplifier supply output to reduce high frequency ripple current at the power amplifier supply output. In some embodiments the generation of the high frequency ripple compensation current based on the switching voltage output estimate and the V RAMP signal may include generating the high frequency ripple compensation current within in a frequency band located substantially near a transmit to receive duplex offset for a band of operation in a communication network. In addition, the frequency band of the high frequency ripple compensation current may have a bandwidth substantially equal to a bandwidth of a receiver channel frequency band for the band of operation. In some embodiments, generation of the switching voltage output estimate may include delaying generation of the switching voltage output estimate by a programmable delay period to temporally align the switching voltage output estimate and the V RAMP signal to position a notch in a ripple rejection response of the power amplifier supply output near the transmit to receive duplex offset for the band of operation. In addition, the method may further include a step for generating a scaled high frequency ripple compensation current estimate based on the high frequency ripple compensation current. Based on the scaled high frequency ripple compensation current estimate, the method may form a feedback signal, which is provided to the switch mode power supply converter. The switch mode power supply converter may adjust the switching output voltage based on the feedback signal. In some embodiments, the switch mode power supply converter is configured to be a buck converter. Alternatively, in other embodiments, the switch mode power supply converter is configured to be a multi-level charge pump buck converter.

One example embodiment of the pseudo-envelope follower power management system may include a switch mode power supply converter and a parallel amplifier cooperatively coupled to provide a linear RF power amplifier supply to a linear RF power amplifier. The pseudo-envelope follower power management system may include a charge pump configured to power the parallel amplifier. The charge pump may generate a plurality of output voltage levels. The charge pump may be either a boost charge pump or a boost/buck charge pump. The pseudo-envelope follower power management system may include an offset voltage control circuit configured to provide feedback to the switch mode power supply converter to regulate an offset voltage developed across a coupling device that couples the output of the parallel amplifier to the linear RF power amplifier supply.

Another example embodiment of a power management system for a linear radio frequency power amplifier includes a switch mode power supply converter and a parallel amplifier operatively coupled to generate a linear radio frequency power amplifier supply output for a linear radio frequency power amplifier of a radio frequency device. The switch mode power supply converter may be configured to generate a plurality of switching voltage levels on a switching voltage output. The switching voltage output of the switch mode power supply converter may be coupled via a power inductor to the linear radio frequency power amplifier supply output. A bypass capacitor may be coupled between the linear radio frequency power amplifier supply output and ground such that the power inductor and bypass capacitor form a low pass filter for the switch mode power supply converter. The parallel amplifier may include a parallel amplifier output coupled, via a coupling device, to the linear radio frequency power amplifier supply output. As an example, the coupling device may be a coupling capacitor. The power management system may further include a charge pump configured to provide a charge pump parallel amplifier power supply output. The charge pump may include a first flying capacitor, a second flying capacitor, a plurality of switches operably coupled to form the charge pump parallel amplifier power supply output. The charge pump may be configured to selectively generate various output voltage levels, derived from a supply voltage, on the charge pump parallel amplifier power supply output. In addition, the charge pump parallel amplifier power supply output may be configured to provide an operational power supply voltage to the parallel amplifier.

Another example embodiment of a pseudo-envelope follower power management system may include a multi-level charge pump buck converter and a parallel amplifier configured to operate in tandem to generate a power amplifier supply voltage output for a linear RF power amplifier. The multi-level charge pump buck converter may include a supply input configured to receive a direct current (DC) voltage, and a switching voltage output. The switching voltage output is coupled to the power amplifier supply voltage output by a power inductor, where the power inductor couples to a bypass capacitor to form an output filter for the switching voltage output of the multi-level charge pump buck converter. The parallel amplifier may include a supply input configured to receive the direct current (DC) voltage, an amplifier output, a first control input configured to receive a V RAMP signal, and a second control input configured to receive the power amplifier supply voltage. The amplifier output may be coupled to the power amplifier supply voltage by a coupling circuit. In some embodiments of the pseudo-envelope follower system, the coupling circuit may be an offset capacitor. In other embodiments of the pseudo-envelope follower system, the coupling circuit may be a wire trace such that the offset voltage between the amplifier output and the power amplifier supply voltage is zero volts.

›SUMMARY · 3 of 3

In addition, the multi-level charge pump buck converter may generate a feed forward control signal configured to provide an indication of the output state of the switching voltage output to the parallel amplifier. In some embodiments, the switching voltage output is provided as the feed forward control signal. In other embodiments, the feed forward control signal is generated by a switcher control circuit and provides an indication of the switching voltage output based on the state of the switcher control circuit. The parallel amplifier may include a power amplifier output current estimate signal that provides an estimate of the output current of the parallel amplifier. In some embodiments of the pseudo-envelope follower system, the parallel amplifier may also generate a threshold offset signal. The threshold offset signal may be configured to estimate the magnitude of the offset voltage appearing across the coupling circuit.

The multi-level buck converter may include a supply input configured to receive a direct current (DC) voltage, a switching voltage output coupled to a power inductor, a switcher control circuit, a multi-level charge pump circuit having a control input, a charge pump supply input configured to receive the DC voltage, a series switch having a first switch terminal, a second switch terminal, and a series control terminal and a shunt switch having a first switch terminal, a second switch terminal, and a shunt control terminal. The first terminal of the series switch may be coupled to the supply input of the multi-level buck converter. The second terminal of the series switch may be coupled to the first terminal of the series switch to form a switching voltage output. The second terminal of the series switch may be coupled to ground. The boost charge pump circuit may include a charge pump control input, a charge pump supply input coupled to the supply input of the multi-level buck converter, and a charge pump output coupled to the supply input of the multi-level buck converter. The boost charge pump includes a plurality of switches and two flying capacitors that provide for three modes of operation. In a charging mode of operation, the flying capacitors are coupled in series between the charge pump supply input and ground, wherein the flying capacitors are switchably disconnected from the charge pump output. In a first boost mode of operation, the flying capacitors are arranged in parallel between the charge pump output and the charge pump supply input to generate a 1.5× the DC voltage output at the charge pump output. In a second boost mode of operation, the flying capacitors are arranged in series between the charge pump output and the charge pump supply input to generate a 2× the DC voltage output at the charge pump output. The multi-level buck converter may include four modes of operation. In a first mode of operation, the series switch is open, the boost charge pump is in the charging mode of operation, and the shunt switch is closed to generate zero volts at the switching voltage output. In a second mode of operation, the series switch is closed, the boost charge pump is in the charging mode of operation, and the shunt switch is open to generate the DC voltage output at the switching voltage output. In a third mode of operation, both the series switch and the shunt switch are open and the boost charge pump is in the first boost mode of operation to generate a 1.5× the DC voltage output at the switching mode output. In a fourth mode of operation, both the series switch and the shunt switch are open and the boost charge pump is in the second boost mode of operation to generate a 2× the DC voltage output at the switching mode output.

Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

›BRIEF DESCRIPTION OF THE DRAWINGS · 1 of 3

The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1A depicts an embodiment of a pseudo-envelope follower power management system for managing power supplied to a linear RF power amplifier.

FIG. 1B depicts an embodiment of a pseudo-envelope follower power management system for managing power supplied to a linear RF power amplifier.

FIG. 2A depicts an embodiment of the pseudo-envelope follower power management system of FIG. 1A in further detail.

FIG. 2B depicts an embodiment of the pseudo-envelope follower power management system of FIG. 1B in further detail.

FIG. 3A depicts an embodiment of a portion of a multi-level charge pump buck converter.

FIG. 3B depicts another embodiment of a portion of a multi-level charge pump buck converter.

FIG. 3C depicts another embodiment of a portion of a multi-level charge pump buck converter.

FIG. 3D depicts another embodiment of a portion of a multi-level charge pump buck converter.

FIG. 3E depicts another embodiment of a portion of a buck converter.

FIG. 3F depicts another embodiment of a portion of a buck converter.

FIG. 3G depicts another embodiment of a portion of a buck converter.

FIG. 3H depicts another embodiment of a portion of a buck converter.

FIG. 3I depicts an embodiment of a switcher control circuit for a multi-level charge pump buck converter having feedback compensation.

FIG. 3J depicts an embodiment of a switcher control circuit for a multi-level charge pump buck converter having feedback compensation.

FIG. 3K depicts an embodiment of a switcher control circuit for a multi-level charge pump buck converter having feedback compensation.

FIG. 3L depicts an embodiment of a switcher control circuit for a multi-level charge pump buck converter having feedback compensation.

FIG. 3M depicts an embodiment of a switcher control circuit for a buck converter having feedback compensation.

FIG. 3N depicts an embodiment of a switcher control circuit for a buck converter having feedback compensation.

FIG. 3P depicts an embodiment of a switcher control circuit for a buck converter having feedback compensation.

FIG. 3Q depicts an embodiment of a switcher control circuit for a buck converter having feedback compensation.

FIG. 3R depicts an embodiment of a switcher control circuit for a multi-level charge pump buck converter having feedback compensation.

FIG. 4A depicts an embodiment of a threshold detector and control circuit of a switcher control circuit of a multi-level charge pump buck converter.

FIG. 4B depicts another embodiment of a threshold detector and control circuit of a switcher control circuit of a multi-level charge pump buck converter.

FIG. 4C depicts another embodiment of a threshold detector and control circuit of a switcher control circuit of a multi-level charge pump buck converter.

FIG. 4D depicts another embodiment of a threshold detector and control circuit of a switcher control circuit of a multi-level charge pump buck converter.

FIG. 4E depicts an embodiment of a threshold detector and control circuit of a buck converter.

FIG. 4F depicts another embodiment of a threshold detector and control circuit of a buck converter.

FIG. 4G depicts another embodiment of a threshold detector and control circuit of a buck converter.

FIG. 4H depicts another embodiment of a threshold detector and control circuit of a buck converter.

FIG. 4I depicts an embodiment of a threshold detector and control circuit of a multi-level charge pump buck converter that includes feedback compensation.

FIG. 4J depicts an embodiment of a threshold detector and control circuit of a multi-level charge pump buck converter that includes feedback compensation.

FIG. 4K depicts another embodiment of a threshold detector and control circuit of a multi-level charge pump buck converter that includes feedback compensation.

FIG. 4L depicts another embodiment of a threshold detector and control circuit of a multi-level charge pump buck converter that includes feedback compensation.

FIG. 4M depicts an embodiment of a threshold detector and control circuit of a buck converter that includes feedback compensation.

FIG. 4N depicts another embodiment of a threshold detector and control circuit of a buck converter that includes feedback compensation.

FIG. 4P depicts another embodiment of a threshold detector and control circuit of a buck converter that includes feedback compensation.

FIG. 4Q depicts another embodiment of a threshold detector and control circuit of a buck converter that includes feedback compensation.

FIG. 4R depicts another embodiment of a threshold detector and control circuit of a multi-level charge pump buck converter that includes feedback compensation.

FIG. 5A depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4A .

FIG. 5B depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4B .

FIG. 5C depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4C .

FIG. 5D depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4D .

FIG. 5E depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4E .

FIG. 5F depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4F .

FIG. 5G depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4G .

FIG. 5H depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4H .

FIG. 5L depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4L .

FIG. 5Q depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4Q .

FIG. 5R depicts an embodiment of a first state machine of the threshold detector and control circuit of FIG. 4R .

›BRIEF DESCRIPTION OF THE DRAWINGS · 2 of 3

FIG. 6A depicts an embodiment of a second state machine of the threshold detector and control circuit of FIG. 4A .

FIG. 6B depicts an embodiment of a second state machine of the threshold detector and control circuit of FIG. 4B .

FIG. 6C depicts an embodiment of a second state machine of the threshold detector and control circuit of FIG. 4C .

FIG. 6D depicts an embodiment of a second state machine of the threshold detector and control circuit of FIG. 4D .

FIG. 6L depicts an embodiment of a second state machine of the threshold detector and control circuit of FIG. 4L .

FIG. 6R depicts an embodiment of a second state machine of the threshold detector and control circuit of FIG. 4R .

FIG. 7A depicts one embodiment of a multi-level charge pump circuit of a pseudo-envelope follower power management system.

FIG. 7B depicts another embodiment of a multi-level charge pump circuit of a pseudo-envelope follower power management system.

FIG. 7C depicts still another embodiment of a multi-level charge pump circuit of a pseudo-envelope follower power management system.

FIG. 8 depicts one embodiment of a V OFFSET loop circuitry of a parallel amplifier circuit of a pseudo-envelope follower power management system.

FIG. 9A depicts an embodiment of the open loop assist circuit of a parallel amplifier circuit of a pseudo-envelope follower power management system.

FIG. 9B depicts an embodiment of the open loop assist circuit of a parallel amplifier circuit of a pseudo-envelope follower power management system.

FIG. 10 depicts an embodiment of a parallel amplifier output impedance compensation circuit of a parallel amplifier circuit of a pseudo-envelope follower power management system.

FIG. 11A depicts one embodiment of the indication of the switching voltage output generated by a multi-level charge pump buck converter in a pseudo-envelope follower power management system.

FIG. 11B depicts another embodiment of the indication of the switching voltage output generated by a multi-level charge pump buck converter in a pseudo-envelope follower power management system.

FIG. 11C depicts another embodiment of the indication of the switching voltage output generated by a multi-level charge pump buck converter in a pseudo-envelope follower power management system.

FIG. 11D depicts another embodiment of the indication of the switching voltage output generated by a multi-level charge pump buck converter in a pseudo-envelope follower power management system.

FIG. 11E depicts another embodiment of the indication of the switching voltage output generated by a multi-level charge pump buck converter in a pseudo-envelope follower power management system.

FIG. 11F depicts another embodiment of the indication of the switching voltage output generated by a multi-level charge pump buck converter in a pseudo-envelope follower power management system

FIG. 12A depicts one embodiment of a parallel amplifier used in a pseudo-envelope follower power management system.

FIG. 12B depicts one embodiment of a rechargeable parallel amplifier used in a pseudo-envelope follower power management system.

FIG. 12C depicts another embodiment of a rechargeable parallel amplifier used in a pseudo-envelope follower power management system.

FIG. 12D depicts one embodiment of a parallel amplifier used in a pseudo-envelope follower power management system.

FIG. 12E depicts another embodiment of a rechargeable parallel amplifier used in a pseudo-envelope follower power management system.

FIG. 12F depicts another embodiment of a rechargeable parallel amplifier used in a pseudo-envelope follower power management system.

FIG. 13 depicts an embodiment of a pseudo-envelope follower power management system including a buck converter and a parallel amplifier circuit having an open loop assist circuit and a parallel amplifier circuit.

FIG. 14 depicts another embodiment of a pseudo-envelope follower power management system including a multi-level charge pump buck converter and a parallel amplifier circuit having both an open loop assist circuit and a parallel amplifier circuit.

FIG. 15 depicts another embodiment of a pseudo-envelope follower power management system including a multi-level charge pump buck converter and a parallel amplifier circuit having a parallel amplifier circuit and a V OFFSET loop circuit.

FIG. 16 depicts another embodiment of a pseudo-envelope follower power management system including a multi-level charge pump buck converter and a parallel amplifier circuit having a parallel amplifier, a V OFFSET loop circuit, an open loop assist circuit and a parallel amplifier output impedance compensation circuit.

FIG. 17A depicts another embodiment of pseudo-envelope follower power management system including a buck converter and a parallel amplifier circuit having a rechargeable parallel amplifier circuit.

FIG. 17B depicts another embodiment of a pseudo-envelope follower power management system including a buck converter and a parallel amplifier circuit having a parallel amplifier circuit.

FIG. 18A depicts an embodiment of a pseudo-envelope follower power management system having a multi-level charge pump buck converter and a μC charge pump circuit configured to provide a parallel amplifier power supply to a parallel amplifier circuit.

FIG. 18B depicts another embodiment of a pseudo-envelope follower power management system having a multi-level charge pump buck converter and a μC charge pump circuit configured to provide a parallel amplifier power supply to a parallel amplifier circuit.

FIG. 18C depicts an embodiment of a pseudo-envelope follower power management system having a buck converter and a μC charge pump circuit configured to provide a parallel amplifier power supply to a parallel amplifier circuit.

FIG. 18D depicts another embodiment of a pseudo-envelope follower power management system having a buck converter and a μC charge pump circuit configured to provide a parallel amplifier power supply to a parallel amplifier circuit.

FIG. 19A depicts an embodiment of a μC charge pump circuit configured to provide a parallel amplifier power supply to a parallel amplifier circuit of a pseudo-envelope follower power management system.

›BRIEF DESCRIPTION OF THE DRAWINGS · 3 of 3

FIG. 19B depicts another embodiment of a μC charge pump circuit configured to provide a parallel amplifier power supply to a parallel amplifier circuit of a pseudo-envelope follower power management system, where the μC charge pump circuit includes both buck and boost modes of operation.

FIGS. 20A-C depict functionally equivalent circuit topologies of the μC charge pump circuit of FIG. 19A for different modes of operation of the μC charge pump circuit.

FIG. 21 depicts a method for configuring a μC charge pump circuit to provide a supply voltage to a parallel amplifier prior to commencement of a data transmission by a linear RF power amplifier.

FIG. 22 depicts a method for pre-charging a V OFFSET Loop Circuit prior to commencement of a data transmission by a linear RF power amplifier.

FIG. 23A depicts an embodiment of a pseudo-envelope follower power management system including a multi-level charge pump buck converter and an embodiment of a parallel amplifier circuit that includes an open loop ripple compensation assist circuit.

FIG. 23B depicts an embodiment of a pseudo-envelope follower power management system including a buck converter and an embodiment of a parallel amplifier circuit that includes an open loop ripple compensation assist circuit.

FIG. 23C depicts an embodiment of a pseudo-envelope follower power management system including a multi-level charge pump buck converter and an embodiment of a parallel amplifier circuit that includes an open loop ripple compensation assist circuit in combination with an open loop assist circuit.

FIG. 23D depicts an embodiment of a pseudo-envelope follower power management system including a buck converter and an embodiment of a parallel amplifier circuit that includes an open loop ripple compensation assist circuit in combination with an open loop assist circuit.

FIG. 24 depicts an embodiment of the open loop ripple compensation assist circuit and corresponding programmable delay circuitry of the pseudo-envelope follower power management systems depicted in FIGS. 23A-23D .

FIG. 25 depicts three example ripple rejection response curves for an embodiment of the pseudo-envelope follower power management system, where each example ripple rejection response curve corresponds to a different programmable delay.

FIG. 26 further depicts an embodiment of the high pass circuitry depicted in FIG. 25 .

FIG. 27A depicts an embodiment of the open loop ripple compensation assist circuit of FIGS. 23A-23D .

FIG. 27B that depicts an alternative embodiment of the open loop ripple compensation assist circuit of FIGS. 23A-23D .

FIG. 28A depicts example ripple rejection response curves for an example pseudo-envelope follower power management system having an operational amplifier isolation circuit.

FIG. 28B depicts example ripple rejection response curves for an example pseudo-envelope follower power management system not having an operational amplifier isolation circuit.

FIG. 29A depicts an embodiment of the programmable delay circuitry depicted in FIG. 24 .

FIG. 29B depicts another example embodiment of the programmable delay circuitry depicted in FIG. 24 .

FIG. 30 depicts another example embodiment of the programmable delay circuitry depicted in FIG. 24 .

FIG. 31A depicts an example embodiment of the operational amplifier of the embodiment of an operational amplifier circuitry depicted in FIG. 27A .

FIG. 31B depicts an example embodiment of the operational amplifier depicted in FIG. 27B , where the Operational Amplifier Output Isolation Circuit is eliminated.

FIG. 32A depicts example embodiments of the operational amplifier push-pull output state circuit and the operational amplifier controlled I COR current circuit of an operational amplifier.

FIG. 32B depicts an example embodiment of the operational amplifier controlled I COR — SENSE current circuit of an operational amplifier.

FIG. 32C depicts an example embodiment of the Gm bias circuit and operational amplifier isolation circuit of the embodiment of the operational amplifier circuitry.

FIG. 32D depicts an example embodiment of the Gm bias circuit of the operational amplifier.

FIG. 33 depicts a graphical representation of the programmable transconductance (Gm) output current function of an example embodiment of the operational amplifier controlled I COR current circuit.

FIG. 34A depicts an embodiment of a parallel amplifier output impedance compensation circuit including a digital V RAMP pre-distortion filter circuit.

FIG. 34B depicts an alternative embodiment of a parallel amplifier output impedance compensation circuit.

FIG. 34C depicts another embodiment of a parallel amplifier output impedance compensation circuit including an analog V RAMP pre-distortion filter circuit.

FIG. 34D depicts an alternative embodiment of a parallel amplifier output impedance compensation circuit.

FIG. 34E depicts an alternative embodiment of a parallel amplifier output impedance compensation circuit.

FIG. 35 depicts embodiments of the digital V RAMP pre-distortion filter and a V RAMP digital-to-analog (D/A) circuit.

FIG. 36 depicts an example embodiment of a variable delay capacitor.

FIG. 37 depicts an example graph of the total delay time provided by the programmable delay circuit depicted in FIG. 30 as a function of the binary weighted programmable capacitor array.

FIG. 38A depicts an example embodiment of a pseudo-envelope follower power management system that includes a feedback delay compensation circuit in combination with a multi-level charge pump buck converter.

FIG. 38B depicts an example embodiment of a pseudo-envelope follower power management system that includes a feedback delay compensation circuit in combination with a buck converter.

FIG. 39A depicts a block diagram of an embodiment of the feedback delay compensation circuit of FIG. 38A and FIG. 38B .

FIG. 39B depicts another embodiment of the feedback delay compensation circuit of FIG. 38A and FIG. 38B .

›DETAILED DESCRIPTION · 1 of 67

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

Embodiments disclosed herein relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a V RAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.

A first embodiment of the pseudo-envelope follower power management system with high frequency ripple compensation includes a switch mode power supply converter and an open loop high frequency ripple compensation assist circuit. For example, the switch mode power supply converter may be configured to operate as a buck converter. As another example, the switch mode power supply converter may be configured to operate as a multi-level charge pump buck converter. The switch mode power supply may generate a switching output voltage and a switching voltage output estimate. The switching voltage output estimate may provide an early indication of a future voltage level of the switching output voltage. For example, in some embodiments, the switch mode power supply converter may also include programmable delay circuitry, a switcher control circuit, and a buffer scalar. The switcher control circuit may generate a digital switching voltage output signal that represents a state of the switcher control circuit used to control generation of the switching output voltage by the switch mode power supply converter. The programmable delay circuitry may receive the digital switching voltage output signal, and delay the digital switching voltage output signal by a programmable delay period to generate a delayed digital switching voltage output signal. The buffer scalar is configured to receive the delayed digital switching voltage output signal, and generate the switching voltage output estimate based on the delayed digital switching voltage output signal and a buffer scalar.

The open loop high frequency ripple compensation assist circuit is configured to receive the switching voltage output estimate and a V RAMP signal. Based on the switching voltage output estimate and the V RAMP signal, the open loop high frequency ripple compensation assist circuit generates a high frequency ripple compensation current. The open loop high frequency ripple compensation assist circuit applies the high frequency ripple compensation current to a power amplifier supply output to reduce high frequency ripple current at the power amplifier supply output. The power amplifier supply output is configured to power a linear radio frequency power amplifier. The high frequency ripple compensation current is generated in a frequency band located substantially near a transmit to receive duplex offset for a band of operation in a communication network, where the frequency band of the high frequency ripple compensation current has a bandwidth substantially equal to a bandwidth of a receiver channel frequency band for the band of operation.

In some embodiments, the switch mode power supply converter further includes programmable delay circuitry configured to delay generation of the switching voltage output estimate by a programmable delay period. The programmable delay period may be configured to temporally align the switching voltage output estimate and the V RAMP signal to position a notch in a ripple rejection response of the power amplifier supply output near the transmit to receive duplex offset for the band of operation. In addition, the open loop high frequency ripple compensation assist circuit may generate a scaled high frequency ripple compensation current estimate based on the high frequency ripple compensation current, which can be used as part of a feedback signal to the switch mode power supply converter. As an example, the switch mode power supply converter may receive a feedback signal, wherein the feedback signal is based on the scaled high frequency ripple compensation current estimate, where the switch mode power supply converter adjusts the switching output voltage based on the feedback signal. In some embodiments, the pseudo-envelope follower power management system with high frequency ripple compensation further includes a parallel amplifier. The parallel amplifier receives the V RAMP signal and a power amplifier supply voltage from the power amplifier supply output. Based on a difference between the V RAMP signal and the power amplifier supply voltage, the parallel amplifier generates a parallel amplifier output current. The parallel amplifier applies the parallel amplifier output current to the power amplifier supply output to control the power amplifier supply voltage. In addition, the parallel amplifier may generate a scaled parallel amplifier output current estimate based on the parallel amplifier output current. The scaled parallel amplifier output current estimate may be combined with the scaled high frequency ripple compensation current estimate to create the feedback signal provided to the switch mode power supply converter.

›DETAILED DESCRIPTION · 2 of 67

Some embodiments of the open loop high frequency ripple compensation assist circuit may include a filter network having a first node and a second node, a feedback network having a first node and a second node, and an operational amplifier including a non-inverting input, an inverting input, and an operational amplifier output. The first node of the filter network may be configured to receive the switching voltage output estimate. The second node of the filter network may be in communication with the inverting input of the operational amplifier. The first node of the feedback network may be in communication with the second node of the filter network and the inverting input of the operational amplifier. In addition, the second node of the feedback network may be in communication with the operational amplifier output. The operational amplifier may be configured to generate the high frequency ripple compensation current. The operational amplifier may also be configured to generate a scaled high frequency ripple compensation current estimate as a function of the high frequency ripple compensation current. The operational amplifier may include a first push-pull output stage in communication with the operational amplifier output, where the first push-pull output stage generates an operational amplifier output current. A bias capacitor having a bias capacitance and a bias resistor may be arranged in series between the operational amplifier output and a reference voltage. For example, the reference voltage may be ground. The first push-pull output stage may have a first stage transconductance. The bias capacitance may be configured such that the first stage transconductance of the first push-pull output stage is substantially equal to a transconductance of the bias resistor in a frequency band located substantially near a transmit to receive duplex offset for a band of operation in a communication network. The open loop high frequency ripple compensation assist circuit may also include an operational amplifier output isolation circuit including a high impedance input in communication with the operational amplifier output and an isolated feedback node in communication with the second node of the feedback network. The operational amplifier may also include a second push-pull output stage configured to generate the high frequency ripple compensation current, where the high frequency ripple compensation current is mirrored to the operational amplifier output current. The second push-pull output stage may include a programmable second output stage transconductance. The programmable second output stage transconductance second output stage transconductance may be a substantially linear function of a programmable transconductance parameter. The open loop high frequency ripple compensation assist circuit may adjust a magnitude of the high frequency ripple compensation current based on the programmable second output stage transconductance. The operational amplifier may also include a third push-pull output stage configured to generate the scaled high frequency ripple compensation current estimate as a function of the high frequency ripple compensation current based on a sense scaling factor.

The filter network may be associated with a first corner frequency of a filter response of the open loop high frequency ripple compensation assist circuit. The feedback network may be associated with a second corner frequency of the frequency response of the open loop high frequency ripple compensation assist circuit. In some cases, the first corner frequency has a programmable range between 3 MHz and 11.5 MHz and the second corner frequency has a programmable range between 3 MHz and 11.5 MHz. In other cases, the first corner frequency is substantially equal to 6 MHz, and the second corner frequency is substantially equal to 6 MHz.

Another example embodiment includes a method for reducing high frequency ripple currents at a power amplifier supply output. The method may include a first step of generating a switching output voltage and a switching voltage output estimate with a switch mode power supply converter, where the switching voltage output estimate provides an early indication of a future voltage level of the switching output voltage. The method may include the step of receiving the switching voltage output estimate and a V RAMP signal at an open loop high frequency ripple compensation assist circuit. The method may include the step of generating a high frequency ripple compensation current based on the switching voltage output estimate and the V RAMP signal. The method may include the step of applying the high frequency ripple compensation current to a power amplifier supply output to reduce high frequency ripple currents at the power amplifier supply output. In some embodiments, the generation of the high frequency ripple compensation current based on the switching voltage output estimate and the V RAMP signal may include generating the high frequency ripple compensation current within in a frequency band located substantially near a transmit to receive duplex offset for a band of operation in a communication network. In addition, the frequency band of the high frequency ripple compensation current may have a bandwidth substantially equal to a bandwidth of a receiver channel frequency band for the band of operation. In some embodiments, generation of the switching voltage output estimate may include delaying generation of the switching voltage output estimate by a programmable delay period to temporally align the switching voltage output estimate and the V RAMP signal to position a notch in a ripple rejection response of the power amplifier supply output near the transmit to receive duplex offset for the band of operation. In addition, the method may further include a step for generating a scaled high frequency ripple compensation current estimate based on the high frequency ripple compensation current. Based on the scaled high frequency ripple compensation current estimate, the method may form a feedback signal, which is provided to the switch mode power supply converter. The switch mode power supply converter may adjust the switching output voltage based on the feedback signal. In some embodiments, the switch mode power supply converter is configured to be a buck converter. Alternatively, in other embodiments, the switch mode power supply converter is configured to be a multi-level charge pump buck converter.

›DETAILED DESCRIPTION · 3 of 67

Embodiments disclosed herein further relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier. One example embodiment of the pseudo-envelope follower power management system may include a switch mode power supply converter and a parallel amplifier cooperatively coupled to provide a linear RF power amplifier supply to a linear RF power amplifier. The pseudo-envelope follower power management system may include a charge pump configured to power the parallel amplifier. The charge pump may generate a plurality of output voltage levels. The charge pump may be either a boost charge pump or a boost/buck charge pump. The pseudo-envelope follower power management system may include an offset voltage control circuit configured to provide feedback to the switch mode power supply converter to regulate an offset voltage developed across a coupling device that couples the output of the parallel amplifier to the linear RF power amplifier supply.

The multi-level buck converter may include a supply input configured to receive a direct current (DC) voltage, a switching voltage output coupled to a power inductor, a switcher control circuit, a multi-level charge pump circuit having a control input, a charge pump supply input configured to receive the DC voltage, a series switch having a first switch terminal, a second switch terminal, and a series control terminal and a shunt switch having a first switch terminal, a second switch terminal, and a shunt control terminal. The first terminal of the series switch may be coupled to the supply input of the multi-level buck converter. The second terminal of the series switch may be coupled to the first terminal of the series switch to form a switching voltage output. The second terminal of the series switch may be coupled to ground. The boost charge pump circuit may include a charge pump control input, a charge pump supply input coupled to the supply input of the multi-level buck converter, and a charge pump output coupled to the supply input of the multi-level buck converter. The boost charge pump includes a plurality of switches and two flying capacitors that provide for three modes of operation. In a charging mode of operation, the flying capacitors are coupled in series between the charge pump supply input and ground, where the flying capacitors are switchably disconnected from the charge pump output. In a first boost mode of operation, the flying capacitors are arranged in parallel between the charge pump output and the charge pump supply input to generate a 1.5× the DC voltage output at the charge pump output. In a second boost mode of operation, the flying capacitors are arranged in series between the charge pump output and the charge pump supply input to generate a 2× the DC voltage output at the charge pump output. The multi-level buck converter may include four modes of operation. In a first mode of operation, the series switch is open, the boost charge pump is in the charging mode of operation, and the shunt switch is closed to generate zero volts at the switching voltage output. In a second mode of operation, the series switch is closed, the boost charge pump is in the charging mode of operation, and the shunt switch is open to generate the DC voltage output at the switching voltage output. In a third mode of operation, both the series switch and the shunt switch are open and the boost charge pump is in the first boost mode of operation to generate a 1.5× the DC voltage output at the switching mode output. In a fourth mode of operation, both the series switch and the shunt switch are open and the boost charge pump is in the second boost mode of operation to generate a 2× the DC voltage output at the switching mode output.

›DETAILED DESCRIPTION · 4 of 67

FIGS. 1A and 2A depict an example embodiment of pseudo-envelope follower power management system 10 A including a multi-level charge pump buck converter 12 , a parallel amplifier circuit 14 , a power inductor 16 , a coupling circuit 18 , and a bypass capacitor 19 . The bypass capacitor 19 has a bypass capacitor capacitance, C BYPASS . The multi-level charge pump buck converter 12 and the parallel amplifier circuit 14 may be configured to operate in tandem to generate a power amplifier supply voltage, V CC , at the power amplifier supply output 28 of the pseudo-envelope follower power management system 10 A for a linear RF power amplifier 22 . The power amplifier supply output 28 provides an output current, I OUT , to the linear RF power amplifier 22 . The linear RF power amplifier 22 may include a power amplifier input, P IN , configured to receive a modulated RF signal and a power amplifier output, P OUT , coupled to an output load, Z LOAD . As an example, the output load, Z LOAD , may be an antenna.

The multi-level charge pump buck converter 12 may include a supply input 24 , (V BAT ), configured to receive a direct current (DC) voltage, V BAT , from a battery 20 and a switching voltage output 26 configured to provide a switching voltage, V SW . The switching voltage output 26 may be coupled to the power amplifier supply output 28 by the power inductor 16 , where the power inductor 16 couples to a bypass capacitor 19 to form an output filter 29 for the switching voltage output 26 of the multi-level charge pump buck converter 12 . The power inductor 16 provides an inductor current, I SW — OUT , to the power amplifier supply output 28 . The parallel amplifier circuit 14 may include a parallel amplifier supply input 30 configured to receive the direct current (DC) voltage, V BAT , from the battery 20 , a parallel amplifier output 32 A, a first control input 34 configured to receive a V RAMP signal, and a second control input configured to receive the power amplifier supply voltage, V CC . The parallel amplifier output 32 A of the parallel amplifier circuit 14 may be coupled to the power amplifier supply voltage V CC , by a coupling circuit 18 . The parallel amplifier output voltage, V PARA — AMP , is provided by the parallel amplifier circuit 14 .

As an example, the parallel amplifier circuit 14 may generate the parallel amplifier output voltage, V PARA — AMP , based on the difference between the V RAMP signal and the power amplifier supply voltage, V CC . Thus, the V RAMP signal may represent either an analog or digital signal that contains the required supply modulation information for a power amplifier collector of a linear RF power amplifier. Typically, the V RAMP signal is provided to the parallel amplifier circuit 14 as a differential analog signal to provide common mode rejection against any noise or spurs that could appear on this signal. The V RAMP signal may be a time domain signal, V RAMP (t), generated by a transceiver or modem and used to transmit radio-frequency (RF) signals. For example, the V RAMP signal may be generated by a digital baseband processing portion of the transceiver or modem, where the digital V RAMP signal, V RAMP — DIGITAL , is digital-to-analog converted to form the V RAMP signal in the analog domain. In some embodiments, the “analog” V RAMP signal is a differential signal. The transceiver or a modem may generate the V RAMP signal based upon a known RF modulation Amp(t)*cos(2*pi*f RF *t+Phase(t)). The V RAMP signal may represent the target voltage for the power amplifier supply voltage, V CC , to be generated at the power amplifier supply output 28 of the pseudo-envelope follower power management system 10 A, where the pseudo-envelope follower power management system 10 A provides the power amplifier supply voltage, V CC , to the linear RF power amplifier 22 . Also the V RAMP signal may be generated from a detector coupled to the RF input power amplifier.

For example, the parallel amplifier circuit 14 includes a parallel amplifier output 32 A that provides a parallel amplifier output voltage, V PARA — AMP , to the coupling circuit 18 . The parallel amplifier output 32 A sources a parallel amplifier circuit output current, I PAWA — OUT , to the coupling circuit 18 . The parallel amplifier circuit 14 , depicted in FIG. 1A and FIG. 1B , may provide a parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , to the multi-level charge pump buck converter 12 as an estimate of the parallel amplifier circuit output current I PAWA — OUT , of the parallel amplifier circuit 14 . Thus, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , represents an estimate of the parallel amplifier circuit output current I PAWA — OUT , provided by the parallel amplifier circuit as a feedback signal to the multi-level charge pump buck converter 12 . Based on the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , multi-level charge pump buck converter 12 may be configured to control the switching voltage, V SW , provided at the switching voltage output 26 of the multi-level charge pump buck converter 12 .

In some embodiments of the pseudo-envelope follower power management system 10 A, depicted in FIG. 1A , and the pseudo-envelope follower power management system 10 B, depicted in FIG. 1B , the coupling circuit 18 may be an offset capacitor, C OFFSET . An offset voltage, V OFFSET , may be developed across the coupling circuit 18 . In other alternative embodiments, the coupling circuit may be a wire trace such that the offset voltage, V OFFSET , between the parallel amplifier output voltage, V PARA — AMP , and the power amplifier supply voltage output, V CC , is zero volts. In still other embodiments, the coupling circuit may be a transformer.

As an example, a pseudo-envelope follower power management system 10 A, depicted in FIG. 2A , is an example embodiment of the pseudo-envelope follower power management systems 10 , depicted in FIG. 1A . Unlike the pseudo-envelope follower power management systems 10 , depicted in FIG. 1A , the pseudo-envelope follower power management system 10 A depicted in FIG. 2A includes an embodiment of the multi-level charge pump buck converter 12 A and a parallel amplifier circuit 14 A having parallel amplifier circuitry 32 . The parallel amplifier circuitry 32 includes a parallel amplifier 35 and a parallel amplifier sense circuit 36 . The parallel amplifier circuit 14 A further includes a parallel amplifier output impedance compensation circuit 37 configured to receive a V RAMP : signal and provide a compensated V RAMP signal, V RAMP — C , as an input to the parallel amplifier 35 . The parallel amplifier circuit 14 A further includes a parallel amplifier output impedance compensation circuit 37 configured to receive the V RAMP signal and generate a compensated V RAMP signal, V RAMP — C , as a function of the V RAMP signal. The parallel amplifier 35 generates a parallel amplifier output current, I PARA — AMP , to produce a parallel amplifier output voltage, V PARA — AMP , at the parallel amplifier output 32 A based on the difference between the compensated V RAMP signal, V RAMP — C and the power amplifier supply voltage, V CC , generated at power amplifier supply output 28 . The parallel amplifier sense circuit 36 generates a scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , which is a fractional representation of the parallel amplifier output current, I PARA — AMP , generated by the parallel amplifier 35 . Alternatively, in those embodiments of the parallel amplifier circuit 14 that do not include the parallel amplifier output impedance compensation circuit 37 , the parallel amplifier 35 generates the parallel amplifier output current, I PARA — AMP , to product the parallel amplifier output voltage, V PARA — AMP , based on the difference between the V RAMP signal and the power amplifier supply voltage, V CC . The parallel amplifier circuit 14 A may further include an open loop assist circuit 39 configured to receive the feed forward control signal 38 , V SWITCHER , the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the V RAMP signal. In response to the feed forward control signal 38 , V SWITCHER , scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the V RAMP signal, the open loop assist circuit 39 may be configured to generate an open loop assist current, I ASSIST . The open loop assist current, I ASSIST , may be provided to the parallel amplifier output 32 A. The parallel amplifier output current, I PARA — AMP , generated by the parallel amplifier 35 and the open loop assist circuit current, I ASSIST , generated by the open loop assist circuit 39 may be combined to form the parallel amplifier circuit output current, I PAWA — OUT , of the parallel amplifier circuit 14 A. The parallel amplifier circuit 14 A may further include a V OFFSET loop circuit 41 , configured to generate a threshold offset current 42 , I THRESHOLD — OFFSET . The threshold offset current 42 , I THRESHOLD — OFFSET , may be provided from the parallel amplifier circuit 14 A as a feedback signal to the multi-level charge pump buck converter 12 A. The V OFFSET loop circuit 41 may be configured to provide a threshold offset current 42 , I THRESHOLD — OFFSET , as an estimate of the magnitude of the offset voltage, V OFFSET , appearing across the coupling circuit 18 . In those cases where the coupling circuit is a wire trace such that the offset voltage, V OFFSET , is always zero volts, the parallel amplifier circuit 14 A may not provide the threshold offset current 42 , I THRESHOLD — OFFSET , to the multi-level charge pump buck converter 12 A. An embodiment of the V OFFSET loop circuit 41 is depicted in FIG. 8 . In addition, another embodiment of the V OFFSET loop circuit 41 A, depicted in FIG. 18A and FIG. 18C , represents an alternative embodiment the V OFFSET loop circuit 41 depicted in FIGS. 2A , 2 B, 8 , 18 A, and 18 C. Moreover, as also described below, an alternative embodiment of a V OFFSET loop circuit 41 B, depicted FIG. 18B and FIG. 18D , represents an alternative embodiment of the V OFFSET loop circuit 41 depicted in FIGS. 2A , 2 B, 8 , 18 B, and 18 D. In addition, another example is the pseudo-envelope follower power management system 10 B, depicted in FIG. 2B , which is similar to the embodiment of the pseudo-envelope follower power management system 10 B, depicted in FIG. 1B . The pseudo-envelope follower power management system 10 B operationally and functionally similar in form and function to the pseudo-envelope follower power management system 10 A, depicted in FIG. 2A . However, unlike the pseudo-envelope follower power management system 10 A depicted in FIG. 2A , the pseudo-envelope follower power management system 10 B includes a multi-level charge pump buck converter 12 B configured to generate an estimated switching voltage output 38 B, V SW — EST , and a parallel amplifier circuit 14 B configured to receive the estimated switching voltage output 38 B, V SW — EST , instead of the feed forward control signal 38 , V SWITCHER . Consequentially, as depicted in FIG. 2B , the open loop assist circuit 39 of the parallel amplifier circuit 14 B in configured to use only the estimated switching voltage output 38 B, V SW — EST , instead of the feed forward control signal 38 , V SWITCHER .

›DETAILED DESCRIPTION · 5 of 67

The generation of the feed forward control signal 38 , V SWITCHER , depicted in FIGS. 1A and 2A , will now be explained with reference to FIG. 3A . As an example, the multi-level charge pump buck converters 12 and 12 A may each be configured to generate a feed forward control signal 38 , V SWITCHER , to provide an indication of the output state of the switching voltage output 26 to the parallel amplifier circuit 14 . As an example, FIG. 3A depicts an embodiment of the switcher control circuit 52 , depicted in FIG. 2A , as a switcher control circuit 52 A. In FIG. 3A , the feed forward control signal 38 , V SWITCHER , is provided by a switch 43 . The switch 43 may be configured by the V SWITCHER — CONTROL signal to provide either an indication of the switching voltage output, V SW , from the threshold detector and control circuit 132 A or a scaled version of the switching voltage output, V SW , from the scalar circuit as the feed forward control signal 38 , V SWITCHER . The threshold detector and control circuit 132 A may generate an estimated switching voltage output 38 B, V SW — EST , based on the state of the switcher control circuit 52 A, where the estimated switching voltage output 38 B, V SW — EST , provides an indication of the switching voltage output, V SW , based on the state of the switcher control circuit 52 A. Due to propagation delay within the switcher control circuit 52 A, the multilevel-charge pump circuit 56 and the switching circuit 58 of the multi-level charge pump buck converter 12 A, the indication of the switching voltage output, V SW , based on the state of the switcher control circuit 52 A is a feed forward signal that indicates what the voltage level of the switching voltage output, V SW , at the switching voltage output 26 will be based on the state of the switcher control circuit 52 A instead of the current voltage level of the switching voltage output, V SW , at the switching voltage output 26 . Thus, the estimated switching voltage output 38 B, V SW — EST , may provide an early indication what the voltage level of the switching voltage output, V SW , will be in the future instead of the present voltage level of the switching voltage output, V SW , at the switching voltage output 26 . In contrast, the scalar circuit may generate a scaled switching voltage output 38 A, V SW — SCALED , by scaling the switching voltage output 26 , V SW , where the scaled switching voltage output 38 A, V SW — SCALED , provides a scaled version of the switching voltage output, V SW . Thus, the scaled switching voltage output 38 A, V SW — SCALED , is a scaled version of the voltage level currently at the switching voltage output 26 instead of a future voltage level. Accordingly, the switch 43 may be configured such that the feed forward control signal 38 , V SWITCHER , provides either the estimated switching voltage output 38 B, V SW — EST , or the scaled switching voltage output 38 A, V SW — SCALED , as the feed forward control signal 38 , V SWITCHER .

Another embodiment of the pseudo-envelope follower power management system 10 B, as depicted in FIG. 1B , is described with reference to FIG. 3B . As depicted in FIG. 1B , the multi-level charge pump buck converter 12 B may be configured to provide both a scaled switching voltage output 38 A, V SW — SCALED , and an estimated switching voltage output 38 B, V SW — EST , to the parallel amplifier circuit 14 B. As still another example, the pseudo-envelope follower power management system 10 B depicted in FIG. 2B may be configured to only provide the estimated switching voltage output 38 B, V SW — EST , as a feed forward signal to the parallel amplifier circuit 14 B.

The generation of the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , depicted in FIGS. 1A and 1B will now be described with continuing reference to the embodiment of the parallel amplifier circuit 14 A, depicted in FIG. 2A , and the embodiment of the parallel amplifier circuit 14 B depicted in FIG. 2B . Embodiments of the parallel amplifier circuit 14 A and the parallel amplifier circuit 14 B, depicted in FIGS. 2A and 2B , may provide the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , where the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , includes a scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and a scaled open loop assist circuit output current estimate, I ASSIST — SENSE . The scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is a scaled estimate of the parallel amplifier output current, I PARA — AMP , generated by the parallel amplifier sense circuit 36 of the parallel amplifier circuitry 32 . In some alternative embodiments, the parallel amplifier 35 may generate the scaled estimate of the parallel amplifier output current, I PARA — AMP — SENSE , directly. The scaled open loop assist circuit current estimate, I ASSIST — SENSE , is a scaled estimate of the open loop assist circuit current, I ASSIST , generated by the open loop assist circuit 39 . In other alternative embodiments of the parallel amplifier circuit 14 depicted in FIG. 1A and FIG. 1B , the parallel amplifier circuit 14 does not include the open loop assist circuit 39 . In those embodiments of the parallel amplifier circuit 14 depicted in FIG. 1A and FIG. 1B that do not include the open loop assist circuit 39 , the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , may only be based on the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE .

Returning to FIGS. 1A and 1B , the pseudo-envelope follower power management systems 10 A and 10 B may further include a control bus 44 coupled to a controller 50 . The control bus 44 may be coupled to a control bus interface 46 of the multi-level charge pump buck converter 12 and the control bus interface 48 of the parallel amplifier circuit 14 . The controller 50 may include various logical blocks, modules, and circuits. The controller 50 may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices. As an example, a combination of computing devices may include a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. The controller may further include or be embodied in hardware and in computer executable instructions that are stored in memory, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium may be coupled to the processor such that a processor can read information from, and write information to, the storage medium. In the alternative, the storage medium or a portion of the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

›DETAILED DESCRIPTION · 6 of 67

FIGS. 2A and 2B depict a pseudo-envelope follower power management system 10 A and a pseudo-envelope follower power management system 10 B, respectively, that include embodiments of the multi-level charge pump buck converter 12 A and the multi-level charge pump buck converter 12 B. As depicted in FIGS. 2A and 2B , some embodiments of the multi-level charge pump buck converter 12 of FIGS. 1A and 1B may include an FLL circuit 54 configured to interoperate with a switcher control circuit 52 , as depicted in FIGS. 2A and 2B . Alternatively, some embodiments of the multi-level charge pump buck converter 12 A and the multi-level charge pump buck converter 12 B may not include an FLL circuit 54 or be configured to operate with the FLL circuit 54 being disabled.

As further depicted in FIGS. 2A and 2B , some embodiments of the switcher control circuit 52 may be configured to control the operation of the multi-level charge pump circuit 56 and the switching circuit 58 to generate the switching voltage, V SW , on the switching voltage output 26 of the multi-level charge pump buck converter 12 A or the multi-level charge pump buck converter 12 B, respectively. For example, the switcher control circuit 52 may use a charge pump mode control signal 60 to configure the operation of the multi-level charge pump circuit 56 to provide a charge pump output 64 to the switching circuit 58 . Alternatively, the switcher control circuit 52 may generate a series switch control signal 66 to configure the switching circuit 58 to provide the switching voltage, V SW , substantially equal to the DC voltage, V BAT , from the battery 20 via a first switching element coupled between the supply input 24 and the switching voltage output 26 . As another example, the switcher control circuit 52 may configure the switching circuit 58 to provide the switching voltage, V SW , through a second switching element coupled to ground such that the switching voltage, V SW , is substantially equal to ground.

In addition, the parallel amplifier circuit 14 A, depicted in FIG. 2A , and the parallel amplifier circuit 14 B, depicted in FIG. 2B , may be configured to provide the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and the threshold offset current 42 , I THRESHOLD — OFFSET , to the switcher control circuit 52 in order to control the operation of the switcher control circuit 52 . As discussed in detail below, some embodiments of the switcher control circuit 52 may be configured to receive and use the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , the threshold offset current 42 , I THRESHOLD — OFFSET , and/or a combination thereof to control the operation of the switcher control circuit 52 .

For example, the switcher control circuit 52 may use the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , the threshold offset current 42 , I THRESHOLD — OFFSET , and/or a combination thereof to determine the magnitude of the voltage provided the switching voltage, V SW , from the multi-level charge pump circuit 56 .

Some embodiments of the switcher control circuit 52 , depicted in FIG. 2A and FIG. 2B , may be configured to interoperate with an FLL circuit 54 . As an example, FIG. 3A depicts an example embodiment of a switcher control circuit 52 A configured to interoperate with an example embodiment of the FLL circuit 54 , which is depicted as FLL circuit 54 A. For the sake of clarity, and not by limitation, the description of the operation of the switcher control circuit 52 A and the FLL circuit 54 A will be done with continuing reference to the multi-level charge pump buck converter 12 A, depicted in FIG. 2A .

As depicted in FIG. 3A , some embodiments of the multi-level charge pump buck converter 12 A may include switcher control circuit 52 A, an embodiment of the frequency lock loop frequency lock loop (FLL) circuit 54 A, a multi-level charge pump circuit 56 , and the switching circuit 58 . The switcher control circuit 52 A may be in communication with the frequency lock loop (FLL) circuit 54 A. The frequency lock loop (FLL) circuit 54 A may be in communication with a clock reference 139 . The multi-level charge pump circuit 56 and the switching circuit 58 may be configured to receive the DC voltage, V BAT , from the supply input 24 of the multi-level charge pump buck converter 12 .

The clock reference 139 may provide a clock reference signal 139 A to the frequency lock loop (FLL) circuit 54 A. In addition, the switcher control circuit 52 A may provide a logic level indication of the switching voltage output, V SW — EST — OUT , to the frequency lock loop (FLL) circuit 54 A. The logic level indication of the switching voltage output, V SW — EST — OUT , is discussed relative to the logic circuit 148 A of FIG. 4A . In some embodiments of the multi-level charge pump buck converter 12 of FIGS. 1A and 1B , the multi-level charge pump buck converter 12 may not include the frequency lock loop (FLL) circuit 54 and a clock reference 139 , as depicted in FIGS. 3C and 3D .

The switcher control circuit 52 A may be configured to receive the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and the threshold offset current 42 , I THRESHOLD — OFFSET , from the parallel amplifier circuit 14 A. The switcher control circuit 52 A may provide a charge pump mode control signal 60 to the charge pump mode control input 62 of the multi-level charge pump circuit 56 . Based upon the charge pump mode control signal 60 , the multi-level charge pump circuit 56 may generate one of a plurality of output voltages or present an open circuit at the charge pump output 64 . The switcher control circuit 52 A may further provide a series switch control signal 66 and a shunt switch control signal 68 to the switching circuit 58 .

The switching circuit 58 may include a series switch 70 and a shunt switch 72 . The series switch 70 and the shunt switch 72 may be a solid state based switch such as a field effect transistor, an insulator-on-semiconductor based transistor, or a bipolar based transistor. The series switch 70 may include a first switch terminal 74 , a second switch terminal 76 , and a series switch control terminal 78 coupled to the series switch control signal 66 . The shunt switch 72 may include a first switch terminal 80 , a second switch terminal 82 , and a shunt switch control terminal 83 coupled to the shunt switch control signal 68 . The first switch terminal 74 of the series switch 70 may be coupled to the supply input 24 , (V BAT ), of the multi-level charge pump buck converters 12 and 12 A, as depicted in FIGS. 1A and 2A . The second switch terminal 76 of the series switch 70 may be coupled to the first switch terminal 80 of the shunt switch 72 and the charge pump output 64 to form the switching voltage output 26 . The second switch terminal 82 of the shunt switch 72 may be coupled to ground.

›DETAILED DESCRIPTION · 7 of 67

As depicted in FIG. 7A , with continuing reference to FIGS. 1A , 2 A and 3 A, the multi-level charge pump circuit 56 may include a charge pump control circuit 84 A, a plurality of switches including a first switch 86 , a second switch 88 , a third switch 90 , a fourth switch 92 , a fifth switch 94 , a sixth switch 96 and a seventh switch 98 , a first flying capacitor 100 having a first terminal 100 A and a second terminal 100 B, and a second flying capacitor 102 having a first terminal 102 A and a second terminal 102 B. As depicted in FIG. 7A , some alternative embodiments of the multi-level charge pump circuit 56 may further include an eighth switch 118 to advantageously provide an additional functional feature, described below. Each of the first switch 86 , the second switch 88 , the third switch 90 , the fourth switch 92 , the fifth switch 94 , the sixth switch 96 , the seventh switch 98 , and the alternatively included eighth switch 118 may be a solid state based switch implemented with field effect transistors, insulator-on-semiconductor based transistors, or bipolar based transistors, or a combination thereof. Each of the first switch 86 , the second switch 88 , the third switch 90 , the fourth switch 92 , the fifth switch 94 , the sixth switch 96 , the seventh switch 98 , and the alternatively included eighth switch 118 may be a solid state transmission gate. As another example, each of the first switch 86 , the second switch 88 , the third switch 90 , the fourth switch 92 , the fifth switch 94 , the sixth switch 96 , the seventh switch 98 , and the alternatively included eighth switch 118 may be based on a GaN process. Alternatively, each of the first switch 86 , the second switch 88 , the third switch 90 , the fourth switch 92 , the fifth switch 94 , the sixth switch 96 , the seventh switch 98 , and the alternatively included eighth switch 118 may be micro-electromechanical systems (MEMS) contact type switches.

The first switch 86 may be coupled between the first terminal 100 A of the first flying capacitor 100 and the charge pump output 64 . The first switch 86 may include a first switch control input configured to receive a first switch control signal 104 from the charge pump control circuit 84 A, where the first switch control signal 104 operably opens and closes the first switch 86 based upon the charge pump mode control signal 60 . The second switch 88 may be coupled between the first terminal 100 A of the first flying capacitor 100 and the supply input 24 , (V BAT ), of the multi-level charge pump buck converter 12 . The second switch 88 may include a second switch control input configured to receive a second switch control signal 106 from the charge pump control circuit 84 A, where the second switch control signal 106 operably opens and closes the second switch 88 based upon the charge pump mode control signal 60 . The third switch 90 may be coupled between the second terminal 100 B of the first flying capacitor 100 and the supply input 24 , (V BAT ), of the multi-level charge pump buck converter 12 . The third switch 90 may include a third switch control input configured to receive a third switch control signal 108 from the charge pump control circuit 84 A, where the third switch control signal 108 operably opens and closes the third switch 90 based upon the charge pump mode control signal 60 . The fourth switch 92 may be coupled between the second terminal 100 B of the first flying capacitor 100 and the first terminal 102 A of the second flying capacitor 102 . The fourth switch 92 may include a fourth switch control input configured to receive a fourth switch control signal 110 from the charge pump control circuit 84 A, where the fourth switch control signal 110 operably opens and closes the fourth switch 92 based upon the charge pump mode control signal 60 . The fifth switch 94 may be coupled between the supply input 24 , (V BAT ), of the multi-level charge pump buck converter 12 and the second terminal 102 B of the second flying capacitor 102 . The fifth switch 94 may include a fifth switch control input configured to receive a fifth switch control signal 112 from the charge pump control circuit 84 A, where the fifth switch control signal 112 operably opens and closes the fifth switch 94 based upon the charge pump mode control signal 60 . The sixth switch 96 may be coupled between the second terminal 102 B of the second flying capacitor 102 and ground. The sixth switch 96 may include a sixth switch control input configured to receive a sixth switch control signal 114 from the charge pump control circuit 84 A, where the sixth switch control signal 114 operably opens and closes the sixth switch 96 based upon the charge pump mode control signal 60 . The seventh switch 98 may be coupled between the first terminal 102 A of the second flying capacitor 102 and the charge pump output 64 . The seventh switch 98 includes a seventh switch control input configured to receive a seventh switch control signal 116 from the charge pump control circuit 84 A, where the seventh switch control signal 116 operably opens and closes the seventh switch 98 based upon the charge pump mode control signal 60 .

Based upon the charge pump mode control signal 60 received at the charge pump control circuit 84 A, the charge pump control circuit 84 A may configure each of the first switch 86 , the second switch 88 , the third switch 90 , the fourth switch 92 , the fifth switch 94 , the sixth switch 96 , the seventh switch 98 , and the alternatively included eighth switch 118 to place the first flying capacitor 100 and the second flying capacitor 102 in various arrangements in order to place the multi-level charge pump circuit 56 in various modes of operation. As an example, the multi-level charge pump circuit 56 may have a charging mode to charge the first flying capacitor 100 and the second flying capacitor 102 , a first boost mode to provide 1.5×V BAT at the charge pump output 64 , and a second boost mode to provide 2×V BAT at the charge pump output 64 . Some alternative embodiments of the multi-level charge pump circuit 56 may further include an eighth switch 118 , the operation of which is discussed below with respect to providing a first output mode of operation.

›DETAILED DESCRIPTION · 8 of 67

As an example, in response to receipt of the charge pump mode control signal 60 that indicates the multi-level charge pump circuit 56 should be in the charging mode of operation, the charge pump control circuit 84 A configures the first flying capacitor 100 and the second flying capacitor 102 to be coupled in series between the supply input 24 , (V BAT ), of the multi-level charge pump buck converter 12 and ground, where the first flying capacitor and the second flying capacitor may be switchably disconnected from the charge pump output 64 . Assuming that the capacitance of the first flying capacitor 100 and the second flying capacitor 102 are equal, the first flying capacitor 100 and the second flying capacitor 102 each charge to a charged voltage of ½×V BAT . The charge pump control circuit 84 A configures the first switch 86 to be open, the second switch 88 to be closed, the third switch 90 to be open, the fourth switch 92 to be closed, the fifth switch 94 to be open, the sixth switch 96 to be closed, and the seventh switch 98 to be open. In those embodiments of the multi-level charge pump circuit 56 that further include the eighth switch 118 , the eighth switch 118 may be configured to be open.

In response to receipt of the charge pump mode control signal 60 that indicates the multi-level charge pump circuit 56 should be in the first boost mode of operation, the charge pump control circuit 84 A configures the first flying capacitor 100 and the second flying capacitor 102 to be arranged in parallel between the charge pump output 64 and the supply input 24 , (V BAT ), to generate 1.5×V BAT at the charge pump output. The charge pump control circuit 84 A configures the first switch 86 to be closed, the second switch 88 to be open, the third switch 90 to be closed, the fourth switch 92 to be open, the fifth switch 94 to be closed, the sixth switch 96 to be open, and the seventh switch 98 to be closed. In those embodiments of the multi-level charge pump circuit 56 that further include the eighth switch 118 , the eighth switch 118 may be configured to be open.

In response to receipt of the charge pump mode control signal 60 that indicates the multi-level charge pump circuit 56 should be in the second boost mode of operation, the charge pump control circuit 84 A configures the first flying capacitor 100 and the second flying capacitor 102 to be arranged in series between the charge pump output 64 and the supply input 24 , (V BAT ), to generate 2×V BAT at the charge pump output 64 . The charge pump control circuit 84 A configures the first switch 86 to be closed, the second switch 88 to be open, the third switch 90 to be open, the fourth switch 92 to be closed, the fifth switch 94 to be closed, the sixth switch 96 to be open, and the seventh switch 98 to be open. In those embodiments of the multi-level charge pump circuit 56 that further include the eighth switch 118 , the eighth switch 118 may be configured to be open.

As discussed above, some embodiments of the multi-level charge pump circuit 56 may further include an eighth switch 118 coupled between the second terminal 100 B of the first flying capacitor 100 and ground in order to provide for a first output mode of operation. The eighth switch 118 may include an eighth switch control input configured to receive an eighth switch control signal 120 from the charge pump control circuit 84 A, where the eighth switch control signal 120 operably opens and closes the eighth switch 118 based upon the charge pump mode control signal 60 .

In the first output mode of operation, the multi-level charge pump circuit 56 may provide ½×V BAT at the charge pump output 64 . In response to receipt of the charge pump mode control signal 60 that indicates the multi-level charge pump circuit 56 should be in the first output mode of operation, the charge pump control circuit 84 A configures the first flying capacitor 100 and the second flying capacitor 102 to be coupled in parallel between the charge pump output 64 and ground. The charge pump control circuit 84 A configures the first switch 86 to be closed, the second switch 88 to be open, the third switch 90 to be open, the fourth switch 92 to be open, the fifth switch 94 to be open, the sixth switch 96 to be closed, the seventh switch 98 to be closed and the eighth switch 118 to be closed.

Otherwise, the charge pump control circuit 84 A configures the eighth switch 118 to be open when the multi-level charge pump circuit 56 is in the charging mode of operation, the first boost mode of operation, or the second boost mode of operation.

FIG. 7B depicts an embodiment of a multi-level charge pump circuit 258 , depicted in FIGS. 18A and 18B , as multi-level charge pump circuit 258 A. The multi-level charge pump circuit 258 A is similar to the multi-level charge pump circuit 56 except the multi-level charge pump circuit 258 A further includes a ninth switch 119 configured to provide an internal charge pump node parallel amplifier supply 294 as an additional output. The ninth switch 119 may be similar to the plurality of switches including the first switch 86 , the second switch 88 , the third switch 90 , the fourth switch 92 , the fifth switch 94 , the sixth 96 , the seventh switch 98 , and eighth switch 118 of FIG. 7A . In addition, the multi-level charge pump circuit 258 A is similar to the multi-level charge pump circuit 56 except that the charge pump control circuit 84 A is replaced by a charge pump control circuit 84 B. Unlike the charge pump control circuit 84 A, the charge pump control circuit 84 B further includes a ninth switch control signal 121 configured to control the ninth switch 119 .

The ninth switch 119 may include a ninth switch control input configured to receive a ninth switch control signal 121 from the charge pump control circuit 84 B, where the ninth switch control signal 121 operably opens and closes the ninth switch 119 based upon the charge pump mode control signal 60 . The ninth switch may be operably coupled between the first terminal 102 A of the second flying capacitor 102 and the internal charge pump node parallel amplifier supply 294 .

›DETAILED DESCRIPTION · 9 of 67

Operationally, the charge pump control circuit 84 B functions similar to the operation of the charge pump control circuit 84 A. As an example, the multi-level charge pump circuit 258 A may have a charging mode to charge the first flying capacitor 100 and the second flying capacitor 102 , a first boost mode to provide 1.5×V BAT at the charge pump output 64 , and a second boost mode to provide 2×V BAT at the charge pump output 64 . However, unlike the charge pump control circuit 84 A, the charge pump control circuit 84 B is configured to operably close the ninth switch 119 when the multi-level charge pump circuit 258 A is configured to operate in either the first boost mode to provide 1.5×V BAT at the charge pump output 64 or the second boost mode to provide 2×V BAT at the charge pump output 64 . Thus, when the ninth switch 119 is in a closed state during either the first boost mode of operation or the second boost mode of operation, the voltage appearing on the first terminal 102 A of the second flying capacitor 102 , is substantially equal to 1.5×V BAT . Advantageously, the configuration of the multi-level charge pump circuit 258 A provides the same voltage output level to the internal charge pump node parallel amplifier supply 294 , which may improve the ripple noise on the power amplifier supply voltage V CC .

FIG. 7C depicts another embodiment of a multi-level charge pump circuit 258 , depicted in FIGS. 18A and 18B , as multi-level charge pump circuit 258 B. The multi-level charge pump circuit 258 B is similar to the multi-level charge pump circuit 258 A of FIG. 7B except the ninth switch may be operably coupled between the first terminal 100 A of the first flying capacitor 100 and the internal charge pump node parallel amplifier supply 294 .

Operationally, the charge pump control circuit 84 C functions similar to the operation of the charge pump control circuit 84 B. As an example, like the multi-level charge pump circuit 258 A, the multi-level charge pump circuit 258 B may have a charging mode to charge the first flying capacitor 100 and the second flying capacitor 102 , a first boost mode to provide 1.5×V BAT at the charge pump output 64 , and a second boost mode to provide 2×V BAT at the charge pump output 64 . In addition, like the charge pump control circuit 84 B, the charge pump control circuit 84 C is configured to operably close the ninth switch 119 when the multi-level charge pump circuit 258 B is configured to operate in either the first boost mode to provide 1.5×V BAT at the charge pump output 64 or the second boost mode to provide 2×V BAT at the charge pump output 64 . Thus, when the ninth switch 119 is in a closed state during either the first boost mode of operation or the second boost mode of operation, the voltage appearing on the first terminal 100 A of the first flying capacitor 100 may depend upon whether the multi-level charge pump circuit 258 B is configured to operate in the first boost mode or the second boost mode. For example, due to the topological location of the first flying capacitor, the voltage output level provided to the internal charge pump node parallel amplifier supply 294 may be 1.5×V BAT when the multi-level charge pump circuit 258 B is configured to operate in the first boost mode and 2.0×V BAT when the multi-level charge pump circuit 258 B is configured to operate in the second boost mode. As a result, advantageously, the multi-level charge pump circuit 258 B may provide a higher power supply rail for the parallel amplifier 35 of FIGS. 18A and 18B . In particular, in the case where the parallel amplifier 35 of FIGS. 18A and 18B is a rechargeable parallel amplifier, similar to the rechargeable parallel amplifier 35 E of FIG. 12E and the rechargeable parallel amplifier 35 F of FIG. 12F , the saved charge voltage, V AB on the charge conservation capacitor, C AB , may be increased and result in a larger range of operation of the second output stage, as depicted in FIGS. 12E and 12F .

In those embodiments that further provide a first output threshold parameter (not shown), the first output threshold parameter may correspond to a first output mode of operation of the multi-level charge pump buck converter 12 . In the first output mode of operation, both the series switch 70 and the shunt switch 72 are open and the multi-level charge pump circuit 56 is in the first output mode of operation to generate a ½×V BAT at the switching voltage output 26 .

Returning to FIG. 3A , for the sake of clarity and not by way of limitation, the following discussion of the operation of the circuits depicted in FIG. 3A will be done with continuing reference to the multi-level charge pump buck converter 12 A depicted in FIG. 2A . As depicted in FIG. 3A , the switcher control circuit 52 A may include a programmable threshold circuit 122 configured to receive a plurality of programmable threshold levels and one embodiment of a threshold detector and control circuit 132 A. The programmable threshold levels may be received from a controller 50 via the control bus 44 . As an example, in some embodiments, the controller 50 may provide a shunt level threshold parameter, a series level threshold parameter, a first boost level threshold parameter, and a second boost level threshold parameter. In another embodiment, the controller 50 may further provide a first output threshold parameter.

As an example, each of the threshold levels may correspond to one of a plurality of output modes of the multi-level charge pump buck converter 12 A. As an example, the shunt level threshold parameter may correspond to a shunt output mode of operation. In a shunt output mode of operation of the multi-level charge pump buck converter 12 A, the series switch 70 is open (not conducting), the multi-level charge pump circuit 56 is in the charging mode of operation, and the shunt switch 72 is closed (conducting) to generate zero volts at the switching voltage output 26 . The shunt output mode of operation provides a conduct path for current to continue flowing through the power inductor 16 when the multi-level charge pump circuit 56 is in the charging mode of operation and the series switch 70 is open (not conducting). The series level threshold parameter may correspond to a shunt output mode of operation of the multi-level charge pump buck converter 12 A. In a series output mode of operation, the series switch 70 is closed (conducting), the multi-level charge pump circuit 56 is in the charging mode of operation, and the shunt switch 72 is open to generate V BAT at the switching voltage output 26 . The first boost level threshold parameter may correspond to a first boost output mode of operation of the multi-level charge pump buck converter 12 A. In the first boost output mode of operation, both the series switch 70 and the shunt switch 72 are open and the multi-level charge pump circuit 56 is in the first boost mode of operation to generate 1.5×V BAT at the switching voltage output 26 . The second boost level threshold parameter may correspond to a second boost output mode of operation of the multi-level charge pump buck converter 12 A. In a second boost output mode of operation, both the series switch 70 and the shunt switch 72 are open and the multi-level charge pump circuit 56 is in the second boost mode of operation to generate a 2×V BAT at the switching voltage output 26 .

›DETAILED DESCRIPTION · 10 of 67

Based upon the shunt level threshold parameter, the series level threshold parameter, the first boost level threshold parameter, and the second boost level threshold parameter, the programmable threshold circuit 122 generates a shunt level threshold 124 , a series level threshold 126 , a first boost level threshold 128 , and a second boost level threshold 130 , respectively, which are provided to the threshold detector and control circuit 132 A. In those embodiments that provide for a first output threshold parameter and a first output mode of operation of the multi-level charge pump circuit 56 , the programmable threshold circuit 122 may further generate a first output threshold (not shown), which is provided to the threshold detector and control circuit 132 A. As depicted in FIG. 3A , the shunt level threshold 124 , the series level threshold 126 , the first boost level threshold 128 , the second boost level threshold 130 and the first output threshold may be represented by a current level for use with a current comparator. In alternative embodiments, programmable threshold circuit 122 may be configured to generate the shunt level threshold 124 , the series level threshold 126 , the first boost level threshold 128 , the second boost level threshold 130 and the first output threshold as voltage levels to be used in conjunction with voltage comparator circuits.

The switcher control circuit 52 A may also receive a mode switch control signal 131 from the controller 50 . The mode switch control signal 131 may configure the threshold detector and control circuit 132 A to operate the multi-level charge pump buck converter 12 A in different modes of operation. As an example, the mode switch control signal 131 may configure operation of a state machine within the threshold detector and control circuit 132 A that governs how the switching voltage output 26 transitions the switching voltage output 26 to provide different output levels. As a first example embodiment of a state machine within the threshold detector and control circuit 132 A, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 A to operate in a first mode of operation, depicted in FIG. 5A . As another example embodiment of a state machine within the threshold detector and control circuit 132 A, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 A to operate in a second mode of operation, depicted in FIG. 6A .

Continuing with FIG. 3A , the switcher control circuit 52 A may further include a multiplier circuit 134 and a summing circuit 136 . The multiplier circuit may be configured to receive the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and a threshold scalar 137 A from the threshold detector and control circuit 132 A. The threshold scalar 137 A may be provided by FLL circuit 54 A, which is one embodiment of the frequency lock loop (FLL) circuit 54 depicted in FIG. 2A .

The FLL circuit 54 A receives a clock reference signal 139 A from a clock reference 139 and a logic level indication of the switching voltage output, V SW — EST — OUT . The FLL circuit 54 A extracts the operating frequency of the multi-level charge pump buck converter 12 A based upon the logic level indication of the switching voltage output, V SW — EST — OUT . Thereafter, the FLL circuit 54 A compares the extracted operating frequency of the multi-level charge pump buck converter 12 A to the clock reference signal 139 A to generate the threshold scalar 137 A. The magnitude of the threshold scalar 137 A may be used to adjust the operating frequency of the multi-level charge pump buck converter 12 A. In some embodiments (not shown), the FLL circuit 54 A may provide the threshold scalar 137 A directly to the multiplier circuit 134 .

The multiplier circuit 134 may multiply the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , by the threshold scalar 137 A to generate a scaled parallel amplifier output current estimate 138 . The scaled parallel amplifier output current estimate 138 is provided to the summing circuit 136 . The summing circuit 136 subtracts the threshold offset current 42 , I THRESHOLD — OFFSET , from the scaled parallel amplifier output current estimate 138 to generate a compensated parallel amplifier circuit output current estimate, I PAWA — COMP , which may be used as a composite feedback signal for the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 as depicted, for example, in FIG. 4A . In those embodiments of the parallel amplifier circuit 14 that do not include the V OFFSET loop circuit 41 , the threshold offset current 42 , I THRESHOLD — OFFSET , and summing circuit 136 are omitted.

The scaled parallel amplifier output current estimate 138 may be used to control the operating frequency of the multi-level charge pump buck converter 12 A by increasing or decreasing the magnitude of the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST . As an example, the FLL circuit 54 A may be configured to increase the magnitude of the threshold scalar 137 A to increase the magnitude of the scaled parallel amplifier output current estimate 138 . As the magnitude of the scaled parallel amplifier output current estimate 138 increases, the operating frequency of the multi-level charge pump buck converter 12 A will tend to also increase, which will tend to increase the power inductor current, I SW — OUT , delivered by the power inductor 16 . The FLL circuit 54 A may be further be configured to decrease the magnitude of the threshold scalar 137 A to decrease the magnitude of the scaled parallel amplifier output current estimate 138 . As the magnitude of the scaled parallel amplifier output current estimate 138 decreases, the magnitude of the scaled parallel amplifier output current estimate 138 , will tend to decrease the operating frequency of the multi-level charge pump buck converter 12 A. As the operating frequency of the multi-level charge pump buck converter 12 A decreases, the power inductor current, I SW — OUT , delivered by the power inductor 16 , tends to decrease. The threshold offset current 42 , I THRESHOLD — OFFSET , may be used to control the offset voltage, V OFFSET , which appears across the coupling circuit 18 , depicted in FIG. 2A .

›DETAILED DESCRIPTION · 11 of 67

FIG. 8 depicts the V OFFSET loop circuit 41 that generates the threshold offset current, I THRESHOLD — OFFSET . Returning to FIG. 3A , as the threshold offset current, I THRESHOLD — OFFSET , increases above zero current, the value magnitude of the compensated parallel amplifier circuit output current estimate, I PAWA — COMP — EST , is reduced, which tends to lower the output frequency of the multi-level charge pump buck converter 12 A. As the output frequency of the multi-level charge pump buck converter 12 A is decreased, the power inductor current, I SW — OUT , delivered by the power inductor 16 will also decrease. As the power inductor current, I SW — OUT , delivered by the power inductor 16 decreases, the offset voltage, V OFFSET , also decreases because the parallel amplifier circuit output current, I PAWA — OUT , tends to become positive to compensate for the reduction of the power inductor current, I SW — OUT . As the threshold offset current, I THRESHOLD — OFFSET , decreases below zero current, the value magnitude of the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is increased, and as a result, the output frequency, also referred to as switching frequency, of the multi-level charge pump buck converter 12 A tends to increase. As the output frequency of the multi-level charge pump buck converter 12 A is increased, the power inductor current, I SW — OUT , delivered by the power inductor 16 increases. As the power inductor current, I SW — OUT , increases, the offset voltage, V OFFSET , also tends to increase because the parallel amplifier circuit output current, I PAWA — OUT , tends to become negative to absorb the increase of the power inductor current, I SW — OUT .

As depicted in FIG. 4A , with continuing reference to FIGS. 2A and 3A , the threshold detector and control circuit 132 A of the switcher control circuit 52 A includes a first comparator 140 , a second comparator 142 , a third comparator 144 , a fourth comparator 146 , and a logic circuit 148 A. The example embodiment of the logic circuit 148 A may include a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof. Some embodiments of the logic circuit 148 A may be implemented in either a digital or analog processor. As depicted in FIG. 4A , the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 may be configured as current comparators. However, in some alternative embodiments, the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 may be configured as voltage comparator circuits, where the input currents provided as inputs to the positive terminal and the negative terminal of each respective one of the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 is first converted to a voltage level.

The first comparator 140 includes a positive terminal coupled to the shunt level threshold 124 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , and a first comparator output configured to generate a shunt level indication 150 A, which is provided to the logic circuit 148 A. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the shunt level threshold 124 , the shunt level indication 150 A is asserted by setting output of the first comparator 140 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the shunt level threshold 124 , the shunt level indication 150 A is de-asserted by setting output of the first comparator 140 to a digital logic high state. The second comparator 142 includes a positive terminal coupled to the series level threshold 126 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , and a second comparator output configured to generate a series level indication 152 A, which is provided to the logic circuit 148 A. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the series level threshold 126 , the series level indication 152 A is asserted by setting output of the second comparator 142 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the series level threshold 126 , the series level indication 152 A is de-asserted by setting output of the second comparator 150 to a digital logic high state. The third comparator 144 includes a positive terminal coupled to the first boost level threshold 128 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , and a third comparator output configured to generate a first boost level indication 154 A, which is provided to the logic circuit 148 A. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than the first boost level threshold 128 , the first boost level indication 154 A is asserted by setting output of the third comparator 144 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the first boost level threshold 128 , the first boost level indication 154 A is de-asserted by setting output of the third comparator 144 to a digital logic high state. The fourth comparator 146 includes a positive terminal coupled to the second boost level threshold 130 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , and a fourth comparator output configured to generate a second boost level indication 156 A, which is provided to the logic circuit 148 A. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than the second boost level threshold 130 , the second boost level indication 156 A is asserted by setting output of the fourth comparator 146 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the second boost level threshold 130 , the second boost level indication 156 A is de-asserted by setting output of the first comparator 146 to a digital logic high state.

›DETAILED DESCRIPTION · 12 of 67

The threshold detector and control circuit 132 A may further include a first output buffer 158 , a second output buffer 160 , and a third output buffer 161 . The logic circuit 148 A may provide a charge pump mode control signal 60 , a series switch control output 162 , a provides a shunt switch control output 164 , and a one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s). The logic circuit 148 A generates the series switch control output 162 to drive the first output buffer 158 , which provides the series switch control signal 66 to the series switch 70 . The logic circuit 148 A generates a shunt switch control output 164 to drive the second output buffer 160 , which provides the shunt switch control signal 68 to the shunt switch 72 . In addition, logic circuit 148 A generates the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), to drive the third output buffer 161 , which provide the estimated switching voltage output 38 B, V SW — EST . Each of the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), indicates a future output mode of the multi-level charge pump buck converter 12 A. In other words, the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s) are a feed forward signal that represents a state of the switcher control circuit 52 A that will be used to configure the multi-level charge pump buck converter 12 A to provide a future voltage level of the switching voltage, V SW , at the switching voltage output 26 . In other words, due to delays in the switcher control circuit 52 A, the multi-level charge pump circuit 56 , and the switching circuit 58 , the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), may provide an early indication of what the switching voltage, V SW , at the switching voltage output 26 will become before the voltage level at the switching voltage output 26 transitions to reflect the switching voltage, V SW , indicated by the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s). Based upon one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), the third output buffer 161 generates the estimated switching voltage output 38 B, V SW — EST . The third output buffer 161 is supplied by the DC voltage, V BAT , such that the output of the third output buffer 161 does not exceed the DC voltage, V BAT .

FIG. 11A through FIG. 11F depict various waveforms that may be used to represent the estimated switching voltage output 38 B, V SW — EST . FIG. 11A depicts one embodiment of the estimated switching voltage output 38 B, V SW — EST , When the multi-level charge pump buck converter 12 A is in either the series output mode, the first boost output mode, or the second boost output mode, the third output buffer 161 outputs a boost/series mode level. Alternatively, when the multi-level charge pump buck converter 12 A is in the shunt output mode, the third output buffer 161 outputs a shunt mode level.

FIG. 11B depicts another embodiment of the estimated switching voltage output 38 B, V SW — EST . When the multi-level charge pump buck converter 12 A is in the series output mode, the third output buffer 161 generates a series level. When the multi-level charge pump buck converter 12 A is in either the first boost output mode or the second boost output mode, the third output buffer 161 outputs a boost mode level. Alternatively, when the multi-level charge pump buck converter 12 A is in the shunt output mode, the third output buffer 161 outputs a shunt mode level.

FIG. 11C depicts another embodiment of the estimated switching voltage output 38 B, V SW — EST . When the multi-level charge pump buck converter 12 A is in the series output mode, the third output buffer 161 generates a series level. When the multi-level charge pump buck converter 12 A is in the first boost output mode the third output buffer 161 generates a first boost level. When the multi-level charge pump buck converter 12 A is in the second boost output mode, the third output buffer 161 outputs a second boost mode level. Alternatively, when the multi-level charge pump buck converter 12 A is in the shunt output mode, the third output buffer 161 outputs a shunt mode level.

FIG. 11D depicts another embodiment of the estimated switching voltage output 38 B, V SW — EST , for the case where the multi-level charge pump circuit 56 includes a first output mode of operation. When the multi-level charge pump buck converter 12 A is in the first output mode of operation, the third output buffer 161 generates a first output level. When the multi-level charge pump buck converter 12 A is in the series output mode, the third output buffer 161 generates a series level. When the multi-level charge pump buck converter 12 A is in the first boost output mode, the third output buffer 161 generates a first boost level. When the multi-level charge pump buck converter 12 A is in the second boost output mode, the third output buffer 161 outputs a second boost mode level. Alternatively, when the multi-level charge pump buck converter 12 A is in the shunt output mode, the third output buffer 161 outputs a shunt level.

FIG. 11E depicts another embodiment of the estimated switching voltage output 38 B, V SW — EST , for the case where the multi-level charge pump circuit 56 includes a first output mode of operation. When the multi-level charge pump buck converter 12 A is in the first output mode of operation, the third output buffer 161 generates a first output level. However, when the multi-level charge pump buck converter 12 A is in either the series output mode, the first boost output mode, or the second boost output mode, the third output buffer 161 generates a boost/series level. Alternatively, when the multi-level charge pump buck converter 12 A is in the shunt output mode, the third output buffer 161 outputs a shunt mode level.

›DETAILED DESCRIPTION · 13 of 67

FIG. 11F depicts another embodiment of the estimated switching voltage output 38 B, V SW — EST , for the case where the multi-level charge pump circuit 56 includes a first output mode of operation. When the multi-level charge pump buck converter 12 A is in either the series output mode, the first boost mode, or the second boost mode, the third output buffer 161 generates a boost/series level. Alternatively, when the multi-level charge pump buck converter 12 A is in either the first output mode of operation or the shunt output mode, the third output buffer 161 outputs a shunt level.

FIG. 8 depicts an embodiment of the V OFFSET loop circuit 41 , depicted in FIGS. 2A and 2B . The embodiment of the V OFFSET loop circuit 41 , depicted in FIG. 8 , generates the threshold offset current 42 , I THRESHOLD — OFFSET , based upon a calculated value of the offset voltage, V OFFSET , and a target offset voltage, V OFFSET — TARGET . For the sake of simplicity, and without limitation, the operation of the V OFFSET loop circuit 41 , depicted in FIG. 8 , will be done with continuing reference to FIG. 2A .

The target offset voltage, V OFFSET — TARGET , may be based upon a parameter provided by the controller 50 to the parallel amplifier circuit 14 .

The V OFFSET loop circuit 41 includes a first subtractor circuit, a second subtractor circuit, and an integrator circuit. The first subtractor circuit may be configured to receive the power amplifier supply voltage, V CC , and the parallel amplifier output voltage, V PARA — AMP . The first subtractor circuit subtracts the parallel amplifier output voltage, V PARA — AMP from the power amplifier supply voltage, V CC , to generate the offset voltage, V OFFSET , which appears across the coupling circuit 18 , depicted in FIG. 2A . The second subtractor circuit receives the offset voltage, V OFFSET , and the target offset voltage, V OFFSET — TARGET . The second subtractor circuit subtracts the target offset voltage, V OFFSET — TARGET , from the offset voltage, V OFFSET , to generate an offset error voltage, V OFFSET — ERROR , which is provided to the integrator circuit. The integrator circuit integrates the offset error voltage, V OFFSET — ERROR , to generate the threshold offset current 42 , I THRESHOLD — OFFSET , which is provided to the multi-level charge pump buck converter 12 A, depicted in FIG. 2A .

The operation of the logic circuit 148 A of FIG. 4A will now be discussed with continuing reference to FIGS. 2A , 3 A, 5 A, 6 A, and 7 A. The logic circuit 148 A may be digital or analog based logic configured for one or more state machines of the threshold detector and control circuit 132 A. As an example embodiment, the logic circuit 148 A ( FIG. 4A ) may have a first state machine corresponding to a first mode of operation of the multi-level charge pump buck converter 12 A, depicted in FIG. 5A , and a second state machine corresponding to a second mode of operation of the multi-level charge pump buck converter 12 A, depicted in FIG. 6A . Based on the mode switch control signal 131 received by the threshold detector and control circuit 132 A, the threshold detector and control circuit 132 A may configure the logic circuit 148 A to use the first state machine to govern operation of the multi-level charge pump buck converter 12 A using the first state machine of the logic circuit 148 A, depicted in FIG. 5A . Alternatively, the threshold detector and control circuit 132 A may configure the logic circuit 148 A to use the second state machine to govern operation of the multi-level charge pump buck converter 12 A using the second state machine of the logic circuit 148 A, depicted in FIG. 6A .

As depicted in FIG. 4A , the logic circuit 148 A may include a boost lockout counter 184 and a boost time counter 186 . The boost time counter 186 may be used to keep track of the time that the multi-level charge pump buck converter 12 A of FIG. 2A is in either the first boost output mode or the second output boost mode. When the multi-level charge pump buck converter 12 A is in either the first boost output mode or the second boost output mode, the multi-level charge pump circuit 56 ( FIG. 3A ) is configured to be in either the first boost mode of operation or the second boost mode of operation, respectively. In one embodiment of the logic circuit 148 A, when the logic circuit 148 A determines that the multi-level charge pump buck converter 12 A is in either the first boost output mode or the second output boost mode, the logic circuit 148 A resets the counter output of the boost time counter 186 and enables the boost time counter 186 to begin counting up. The logic circuit 148 A compares the counter output of the boost time counter 186 to a maximum boost time parameter, which may be provided by the controller 50 . If the counter output of the boost time counter 186 is equal to or exceeds the maximum boost time parameter before the multi-level charge pump buck converter 12 A is configured to return to either the shunt output mode of operation or the series output mode of operation, the logic circuit 148 A asserts a minimum charge time indicator. However, if the multi-level charge pump buck converter 12 A returns to either the series output mode of operation or the shunt output mode of operation while the counter output of the boost time counter 186 is less than the maximum boost time parameter, the logic circuit 148 A de-asserts the minimum charge time indicator.

The boost lockout counter 184 may be a count-down timer that is used to ensure that the multi-level charge pump circuit 56 of FIGS. 2A and 3A remains in a charging mode of operation for a minimum charge time period after the multi-level charge pump circuit 56 has been in either the first boost mode of operation or the second boost mode of operation. This permits the first flying capacitor 100 and the second flying capacitor 102 , of FIG. 7A , a sufficient amount of time to charge before the multi-level charge pump circuit 56 transitions again into either the first boost mode of operation or the second boost mode of operation. The minimum charge time period may be a parameter provided by the controller 50 via the control bus 44 , as depicted in FIG. 1A . Operationally, after the multi-level charge pump buck converter 12 A transitions from either the first boost output mode or the second boost output mode to either the shunt output mode of operation or the series output mode of operation, the logic circuit 148 A determines whether the minimum charge time indicator is asserted. If the minimum charge time indicator is asserted, the logic circuit 148 A sets the count value of the boost lockout counter 184 to an equal minimum charge time period and enables the boost lockout counter 184 to begin counting down. Once the boost lockout counter 184 counts down to zero, the logic circuit 148 A is configured to de-assert the minimum charge time indicator.

›DETAILED DESCRIPTION · 14 of 67

Operation of the first state machine implemented in the logic circuit 148 A, which is depicted in FIG. 5A , will now be described. The first state machine includes a shunt output mode 188 A, a series output mode 190 A, a first boost output mode 192 A, and a second boost output mode 194 A.

In the shunt output mode 188 A, the logic circuit 148 A ( FIG. 4A ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3A ) is in an open state (not conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in a closed state (conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 2A ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to ground. In response to assertion of the series level indication 152 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the series level threshold 126 , the logic circuit 148 A configures the first state machine to transition to the series output mode 190 A. Otherwise the state machine remains in the shunt output mode 188 A.

In the series output mode 190 A, the logic circuit 148 A configures the series switch control output 162 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT .

In response to de-assertion of the shunt level indication 150 A ( FIG. 4A ), which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the shunt level threshold 124 , the logic circuit 148 A configures the first state machine to transition to the shunt output mode 188 A ( FIG. 5A ). However, in response to assertion of the first boost level indication 154 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the first boost level threshold 128 , the logic circuit 148 A configures the first state machine to transition to the desired voltage level of the power amplifier supply voltage V CC , that correspond to the first boost output mode 192 A. Otherwise, the first state machine remains in the series output mode 190 A.

In the first boost output mode 192 A, the logic circuit 148 A ( FIG. 4A ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3A ) is in an open state (not conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the shunt level indication 150 A ( FIG. 4A ), which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the shunt level threshold 124 , the logic circuit 148 A configures the first state machine to transition to the shunt output mode 188 A ( FIG. 5A ). However, in response to assertion of the second boost level indication 156 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the second boost level threshold 130 , the logic circuit 148 A configures the first state machine to transition to the second boost output mode 194 A. Otherwise, the first state machine remains in the first boost output mode 192 A.

In the second boost output mode 194 A, the logic circuit 148 A ( FIG. 4A ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3A ) is in an open state (not conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT . In response to de-assertion of the shunt level indication 150 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the shunt level threshold 124 , the first state machine transitions to the shunt output mode 188 A. Otherwise, the state machine remains in the second boost output mode 194 A.

Operation of the second state machine of the logic circuit 148 A, which is depicted in FIG. 6A , will now be described. The second state machine includes a shunt output mode 196 A, a series output mode 198 A, a first boost output mode 200 A, and a second boost output mode 202 A. In addition, the second state machine uses the above-described boost lockout counter 184 and boost time counter 186 of the logic circuit 148 A.

In the shunt output mode 196 A, the logic circuit 148 A ( FIG. 4A ) configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in a closed state (conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3A ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to ground. If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to assertion of the series level indication 152 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the series level threshold 126 , the second state machine transitions to the series output mode 198 A. Otherwise the second state machine remains in the shunt output mode 196 A.

›DETAILED DESCRIPTION · 15 of 67

In the series output mode 198 A, the logic circuit 148 A ( FIG. 4A ) configures the series switch control output 162 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to de-assertion of the shunt level indication 150 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the shunt level threshold 124 , the logic circuit 148 A configures the second state machine to transition to the shunt output mode 196 A. However, in response to assertion of the first boost level indication 154 D, which indicates that the compensated power amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the first boost level threshold 128 , the logic circuit 148 A determines whether both the minimum charge time indicator is de-asserted and the first boost level indication 154 A is asserted. If the minimum charge time indicator is de-asserted and the first boost level indication 154 A is asserted, the logic circuit 148 A configures the second machine to transition to the first boost output mode 200 A. Otherwise, the logic circuit 148 A prevents the second state machine from transitioning to the first boost output mode 200 A until the minimum time indicator is de-asserted. Once both the minimum charge time indicator is de-asserted and the first boost level indication 154 A is asserted, the logic circuit 148 A configures the second state machine to transition to the first boost output mode 200 A, resets the counter output of the boost time counter 186 , and enables the boost time counter 186 to begin counting up. Otherwise, the second state machine remains in the series output mode 198 A.

In the first boost output mode 200 A, the logic circuit 148 A configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the first boost level indication 154 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the first boost level threshold 128 , the logic circuit 148 A configures the second state machine to transition to the series output mode 198 A. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 A asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 A sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. However, in response to assertion of the second boost level indication 156 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the second boost level threshold 130 , the logic circuit 148 A configures the second state machine to transition to the second boost output mode 202 A. Otherwise, the second state machine remains in the first boost output mode 200 A.

In the second boost output mode 202 A, the logic circuit 148 A configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 A also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 A configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3A ) to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3A is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT .

In response to de-assertion of the first boost level indication 154 A, which indicates that the compensated power amplifier circuit output current estimate, I PAWA — COMP , is less than the first boost level threshold 128 , the logic circuit 148 A configures the second state machine to transition to the series output mode 198 A. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 A asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 A sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. Otherwise, the second state machine remains in the second boost output mode 202 A.

The threshold and control circuit 132 A further provides a logic level indication of the switching voltage output, V SW — EST — OUT , which is a logic level representation of the switching voltage output, V SW . The switching voltage output, V SW — EST — OUT , may be based upon the V SW — EST — CMOS — SIGNAL (s). In some embodiments of the threshold and control circuit 132 A, the logic level indication of the switching voltage output, V SW — EST — OUT , may be asserted when the multi-level charge pump buck converter 12 A is in either the series output mode, the first boost output mode, or the second boost output mode. The logic level indication of the switching voltage output, V SW — EST — OUT , is de-asserted when the multi-level charge pump buck converter 12 A is in the shunt output mode.

›DETAILED DESCRIPTION · 16 of 67

FIG. 3B depicts another embodiment of switcher control circuit 52 , the switcher control circuit 52 B, and another embodiment of the FLL circuit 54 of the multi-level charge pump buck converter 12 , FLL circuit 54 B. The operation of the switcher control circuit 52 B and the FLL circuit 54 B will now be described.

Unlike the FLL circuit 54 A depicted in FIG. 3A , the FLL circuit 54 B outputs a threshold scalar′ 137 B. Similar to the FLL circuit 54 A, the FLL circuit 54 B receives a clock reference signal 139 A from a clock reference 139 and a logic level indication of the switching voltage output, V SW — EST — OUT . The FLL circuit 54 B extracts the operating frequency of the multi-level charge pump buck converter 12 based upon the logic level indication of the switching voltage output, V SW — EST — OUT . Thereafter, the FLL circuit 54 B compares the extracted operating frequency of the multi-level charge pump buck converter 12 to the clock reference signal 139 A to generate the threshold scalar′ 137 B. The magnitude of the threshold scalar′ 137 B may be used to adjust the operating frequency of the multi-level charge pump buck converter 12 . As will be discussed relative to the threshold detector and control circuit 132 B of FIG. 4B , the FLL circuit 54 B provides the threshold scalar′ 137 B directly to a plurality of multiplier circuits, where the plurality of multiplier circuits includes a first multiplier circuit 168 , a second multiplier circuit 170 , a third multiplier circuit 172 , and a fourth multiplier circuit 174 . The first multiplier circuit 168 , the second multiplier circuit 170 , the third multiplier circuit 172 , and the fourth multiplier circuit 174 may be used to scale the shunt level threshold 124 , the series level threshold 126 , the first boost level threshold 128 , and the second boost level threshold 130 , respectively to generate a scaled shunt level threshold 176 , a scaled series level threshold 178 , a scaled first boost level threshold 180 , and a scaled second boost level threshold 182 , of FIG. 4B . The scaled shunt level threshold 176 , the scaled series level threshold 178 , the scaled first boost level threshold 180 , and the scaled second boost level threshold 182 may be used to control the operating frequency of the multi-level charge pump buck converter 12 .

As an example, the FLL circuit 54 B may be configured to decrease the magnitude of the threshold scalar′ 137 B to decrease the magnitude of the scaled shunt level threshold 176 , the scaled series level threshold 178 , the scaled first boost level threshold 180 , and the scaled second boost level threshold 182 . As the magnitudes of the scaled shunt level threshold 176 , the scaled series level threshold 178 , the scaled first boost level threshold 180 , and the scaled second boost level threshold 182 decrease, the operating frequency of the multi-level charge pump buck converter 12 will tend to increase, which will tend to increase the power inductor current, I SW — OUT , delivered by the power inductor 16 .

The FLL circuit 54 B may be configured to increase the magnitude of the threshold scalar′ 137 B to increase the magnitude of the scaled shunt level threshold 176 , the scaled series level threshold 178 , the scaled first boost level threshold 180 , and the scaled second boost level threshold 182 . As the scaled shunt level threshold 176 , the scaled series level threshold 178 , the scaled first boost level threshold 180 , and the scaled second boost level threshold 182 are increased, the operating frequency of the multi-level charge pump buck converter 12 will tend to decrease, which will tend to decrease the power inductor current, I SW — OUT , delivered by the power inductor 16 .

Returning to FIG. 3B , unlike the switcher control circuit 52 A of FIG. 3A , the switcher control circuit 52 B includes a threshold detector and control circuit 132 B. The switcher control circuit 52 B omits the multiplier circuit 134 . As will be discussed below relative to the threshold detector and control circuit 132 B of FIG. 4B , the summing circuit 136 , is placed in the threshold detector and control circuit 132 B.

Also, similar to the switcher control circuit 52 A, the switcher control circuit 52 B may also receive a mode switch control signal 131 from the controller 50 . The mode switch control signal 131 may configure the threshold detector and control circuit 132 B to operate the multi-level charge pump buck converter in different modes of operation. As an example, the mode switch control signal 131 may configure operation of a state machine within the threshold detector and control circuit 132 B that governs how the switching voltage output 26 transitions the switching voltage output 26 to provide different output levels. As a first example embodiment of a state machine within the threshold detector and control circuit 132 B, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 to operate in a first mode of operation, depicted in FIG. 5B . As another example embodiment of a state machine within the threshold detector and control circuit 132 A, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 to operate in a second mode of operation, depicted in FIG. 6B .

Referring to FIG. 4B , the FLL circuit 54 B will now be discussed. Similar to FLL Circuit 54 A of FIG. 3A , the FLL circuit 54 B may be configured to receive a clock reference signal 139 A from the clock reference 139 and a logic level indication of the switching voltage output, V SW — EST — OUT , from the switcher control circuit 52 B. The logic level indication of the switching voltage output, V SW — EST — OUT , may be provided by the logic circuit 148 B of the threshold detector and control circuit 132 B. As discussed above, the logic level indication of the switching voltage output, V SW — EST — OUT , is a logic level representation of the switching voltage output, V SW .

›DETAILED DESCRIPTION · 17 of 67

The one embodiment of the threshold detector and control circuit 132 B includes a first multiplier circuit 168 , a second multiplier circuit 170 , a third multiplier circuit 172 , and a fourth multiplier circuit 174 . The first multiplier circuit 168 may be configured to receive the shunt level threshold 124 and the receive threshold scalar′ 137 B. The first multiplier circuit 168 multiplies the shunt level threshold 124 by the received threshold scalar′ 137 B to generate a scaled shunt level threshold 176 . The second multiplier circuit 170 may be configured to receive the series level threshold 126 and the threshold scalar′ 137 B. The second multiplier circuit 170 multiplies the series level threshold 126 by the threshold scalar′ 137 B to generate a scaled series level threshold 178 . The third multiplier circuit 172 may be configured to receive the first boost level threshold 128 and the threshold scalar′ 137 B. The third multiplier circuit 172 may multiplies the first boost level threshold 128 by the threshold scalar′ 137 B to generate a scaled first boost level threshold 180 . The fourth multiplier circuit 174 may be configured to receive the second boost level threshold 130 and the threshold scalar′ 137 B. The fourth multiplier circuit 174 multiplies the second boost level threshold 130 by the threshold scalar′ 137 B to generate the scaled second boost level threshold 182 . The summing circuit 136 subtracts the threshold offset current 42 , I THRESHOLD — OFFSET , from the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , to generate a compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, which may be used as a composite feedback signal for the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 . As discussed before, the threshold offset current 42 , I THRESHOLD — OFFSET , may be used to control the offset voltage, V OFFSET , that is generated across the coupling circuit 18 , as depicted in FIG. 2A . In the case where the coupling circuit 18 is a wire, such that the parallel amplifier output 32 A is directly coupled to the power amplifier supply output 28 , the V OFFSET loop circuit 41 and the threshold offset current, I THRESHOLD — OFFSET , are omitted such that I PAWA — COMP ′ is the same as parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST .

The first comparator 140 includes a positive terminal coupled to the scaled shunt level threshold 176 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, and a first comparator output configured to generate a shunt level indication 150 B, which is provided to the logic circuit 148 B. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled shunt level threshold 176 , the shunt level indication 150 B is asserted by setting output of the first comparator 140 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled shunt level threshold 176 , the shunt level indication 150 B is de-asserted by setting output of the first comparator 140 to a digital logic high state. The second comparator 142 includes a positive terminal coupled to the scaled series level threshold 178 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, and a second comparator output configured to generate a series level indication 152 B, which is provided to the logic circuit 148 B. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled series level threshold 178 , the series level indication 152 B is asserted by setting output of the second comparator 142 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled series level threshold 178 , the series level indication 152 B is de-asserted by setting output of the second comparator 142 to a digital logic high state. The third comparator 144 includes a positive terminal coupled to the scaled first boost level threshold 180 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, and a third comparator output configured to generate a first boost level indication 154 B, which is provided to the logic circuit 148 B. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than the scaled first boost level threshold 180 , the first boost level indication 154 B is asserted by setting output of the third comparator 144 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled first boost level threshold 180 , the first boost level indication 154 B is de-asserted by setting output of the third comparator 144 to a digital logic high state. The fourth comparator 146 includes a positive terminal coupled to the scaled second boost level threshold 182 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, and a fourth comparator output configured to generate a second boost level indication 156 B, which is provided to the logic circuit 148 B. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than the scaled second boost level threshold 182 , the second boost level indication 156 B is asserted by setting output of the fourth comparator 146 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled second boost level threshold 182 , the second boost level indication 156 B is de-asserted by setting output of the fourth comparator 146 to a digital logic high state.

›DETAILED DESCRIPTION · 18 of 67

The logic circuit 148 B will now be discussed. The logic circuit 148 B is similar to the logic circuit 148 A of FIG. 4A . The example embodiment of the logic circuit 148 B may include a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform. Some embodiments of the logic circuit 148 B may be implemented in either a digital or analog processor. The logic circuit 148 B generates the series switch control output 162 , the shunt switch control output 164 , the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), the charge pump mode control signal 60 , and the logic level indication of the switching voltage output, V SW — EST — OUT in a similar fashion as the logic circuit 148 A, which has been previously discussed.

The operation of the logic circuit 148 B will now be discussed with continuing reference to FIGS. 2A , 3 B, 4 B, 5 B, 6 B, and 7 A. Similar to the logic circuit 148 A of FIG. 4A , the logic circuit 148 B may be digital or analog based logic configured for one or more state machines of the threshold detector and control circuit 132 B. As an example embodiment, the logic circuit 148 B ( FIG. 4B ) may have a first state machine corresponding to a first mode of operation, depicted in FIG. 5B and a second state machine corresponding to a second mode of operation, depicted in FIG. 6B . Based on the mode switch control signal 131 , depicted in FIG. 3B , received by the threshold detector and control circuit 132 B, the threshold detector and control circuit 132 B may configure the logic circuit 148 B to use the first state machine to govern operation of the multi-level charge pump buck converter using the first state machine of the logic circuit 148 B, depicted in FIG. 5B . Alternatively, the threshold detector and control circuit 132 B may configure the logic circuit 148 B to use the second state machine to govern operation of the multi-level charge pump buck converter using the second state machine of the logic circuit 148 B, depicted in FIG. 6B

Also similar to the logic circuit 148 A, the logic circuit 148 B may include a boost lockout counter 184 and a boost time counter 186 . The boost time counter 186 may be used to keep track of the time that the multi-level charge pump buck converter 12 A is in either the first boost output mode or the second boost output mode. When the multi-level charge pump buck converter 12 A is in either the first boost output mode or the second boost output mode, the multi-level charge pump circuit 56 ( FIG. 3B ) is configured to be in either the first boost mode of operation or the second boost mode of operation, respectively. In one embodiment of the logic circuit 148 B, when the logic circuit 148 B determines that the multi-level charge pump buck converter 12 A is in either the first boost output mode or the second boost output mode, the logic circuit 148 B resets the counter output of the boost time counter 186 and enables the boost time counter 186 to begin counting up. The logic circuit 148 B compares the counter output of the boost timer counter 186 to a maximum boost time parameter, which may be provided by the controller 50 . If the counter output of the boost time counter 186 is equal to or exceeds the maximum boost time parameter before the multi-level charge pump buck converter 12 A is configured to return to either the shunt output mode of operation or the series output mode of operation, the logic circuit 148 B asserts a minimum charge time indicator. However, if the multi-level charge pump buck converter 12 A returns to either the series output mode of operation or the shunt output mode of operation while the counter output of the boost time counter 186 is less than the maximum boost time parameter, the logic circuit 148 B de-asserts the minimum charge time indicator.

Similar to the boost lockout counter 184 of the logic circuit 148 A, the boost lockout counter 184 of the logic circuit 148 B may be a count-down timer that is used to ensure that the multi-level charge pump circuit 56 , depicted in FIG. 3B , remains in a charging mode of operation for a minimum charge time period after the multi-level charge pump circuit 56 has been in either the first boost mode of operation or the second boost mode of operation. This permits the first flying capacitor 100 and the second flying capacitor 102 of FIG. 7A a sufficient amount of time to charge before the multi-level charge pump circuit 56 transitions again into either the first boost mode of operation or the second boost mode of operation. Similar to the logic circuit 148 A, the minimum charge time period may be a parameter provided by the controller 50 via the control bus 44 to the logic circuit 148 B. Operationally, after the multi-level charge pump buck converter 12 A transitions from either the first boost output mode or the second boost output mode to either the shunt output mode of operation or the series output mode of operation, the logic circuit 148 B determines whether the minimum charge time indicator is asserted. If the minimum charge time indicator is asserted, the logic circuit 148 B sets the count value of the boost lockout counter 184 to equal the minimum charge time period and enables the boost lockout counter 184 to begin counting down. Once the boost lockout counter 184 counts down to zero, the logic circuit 148 B is configured to de-assert the minimum charge time indicator.

Operation of the first state machine implemented in the logic circuit 148 B, depicted in FIG. 5B , will now be described. The first state machine includes a shunt output mode 188 B, a series output mode 190 B, a first boost output mode 192 B, and a second boost output mode 194 B.

In the shunt output mode 188 B, the logic circuit 148 B ( FIG. 4B ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3B ) is in an open state (not conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in a closed state (conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3B ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to ground. In response to assertion of the series level indication 152 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled series level threshold 178 , the logic circuit 148 B configures the first state machine to transition to the series output mode 190 B. Otherwise the first state machine remains in the shunt output mode 188 B.

›DETAILED DESCRIPTION · 19 of 67

In the series output mode 190 B, the logic circuit 148 B configures the series switch control output 162 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT .

In response to de-assertion of the shunt level indication 150 B ( FIG. 4B ), which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled shunt level threshold 176 , the logic circuit 148 B configures the first state machine to transition to the shunt output mode 188 B ( FIG. 5B ). However, in response to assertion of the first boost level indication 154 B which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled first boost level threshold 180 , the logic circuit 148 B configures the first state machine to transition to the first boost output mode 192 B. Otherwise, the first state machine remains in the series output mode 190 B.

In the first boost output mode 192 B, the logic circuit 148 B ( FIG. 4B ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3B ) is in an open state (not conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the shunt level indication 150 B ( FIG. 4B ), which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled shunt level threshold 176 , the logic circuit 148 B configures the first state machine to transition to the shunt output mode 188 B ( FIG. 5B ). However, in response to assertion of the second boost level indication 156 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled second boost level threshold 182 , the logic circuit 148 B configures the first state machine to transition to the second boost output mode 194 B. Otherwise, the first state machine remains in the first boost output mode 192 B.

In the second boost output mode 194 B, the logic circuit 148 B ( FIG. 4B ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3B ) is in an open state (not conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT . In response to de-assertion of the shunt level indication 150 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled shunt level threshold 176 , the first state machine transitions to the shunt output mode 188 B. Otherwise, the first state machine remains in the second boost output mode 194 B.

Operation of the second state machine of the logic circuit 148 B ( FIG. 3B ), which is depicted in FIG. 6B , will now be described. The second state machine includes a shunt output mode 196 B, a series output mode 198 B, a first boost output mode 200 B, and a second boost output mode 202 B. In addition, the second state machine uses the above-described boost lockout counter 184 and boost time counter 186 of the logic circuit 148 B.

In the shunt output mode 196 B, the logic circuit 148 B, depicted in FIG. 4B , configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in a closed state (conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 , depicted in FIG. 2A , to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to ground. If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to assertion of the series level indication 152 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled series level threshold 178 , the second state machine transitions to the series output mode 198 B. Otherwise the second state machine remains in the shunt output mode 196 B.

In the series output mode 198 B, the logic circuit 148 B ( FIG. 4B ) configures the series switch control output 162 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to de-assertion of the shunt level indication 150 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled shunt level threshold 176 , the logic circuit 148 B configures the second state machine to transition to the shunt output mode 196 B. However, in response to assertion of the first boost level indication 154 B which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ is greater than or equal to the scaled first boost level threshold 180 , the logic circuit 148 B determines whether both the minimum charge time indicator is de-asserted and the first boost level indication 154 B is asserted. If the minimum charge time indicator is de-asserted and the first boost level indication 154 B is asserted, the logic circuit 148 B configures the second machine to transition to the first boost output mode 200 B. Otherwise, the logic circuit 148 B prevents the second state machine from transitioning to the first boost output mode 200 B until the minimum time indicator is de-asserted. Once both the minimum charge time indicator is de-asserted and the first boost level indication 154 B is asserted, the logic circuit 148 B configures the second state machine to transition to the first boost output mode 200 B, resets the counter output of the boost time counter 186 , and enables the boost time counter 186 to begin counting up. Otherwise, the second state machine remains in the series output mode 198 B.

›DETAILED DESCRIPTION · 20 of 67

In the first boost output mode 200 B, the logic circuit 148 B configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the first boost level indication 154 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled first boost level threshold 180 , the logic circuit 148 B configures the second state machine to transition to the series output mode 198 B. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 B asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 B sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. However, in response to assertion of the second boost level indication 156 B which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled second boost level threshold 182 , the logic circuit 148 B configures the second state machine to transition to the second boost output mode 202 B. Otherwise, the second state machine remains in the first boost output mode 200 B.

In the second boost output mode 202 B, the logic circuit 148 B configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 B also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 B configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3B is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT .

In response to de-assertion of the first boost level indication 154 B which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the scaled first boost level threshold 180 , the logic circuit 148 B configures the second state machine to transition to the series output mode 198 B. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 B asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 B sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. Otherwise, the second state machine remains in the second boost output mode 202 B.

FIG. 3C depicts an embodiment of the pseudo-envelope follower power management system 10 B of FIG. 1B that does not include a frequency lock loop (FLL) circuit. The embodiment of the pseudo-envelope follower power management system 10 B that does not include a frequency lock loop (FLL) circuit may include a switcher control circuit 52 C. The switcher controller circuit 52 C may include a threshold detector and control circuit 132 C, which is similar to the threshold detector and control circuit 132 B of FIG. 3B . However, unlike threshold detector and control circuit 132 B, the threshold detector and control circuit 132 C may not be configured to provide the logic level indication of the switching voltage output, V SW — EST — OUT , to an FLL circuit. Likewise, unlike threshold detector and control circuit 132 B, the threshold detector and control circuit 132 C may not be configured to receive a threshold scalar from an FLL circuit.

FIG. 4C depicts an embodiment of the threshold detector and control circuit 132 C. Similar to the threshold detector and control circuit 132 B of FIG. 4B , the threshold detector and control circuit 132 C includes a summing circuit 136 configured to receive the threshold offset current 42 , I THRESHOLD — OFFSET , and the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , generated by the parallel amplifier circuit. The summing circuit 136 subtracts the threshold offset current 42 , I THRESHOLD — OFFSET , from the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , to generate a compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, which may be used as a composite feedback signal for the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 . As discussed before, the threshold offset current 42 , I THRESHOLD — OFFSET , may be used to control the offset voltage, V OFFSET , which is generated across the coupling circuit 18 , as depicted in FIG. 1A . In the case where the coupling circuit 18 is a wire, such that the parallel amplifier output 32 A is directly coupled to the power amplifier supply output 28 , the V OFFSET loop circuit 41 and the threshold offset current 42 , I THRESHOLD — OFFSET , are omitted such that I PAWA — COMP ′ is the same as the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST .

As depicted in FIG. 4C , with continuing reference to FIGS. 1A and 3C , the threshold detector and control circuit 132 C may include a first comparator 140 , a second comparator 142 , a third comparator 144 , a fourth comparator 146 , and a logic circuit 148 C. The example embodiment of the logic circuit 148 C may include a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform. Some embodiments of the logic circuit 148 C may be implemented in either a digital or analog processor.

›DETAILED DESCRIPTION · 21 of 67

The first comparator 140 includes a positive terminal coupled to the shunt level threshold 124 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, and a first comparator output configured to generate a shunt level indication 150 C, which is provided to the logic circuit 148 C. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the shunt level threshold 124 , the shunt level indication 150 C is asserted by setting output of the first comparator 140 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the shunt level threshold 124 , the shunt level indication 150 C is de-asserted by setting output of the first comparator 140 to a digital logic high state. The second comparator 142 includes a positive terminal coupled to the series level threshold 126 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ and a second comparator output configured to generate a series level indication 152 C, which is provided to the logic circuit 148 C. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ is greater than or equal to the series level threshold 126 , the series level indication 152 C is asserted by setting output of the second comparator 142 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ is less than the series level threshold 126 , the series level indication 152 C is de-asserted by setting output of the second comparator 142 to a digital logic high state. The third comparator 144 includes a positive terminal coupled to the first boost level threshold 128 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, and a third comparator output configured to generate a first boost level indication 154 C which is provided to the logic circuit 148 C. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than the first boost level threshold 128 , the first boost level indication 154 C is asserted by setting output of the third comparator 144 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ is less than the first boost level threshold 128 , the first boost level indication 154 C is de-asserted by setting output of the third comparator 144 to a digital logic high state. The fourth comparator 146 includes a positive terminal coupled to the second boost level threshold 130 , a negative terminal coupled to the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ and a fourth comparator output configured to generate a second boost level indication 156 C, which is provided to the logic circuit 148 C. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ is greater than the second boost level threshold 130 , the second boost level indication 156 C is asserted by setting output of the fourth comparator 146 to a digital logic low state. When the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ,′ is less than the second boost level threshold 130 , the second boost level indication 156 C is de-asserted by setting output of the fourth comparator 146 to a digital logic high state.

Similar to the logic circuit 148 A of FIG. 4A and the logic circuit 148 B of FIG. 4B , the logic circuit 148 C of FIG. 4C may be configured to generate a charge pump mode control signal 60 , a series switch control output 162 provided to the first output buffer 158 , a shunt switch control output 164 provided to the second output buffer 160 , one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), provided to the third output buffer 161 , and an estimated switching voltage output 38 B, V SW — EST . As previously described, the series switch control output 162 , a shunt switch control output 164 , and the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), may be configured to operate with the first output buffer 158 , the second output buffer 160 , and the third output buffer 161 to generate the series switch control signal 66 , the shunt switch control signal 68 , and the estimated switching voltage output 38 B, V SW — EST , respectively. Similar to the logic circuit 148 A of FIG. 4A and the logic circuit 148 B of FIG. 4B , the logic circuit 148 C may include a boost lockout counter 184 and a boost time counter 186 . The operation of the boost lockout counter 184 and a boost time counter 186 of the logic circuit 148 C is substantially similar to the operation of the boost lockout counter 184 and a boost time counter 186 of the logic circuit 148 A and 148 B of FIGS. 4A and 4B , respectively.

Similar to the threshold detector and control circuit 132 A of FIG. 4A and the threshold detector and control circuit 132 B of FIG. 4B , the threshold detector and control circuit 132 C may be configured to receive a mode switch control signal 131 from the controller 50 , as depicted in FIG. 3C , in order to configure the logic circuit 148 C to operate the multi-level charge pump buck converter in different modes of operation. As an example, the mode switch control signal 131 may configure operation of a state machine within the threshold detector and control circuit 132 C that governs how the switching voltage output 26 transitions the switching voltage output 26 to provide different output levels. As a first example embodiment of a state machine within the threshold detector and control circuit 132 C, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 to operate in a first mode of operation, depicted in FIG. 5C . As another example embodiment of a state machine within the threshold detector and control circuit 132 C, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 to operate in a second mode of operation, depicted in FIG. 6C .

›DETAILED DESCRIPTION · 22 of 67

The operation of the logic circuit 148 C will now be discussed with continuing reference to FIGS. 2A , 3 C, 4 C, 5 C, 6 C, and 7 A. Similar to the logic circuit 148 A of FIG. 4A and the logic circuit 148 B of FIG. 4B , the logic circuit 148 C may be digital or analog based logic configured for one or more state machines of the threshold detector and control circuit 132 C.

Operation of the first state machine implemented in the logic circuit 148 C, depicted in FIG. 5C , will now be described. The first state machine includes a shunt output mode 188 C, a series output mode 190 C, a first boost output mode 192 C, and a second boost output mode 194 C.

In the shunt output mode 188 C, the logic circuit 148 C ( FIG. 4C ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3C ) is in an open state (not conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in a closed state (conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3C ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to ground. In response to assertion of the series level indication 152 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the series level threshold 126 , the logic circuit 148 C configures the first state machine to transition to the series output mode 190 C. Otherwise the state machine remains in the shunt output mode 188 C.

In the series output mode 190 C, the logic circuit 148 C configures the series switch control output 162 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT .

In response to de-assertion of the shunt level indication 150 C ( FIG. 4C ), which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the shunt level threshold 124 , the logic circuit 148 C configures the first state machine to transition to the shunt output mode 188 C ( FIG. 5C ). However, in response to assertion of the first boost level indication 154 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the first boost level threshold 128 , the logic circuit 148 C configures the first state machine to transition to the first boost output mode 192 C. Otherwise, the first state machine remains in the series output mode 190 C.

In the first boost output mode 192 C, the logic circuit 148 C ( FIG. 4C ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3C ) is in an open state (not conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the shunt level indication 150 C ( FIG. 4C ), which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the shunt level threshold 124 , the logic circuit 148 C configures the first state machine to transition to the shunt output mode 188 C ( FIG. 5C ). However, in response to assertion of the second boost level indication 156 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the second boost level threshold 130 , the logic circuit 148 C configures the first state machine to transition to the second boost output mode 194 C. Otherwise, the first state machine remains in the first boost output mode 192 C.

In the second boost output mode 194 C, the logic circuit 148 C ( FIG. 4C ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3C ) is in an open state (not conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT . In response to de-assertion of the shunt level indication 150 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the shunt level threshold 124 , the first state machine transitions to the shunt output mode 188 C. Otherwise, the state machine remains in the second boost output mode 194 C.

Operation of the second state machine of the logic circuit 148 C, depicted in FIG. 6C , will now be described. The second state machine includes a shunt output mode 196 C, a series output mode 198 C, a first boost output mode 200 C, and a second boost output mode 202 C. In addition, the second state machine uses the above-described boost lockout counter 184 and boost time counter 186 of the logic circuit 148 C.

›DETAILED DESCRIPTION · 23 of 67

In the shunt output mode 196 C, the logic circuit 148 C ( FIG. 4C ) configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in a closed state (conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3C ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to ground. If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to assertion of the series level indication 152 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the series level threshold 126 , the second state machine transitions to the series output mode 198 C. Otherwise the second state machine remains in the shunt output mode 196 C.

In the series output mode 198 C, the logic circuit 148 C ( FIG. 4C ) configures the series switch control output 162 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to de-assertion of the shunt level indication 150 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the shunt level threshold 124 , the logic circuit 148 C configures the second state machine to transition to the shunt output mode 196 C. However, in response to assertion of the first boost level indication 154 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the first boost level threshold 128 , the logic circuit 148 C determines whether both the minimum charge time indicator is de-asserted and the first boost level indication 154 C is asserted. If the minimum charge time indicator is de-asserted and the first boost level indication 154 C is asserted, the logic circuit 148 C configures the second machine to transition to the first boost output mode 200 C. Otherwise, the logic circuit 148 C prevents the second state machine from transitioning to the first boost output mode 200 C until the minimum time indicator is de-asserted. Once both the minimum charge time indicator is de-asserted and the first boost level indication 154 C is asserted, the logic circuit 148 C configures the second state machine to transition to the first boost output mode 200 C, resets the counter output of the boost time counter 186 , and enables the boost time counter 186 to begin counting up. Otherwise, the second state machine remains in the series output mode 198 C.

In the first boost output mode 200 C, the logic circuit 148 C configures the series switch control output 162 such that the series switch 70 is in an open state (not conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 is in an open state (not conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3C ) to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the first boost level indication 154 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the first boost level threshold 128 , the logic circuit 148 C configures the second state machine to transition to the series output mode 198 C. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 C asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 C sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. However, in response to assertion of the second boost level indication 156 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the second boost level threshold 130 , the logic circuit 148 C configures the second state machine to transition to the second boost output mode 202 C. Otherwise, the second state machine remains in the first boost output mode 200 C.

In the second boost output mode 202 C, the logic circuit 148 C configures the series switch control output 162 such that the series switch 70 ( FIG. 3C ) is in an open state (not conducting). The logic circuit 148 C also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3C ) is in an open state (not conducting). In addition, the logic circuit 148 C configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3C ) to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3C is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT .

›DETAILED DESCRIPTION · 24 of 67

In response to de-assertion of the first boost level indication 154 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the first boost level threshold 128 , the logic circuit 148 C configures the second state machine to transition to the series output mode 198 C. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 C asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 C sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. Otherwise, the second state machine remains in the second boost output mode 202 C.

The threshold and control circuit 132 C further provides a logic level indication of the switching voltage output, V SW — EST — OUT , which is a logic level representation of the switching voltage output, V SW . The switching voltage output, V SW — EST — OUT , may be based upon the V SW — EST — CMOS — SIGNAL (s). In some embodiments of the threshold and control circuit 132 C, the logic level indication of the switching voltage output, V SW — EST — OUT , may be asserted when the multi-level charge pump buck converter 12 A is in either the series output mode, the first boost output mode, or the second boost output mode. The logic level indication of the switching voltage output, V SW — EST — OUT , is de-asserted when the multi-level charge pump buck converter 12 A is in the shunt output mode of operation.

By way of example, and not by limitation, FIG. 3D depicts an embodiment of the pseudo-envelope follower power management system 10 B of FIG. 1B that includes neither a frequency lock loop (FLL) circuit nor a V OFFSET loop circuit 41 . In addition, FIG. 3D depicts another embodiment of the pseudo-envelope follower power management system 10 B of FIG. 1B where the coupling circuit 18 is a wire and the parallel amplifier output 32 A of the parallel amplifier circuit 14 is directly coupled to the power amplifier supply output 28 . Other embodiments of the pseudo-envelope follower power management system 10 B of FIG. 1B that include the circuitry depicted in FIG. 3D may include a coupling circuit 18 that does not directly couple the output of the parallel amplifier output 32 A to the power amplifier supply output 28 , V CC . In those cases, the circuitry depicted in FIG. 3D may be included in a parallel amplifier circuit 14 , of FIG. 1A , that includes a V OFFSET loop circuit 41 .

FIG. 3D depicts an embodiment of the multi-level charge pump buck converter having a switcher control circuit 52 D, which is similar to the switcher control circuit 52 C depicted in FIG. 3C . However, unlike the switcher control circuit 52 C, the switcher control circuit 52 D includes a threshold detector and control circuit 132 D that is not configured to receive the threshold offset current 42 , I THRESHOLD — OFFSET , from the parallel amplifier circuit 14 .

Similar to the threshold detector and control circuit 132 A of FIG. 4A , the threshold detector and control circuit 132 B of FIG. 4B , and the threshold detector and control circuit 132 C of FIG. 4C , the threshold detector and control circuit 132 D of FIG. 4D may be configured to receive mode switch control signal 131 , depicted in FIG. 3D , from the controller 50 in order to configure the logic circuit 148 D to operate the multi-level charge pump buck converter in different modes of operation. As an example, the mode switch control signal 131 may configure operation of a state machine within the threshold detector and control circuit 132 D that governs how the switching voltage output 26 transitions the switching voltage output 26 to provide different output levels. As a first example embodiment of a first state machine within the threshold detector and control circuit 132 D, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 to operate in a first mode of operation, depicted in FIG. 5D . As another example embodiment a second state machine within the threshold detector and control circuit 132 D, the mode switch control signal 131 may configure the multi-level charge pump buck converter 12 to operate in a second mode of operation, depicted in FIG. 6D .

One embodiment of the threshold detector and control circuit 132 D is depicted in FIG. 4D . The threshold detector and control circuit 132 D is similar to the threshold detector and control circuit 132 A, depicted in FIG. 4A , except the logic circuit 148 A is replace by a logic circuit 148 D and the parallel amplifier circuit output current estimate, I PAWA — COMP , is replaced by the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST . As discussed above, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , may include the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the scaled open loop assist circuit output current estimate, I ASSIST — SENSE . However, in some embodiments of the parallel amplifier circuit that do not include the open loop assist circuit 39 , the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , only includes the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , generated by the parallel amplifier sense circuit 36 of the parallel amplifier circuitry 32 , as above described.

The threshold detector and control circuit 132 D of FIG. 4D will be described with continuing reference to FIG. 3D . The threshold detector and control circuit 132 D may include a first comparator 140 , a second comparator 142 , a third comparator 144 , a fourth comparator 146 , and a logic circuit 148 D. The example embodiment of the logic circuit 148 D may include a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform. Some embodiments of the logic circuit 148 D may be implemented in either a digital or analog processor.

›DETAILED DESCRIPTION · 25 of 67

The first comparator 140 includes a positive terminal coupled to the shunt level threshold 124 , a negative terminal coupled to the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and a first comparator output is configured to generate a shunt level indication 150 D, which is provided to the logic circuit 148 D. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the shunt level threshold 124 , the shunt level indication 150 D is asserted by setting output of the first comparator 140 to a digital logic low state. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the shunt level threshold 124 , the shunt level indication 150 D is de-asserted by setting output of the first comparator 140 to a digital logic high state. The second comparator 142 includes a positive terminal coupled to the series level threshold 126 , a negative terminal coupled to the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and a second comparator output is configured to generate a series level indication 152 D, which is provided to the logic circuit 148 D. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the series level threshold 126 , the series level indication 152 D is asserted by setting output of the second comparator 142 to a digital logic low state. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the series level threshold 126 , the series level indication 152 D is de-asserted by setting output of the second comparator 142 to a digital logic high state. The third comparator 144 includes a positive terminal coupled to the first boost level threshold 128 , a negative terminal coupled to the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and a third comparator output is configured to generate a first boost level indication 154 D, which is provided to the logic circuit 148 D. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than the first boost level threshold 128 , the first boost level indication 154 D is asserted by setting output of the third comparator 144 to a digital logic low state. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the first boost level threshold 128 , the first boost level indication 154 D is de-asserted by setting output of the third comparator 144 to a digital logic high state. The fourth comparator 146 includes a positive terminal coupled to the second boost level threshold 130 , a negative terminal coupled to the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , and a fourth comparator output is configured to generate a second boost level indication 156 D, which is provided to the logic circuit 148 D. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than the second boost level threshold 130 , the second boost level indication 156 D is asserted by setting output of the fourth comparator 146 to a digital logic low state. When the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the second boost level threshold 130 , the second boost level indication 156 D is de-asserted by setting output of the fourth comparator 146 to a digital logic high state.

Similar to the logic circuit 148 A of FIG. 4A , the logic circuit 148 B of FIG. 4B , and the logic circuit 148 C of FIG. 4C , the logic circuit 148 D may also be configured to generate charge pump mode control signal, a series switch control output 162 provided to the first output buffer 158 , a shunt switch control output 164 provided to the second output buffer 160 , one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), provided to the third output buffer 161 , and an estimated switching voltage output 38 B, V SW — EST . As previously described, the series switch control output 162 , the shunt switch control output 164 , and the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), may be configured to operate with the first output buffer 158 , the second output buffer 160 , and the third output buffer 161 to generate the series switch control signal 66 , the shunt switch control signal 68 , and the estimated switching voltage output 38 B, V SW — EST , respectively. Also similar to the logic circuit 148 A of FIG. 4A , the logic circuit 148 B of FIG. 4B , and the logic circuit 148 C of FIG. 4C , the logic circuit 148 D may include a boost lockout counter 184 and a boost time counter 186 . The operation of the boost lockout counter 184 and the boost time counter 186 of the logic circuit 148 D is substantially similar to the operation of the boost lockout counter 184 and the boost time counter 186 of the logic circuits 148 A, 148 B, and 148 C of FIGS. 4A , 4 B, and 4 C, respectively.

The example embodiment of the logic circuit 148 D may include a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform. Some embodiments of the logic circuit 148 D may be implemented in either a digital or analog processor. In addition, the logic circuit 148 D may include an embodiment of the first state machine and the second state machine of the threshold detector and control circuit 132 D.

Operation of the first state machine implemented in the logic circuit 148 D, depicted in FIG. 5D , will now be described. The first state machine includes a shunt output mode 188 D, a series output mode 190 D, a first boost output mode 192 D, and a second boost output mode 194 D.

In the shunt output mode 188 D, the logic circuit 148 D ( FIG. 4D ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in an open state (not conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in a closed state (conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3D ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to ground. In response to assertion of the series level indication 152 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the series level threshold 126 , the logic circuit 148 D configures the first state machine to transition to the series output mode 190 D. Otherwise the state machine remains in the shunt output mode 188 D.

›DETAILED DESCRIPTION · 26 of 67

In the series output mode 190 D, the logic circuit 148 D configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in a closed state (conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in an open state (not conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT .

In response to de-assertion of the shunt level indication 150 D ( FIG. 4D ), which indicates that the power amplifier circuit output current estimate, I PAWA — OUT — EST , is less than the shunt level threshold 124 , the logic circuit 148 D configures the first state machine to transition to the shunt output mode 188 D ( FIG. 5D ). However, in response to assertion of the first boost level indication 154 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the first boost level threshold 128 , the logic circuit 148 D configures the first state machine to transition to the first boost output mode 192 D. Otherwise, the first state machine remains in the series output mode 190 D.

In the first boost output mode 192 D, the logic circuit 148 D ( FIG. 4D ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in an open state (not conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in an open state (not conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the shunt level indication 150 D ( FIG. 4D ), which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the shunt level threshold 124 , the logic circuit 148 D configures the first state machine to transition to the shunt output mode 188 D ( FIG. 5D ). However, in response to assertion of the second boost level indication 156 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the second boost level threshold 130 , the logic circuit 148 D configures the first state machine to transition to the second boost output mode 194 D. Otherwise, the first state machine remains in the first boost output mode 192 D.

In the second boost output mode 194 D, the logic circuit 148 D ( FIG. 4D ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in an open state (not conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in an open state (not conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT . In response to de-assertion of the shunt level indication 150 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the shunt level threshold 124 , the first state machine transitions to the shunt output mode 188 D. Otherwise, the state machine remains in the second boost output mode 194 D.

Operation of the second state machine of the logic circuit 148 D, depicted in FIG. 6D , will now be described. The second state machine includes a shunt output mode 196 D, a series output mode 198 D, a first boost output mode 200 D, and a second boost output mode 202 D. In addition, the second state machine uses the above-described boost lockout counter 184 and boost time counter 186 of the logic circuit 148 D.

In the shunt output mode 196 D, the logic circuit 148 D ( FIG. 4D ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in an open state (not conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in a closed state (conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3D ) to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to ground. If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to assertion of the series level indication 152 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the series level threshold 126 , the second state machine transitions to the series output mode 198 D. Otherwise the second state machine remains in the shunt output mode 196 D.

In the series output mode 198 D, the logic circuit 148 D ( FIG. 4D ) configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in a closed state (conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in an open state (not conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a charging mode of operation. As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . If the boost lockout counter 184 is enabled, the boost lockout counter 184 continues to count down. In response to de-assertion of the shunt level indication 150 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the shunt level threshold 124 , the logic circuit 148 D configures the second state machine to transition to the shunt output mode 196 D. However, in response to assertion of the first boost level indication 154 D, which indicates that parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the first boost level threshold 128 , the logic circuit 148 D determines whether both the minimum charge time indicator is de-asserted and the first boost level indication 154 D is asserted. If the minimum charge time indicator is de-asserted and the first boost level indication 154 D is asserted, the logic circuit 148 D configures the second machine to transition to the first boost output mode 200 D. Otherwise, the logic circuit 148 D prevents the second state machine from transitioning to the first boost output mode 200 D until the minimum time indicator is de-asserted. Once both the minimum charge time indicator is de-asserted and the first boost level indication 154 D is asserted, the logic circuit 148 D configures the second state machine to transition to the first boost output mode 200 D, resets the counter output of the boost time counter 186 , and enables the boost time counter 186 to begin counting up. Otherwise, the second state machine remains in the series output mode 198 D.

›DETAILED DESCRIPTION · 27 of 67

In the first boost output mode 200 D, the logic circuit 148 D configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in an open state (not conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in an open state (not conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 to be in a first boost mode of operation to provide 1.5×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to 1.5×V BAT . In response to de-assertion of the first boost level indication 154 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the first boost level threshold 128 , the logic circuit 148 D configures the second state machine to transition to the series output mode 198 D. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 D asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 D sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. However, in response to assertion of the second boost level indication 156 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the second boost level threshold 130 , the logic circuit 148 D configures the second state machine to transition to the second boost output mode 202 D. Otherwise, the second state machine remains in the first boost output mode 200 D.

In the second boost output mode 202 D, the logic circuit 148 D configures the series switch control output 162 such that the series switch 70 ( FIG. 3D ) is in an open state (not conducting). The logic circuit 148 D also configures the shunt switch control output 164 such that the shunt switch 72 ( FIG. 3D ) is in an open state (not conducting). In addition, the logic circuit 148 D configures the charge pump mode control signal 60 to instruct the multi-level charge pump circuit 56 ( FIG. 3D ) to be in a second boost mode of operation to provide 2×V BAT at the charge pump output 64 . As a result, the switching voltage output 26 of FIG. 3D is configured to provide a switching voltage, V SW , substantially equal to 2×V BAT .

In response to de-assertion of the first boost level indication 154 D, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the first boost level threshold 128 , the logic circuit 148 D configures the second state machine to transition to the series output mode 198 D. If the count output of the boost time counter 186 exceeds the maximum boost time parameter, the logic circuit 148 D asserts a minimum charge time indicator. In response to the minimum charge time indicator being asserted, the logic circuit 148 D sets the count value of the boost lockout counter 184 and enables the boost lockout counter 184 to begin counting down. Otherwise, the second state machine remains in the second boost output mode 202 D.

With respect to the cases where the first state machine or the second state machine of the logic circuit 148 A, the logic circuit 148 B, the logic circuit 148 C, and the logic circuit 148 D depicted in the respective FIGS. 4A , 4 B, 4 C, and 4 D, are configured to be in either the first boost output mode 192 A, the first boost output mode 192 B, the first boost output mode 192 C, and the first boost output mode 192 D, or the first boost output mode 200 A, the first boost output mode 200 B, the first boost output mode 200 C, or the first boost output mode 200 D, respectively, when the multi-level charge pump circuit 56 is configured to be in a first boost mode of operation, the first switch 86 , the third switch 90 , the fifth switch 94 and the seventh switch 98 of the multi-level charge pump circuit 56 are configured to be closed such that charge from the supply input 24 , (V BAT ), the first flying capacitor 100 and the second flying capacitor 102 , arranged in parallel, is provided directly to the switching voltage output 26 via the charge pump output 64 in order to provide substantially 1.5×V BAT at the switching voltage output 26 . The second switch 88 , the fourth switch 92 , and the sixth switch 96 , and the eighth switch 118 of the multi-level charge pump are configured to be open.

Similarly, with respect to the cases where the first state machine or the second state machine of the logic circuit 148 A, the logic circuit 148 B, the logic circuit 148 C, and logic circuit 148 D depicted in the respective FIGS. 4A , 4 B, 4 C, and 4 D, are configured to be in either the second boost output mode 194 A, the second boost output mode 194 B, the second boost output mode 194 C, and the second boost output mode 194 D, or the second boost output mode 202 A, the second boost output mode 202 B, the second boost output mode 202 C, and the second boost output mode 202 D, when the multi-level charge pump circuit 56 is configured to be in a second boost mode of operation, the first switch 86 , the fourth switch 92 , and the fifth switch 94 are configured to be closed such that charge from the supply input 24 , (V BAT ), the first flying capacitor 100 and the second flying capacitor 102 , arranged in series, is provided directly to the switching voltage output 26 via the charge pump output 64 in order to provide substantially 2×V BAT at the switching voltage output 26 . The second switch 88 , the third switch 90 , the sixth switch 96 , and the seventh switch 98 of the multi-level charge pump circuit 56 are configured to be open. In those embodiments of the multi-level charge pump circuit 56 that further include the eighth switch 118 , the eighth switch 118 may also be configured to be open.

›DETAILED DESCRIPTION · 28 of 67

Advantageously, this permits the multi-level charge pump circuit 56 to provide either substantially 1.5×V BAT or substantially 2×V BAT at the switching voltage output 26 without the need for a charge pump output capacitor. Moreover, while some embodiments of the multi-level charge pump circuit 56 may include more than two flying capacitors or inductive components to provide boost voltage levels, some embodiments of the multi-level charge pump circuit 56 only include the first flying capacitor 100 and the second flying capacitor 102 . Even more advantageously, some embodiments of the multi-level charge pump circuit 56 that further include an eighth switch 118 , may provide an additional first output mode of operation to provide substantially ½×V BAT at the switching voltage output 26 using only the first flying capacitor 100 and the second flying capacitor 102 .

Returning to FIG. 2A , an example embodiment of the parallel amplifier circuit 14 A includes the parallel amplifier circuitry 32 . The parallel amplifier circuitry 32 includes a parallel amplifier 35 and a parallel amplifier sense circuit 36 . The parallel amplifier 35 generates the parallel amplifier output voltage, V PARA — AMP , at the parallel amplifier output 32 A based on the difference between the compensated V RAMP signal, V RAMP — C , and the power amplifier supply voltage, V CC . In addition, the parallel amplifier 35 outputs a parallel amplifier output current, I PARA — AMP . The parallel amplifier sense circuit 36 may include one or more current mirror circuits that are in communication with the parallel amplifier 35 depending upon the operational blocks included in the example embodiment of the parallel amplifier circuit 14 A. Based upon the parallel amplifier output current, I PARA — AMP , the parallel amplifier sense circuit 36 generates a scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , which provides an indication of the parallel amplifier output current, I PARA — AMP . In those embodiments of the parallel amplifier circuit 14 A that include an open loop assist circuit 39 , the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is combined with the scaled open loop assist circuit output current estimate, I ASSIST — SENSE , from the open loop assist circuit 39 to generate the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , which is provided to the multi-level charge pump buck converter 12 A. However, in those embodiments of the parallel amplifier circuit 14 A that do not include an open loop assist circuit 39 , only the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , may be provided as a contribution to form the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , provided to the multi-level charge pump buck converter 12 A. In addition, as depicted in FIG. 2A , in those embodiments of the parallel amplifier circuit 14 A that include a parallel amplifier output impedance compensation circuit 37 , a copy of the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is provided to the parallel amplifier output impedance compensation circuit 37 . However, in those embodiments of the parallel amplifier circuit 14 A that do not include a parallel amplifier output impedance compensation circuit 37 , the parallel amplifier sense circuit 36 is configured to only provide the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , as a contribution to the formation of the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , provided to the multi-level charge pump buck converter 12 A.

FIG. 12A depicts one embodiment of the parallel amplifier 35 as the parallel amplifier 35 A. The parallel amplifier 35 A depicts one embodiment of an AB class amplifier. The parallel amplifier 35 A includes a parallel amplifier input voltage 204 , a first amplifier, AMP A , 206 , the second amplifier 208 , AMP B , a first output stage 210 , and an amplifier feedback node 212 . The parallel amplifier input voltage 204 may be configured to receive either the V RAMP signal or the compensated V RAMP signal, V RAMP — C .

The first amplifier 206 , AMP A , includes a positive input terminal 206 A, a negative input terminal 206 B, and an output terminal 206 C. Regarding the first amplifier 206 , AMP A , the positive input terminal 206 A may be coupled to the parallel amplifier input voltage 204 . The negative input terminal 206 B may be coupled to the amplifier feedback node 212 , which is coupled to the power amplifier supply voltage, V CC . A first resistor, R A , and a first capacitor, C A , are arranged in series between the output terminal 206 C and the amplifier feedback node 212 . The first resistor, R A , and the first capacitor, C A , are a feedback network used to extend the operating bandwidth by compensating for the dominant pole introduced by the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 . The feedback network may be configured to extend the modulation bandwidth of the first amplifier 206 , AMP A , out to approximately 30 MHz. The first amplifier 206 , AMP A , generates a first amplifier output voltage, V A , at the output terminal 206 C based upon the difference between the parallel amplifier input voltage 204 appearing at the positive input terminal 206 A and the power amplifier supply voltage, V CC , appearing at the negative input terminal 206 B.

Regarding the second amplifier 208 , AMP B , the positive input terminal 208 A may be coupled to the parallel amplifier input voltage 204 . The negative input terminal 208 B may be coupled to the amplifier feedback node 212 , which is coupled to the power amplifier supply voltage, V CC . A second resistor, R B , and a second capacitor, C B , are arranged in series between the output terminal 208 C and the amplifier feedback node 212 . The second resistor, R B , and the second capacitor, C B , are a feedback network used to extend the operating bandwidth by compensating for the dominant pole introduced by the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 . The feedback network may be configured to extend the modulation bandwidth of the second amplifier 208 , AMP B , out to approximately 30 MHz. The second amplifier 208 , AMP B , generates a second amplifier output voltage, V B , at the output terminal 208 C based upon the difference between the parallel amplifier input voltage 204 appearing at the positive input terminal 208 A and the power amplifier supply voltage, V CC , appearing at the negative input terminal 208 B.

›DETAILED DESCRIPTION · 29 of 67

The first output stage 210 includes a first switching element, SW 1A , 214 and a second switching element, SW 1B , 216 . As a non limiting example, some embodiments of the first switching element, SW 1A , 214 and the second switching element, SW 1B , 216 , may be a solid state based switch such as a field effect transistor, an insulator-on-semiconductor based transistor, or a bipolar based transistor. These transistors may operate mainly in Class-AB mode, thus near to linear operation, even though the transistors are referred to as switches. In one example embodiment, the first switching element 214 , SW 1A , may be a PFET device having a drain 214 D, a gate 214 G, and a source 214 S. Likewise, the second switching element 216 , SW 1B , may be an NFET device having a drain 216 D, a gate 216 G, and a source 216 S.

The source 214 S of the first switching element 214 , SW 1A , may be coupled to the parallel amplifier supply input 30 , (V BAT ), of the multi-level charge pump buck converter 12 . The drain 214 D of the first switching element 214 , SW 1A , may be coupled to the drain 216 D of the second switching element 216 , SW 1B , to form a parallel amplifier output node 218 that provides the parallel amplifier output voltage, V PARA — AMP , of the parallel amplifier 35 A. The source 216 S of the second switching element 216 , SW 1B , may be coupled to ground.

The gate 214 G of the first switching element 214 , SW 1A , may be coupled to the output terminal 206 C of the first amplifier 206 , AMP A , in order to receive the first amplifier output voltage, V A . Similarly, the gate 216 G of the second switching element 216 , SW 1B , may be coupled to the output terminal 208 C of the second amplifier 208 , AMP B , in order to receive the second amplifier output voltage, V B .

The parallel amplifier 35 A may be configured to source from the parallel amplifier output node 218 and sink current to the parallel amplifier output node 218 based upon the difference between the parallel amplifier input voltage 204 (either V RAMP or V RAMP — C ) and the power amplifier supply voltage, V CC . For example, when the power inductor current, I SW — OUT , delivered by the power inductor 16 and the bypass capacitor current, I BYPASS — CAP , delivered by the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 are insufficient to supply the output current, I OUT , to the linear RF power amplifier 22 , the parallel amplifier 35 A turns on the first switching element 214 , SW 1A , to provide additional current through the coupling capacitor 18 A to the power amplifier supply output 28 . However, when the power inductor current, I SW — OUT , delivered by the power inductor 16 , and the bypass capacitor current, I BYPASS — CAP , from the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 exceed the desired level of output current, I OUT , to be delivered to the linear RF power amplifier 22 , the parallel amplifier 35 A turns on the second switching element 216 , SW 1B , to shunt the excess current provided to the power amplifier supply output 28 to ground.

In the case, as depicted in FIGS. 2A and 2B , where the parallel amplifier circuit 14 A includes an open loop assist circuit 39 providing an open loop assist circuit current, I ASSIST , the parallel amplifier 35 A compensates for either an excess of current or the lack of current supplied to the power amplifier supply output 28 . As an example, when the power inductor current, I SW — OUT , the open loop assist current, I ASSIST , and the bypass capacitor current, I BYPASS — CAP , deliver less than the desired level of output current, I OUT , to the linear RF power amplifier 22 , the parallel amplifier 35 turns on the first switching element 214 , SW 1A , to provide the additional current desired by the linear RF power amplifier 22 . As another example, when the power inductor current, I SW — OUT , the open loop assist current, I ASSIST , and the bypass capacitor current, I BYPASS — CAP , deliver excess current to the power amplifier supply output 28 , the parallel amplifier 35 A turns on the second switching element 216 , SW 1B , such that the excess current is shunted to ground.

FIG. 12B depicts another embodiment of the parallel amplifier 35 as the rechargeable parallel amplifier 35 B. Unlike the parallel amplifier 35 A of FIG. 12A , the rechargeable parallel amplifier 35 B includes a second output stage 220 A, a charge conservation capacitor, C AB , and an output control circuit 230 A.

The second output stage 220 A includes a first switching element 222 , SW 2A , and a second switching element 224 , SW 2B . As a non limiting example, some embodiments of the first switching element 222 , SW 2A , and the second switching element 224 , SW 2B , may be a solid state based switch such as a field effect transistor, an insulator-on-semiconductor transistor, or a bipolar based transistor. These transistors operate mainly in Class-AB mode, thus near to linear operation, even though the transistors are referred to as switches. In one example embodiment, the first switching element 222 , SW 2A , may be a PFET device having a drain 222 D, a gate 222 G, and a source 222 S. Likewise, the second switching element 224 , SW 2B , may be an NFET device having a drain 224 D, a gate 224 G, and a source 224 S.

The source 222 S of the first switching element 222 , SW 2A , may be coupled to the charge conservation capacitor, C AB . The drain 222 D of the first switching element 222 , SW 2A , and the drain 224 D of the second switching element 224 , SW 2B , may be coupled to the parallel amplifier output node 218 to provide the parallel amplifier output voltage, V PARA — AMP , of the rechargeable parallel amplifier 35 B. The source 224 S of the second switching element 224 , SW 2B , may be coupled to the charge conservation capacitor, C AB . As will be explained in further detail below, when the second switching element 224 , SW 2B , of the second output stage 220 A may be turned on to sink excess current provided to the power amplifier supply output 28 , charge is stored on the charge conservation capacitor, C AB , to generate a saved charge voltage, V AB . Similarly, when insufficient current is provided to the power amplifier supply output 28 , the first switching element 222 , SW 2A , may be turned on to provide additional current to the power amplifier supply output 28 from the charge conservation capacitor, C AB .

›DETAILED DESCRIPTION · 30 of 67

In order to operate in the linear mode of operation, the range of operation of the first switching element 222 , SW 2A , and the second switching element 224 , SW 2B , must take into consideration a minimum headroom voltage, V HEADROOM , of each device. As an example, the first switching element 222 , SW 2A , may operate in the linear mode provided the parallel amplifier output node 218 that provides the parallel amplifier output voltage, V PARA — AMP , is less than the saved charge voltage, V AB , minus the minimum headroom voltage, V HEADROOM . Similarly, the second switching element 224 , SW 2B , may operate in the linear mode provided the parallel amplifier output node 218 that provides the parallel amplifier output voltage, V PARA — AMP , is greater than the saved charge voltage, V AB , plus the minimum headroom voltage, V HEADROOM .

The output control circuit 230 A includes a V A input, V A — IN , a V B input, V B — IN , a V AB input, V AB — IN , and a V PARA — AMP input, V PARA — AMP — IN . The V A input, V A — IN , may be coupled to the output terminal 206 C of the first amplifier 206 , AMP A , to receive the first amplifier output voltage, V A . The V B input, V B — IN , may be coupled to the output terminal 208 C of the second amplifier 208 , AMP B , to receive the second amplifier output voltage, V B . The V PARA — AMP input, V PARA — AMP — IN , may be coupled to the parallel amplifier output node 218 to receive the parallel amplifier output voltage, V PARA — AMP . The V AB input, V AB — IN , may be coupled to the saved charge voltage, V AB .

The output control circuit 230 A may include a first switch control output, V SW1A , a second switch control output, V SW2A , a third switch control output, V SW2B , and a fourth switch control output, V SW1B . The first switch control output, V SW1A , may be coupled to the gate 214 G of the first switching element 214 , SW 1A . The second switch control output, V SW2A , may be coupled to the gate 222 G of the first switching element 222 , SW 2A . The third switch control output, V SW2B , may be coupled to the gate 224 G of the second switching element 224 , SW 2B . The fourth switch control output, V SW1B , may be coupled to the gate 216 G of the second switching element 216 , SW 1B .

The output control circuit 230 A selectively couples the V A input, V A — IN , to either the first switch control output, V SW1A , or the second switch control output, V SW2A , based upon the minimum headroom voltage, V HEADROOM , the saved charge voltage, V AB , and the parallel amplifier output voltage, V PARA — AMP . For example, when the parallel amplifier output voltage, V PARA — AMP , is greater than the saved charge voltage, V AB , minus the minimum headroom voltage, V HEADROOM , the output control circuit 230 A couples the V A input, V A — IN , to the first switch control output, V SW1A , of the first output stage 210 and sets the second switch control output, V SW2A , to disable the second switching element 224 , SW 2A , of the second output stage 220 A. As an example, the output control circuit 230 A may pull up the second switch control output, V SW2A , to the saved charge voltage, V AB . As a result, the first amplifier output voltage, V A , is coupled to the gate 214 G of the first switching element 214 , SW 1A , of the first output stage 210 .

However, when the parallel amplifier output voltage, V PARA — AMP , is less than or equal to the saved charge voltage, V AB , minus the minimum headroom voltage, V HEADROOM , the output control circuit 230 A couples the V A input, V A — IN , to the second switch control output, V SW2A , and sets the first switch control output, V SW 1A , to disable the first switching element 214 , SW 1A , of the first output stage 210 . As an example, the output control circuit 230 A may pull up the first switch control output, V SW1A , to the parallel amplifier supply input 30 , (V BAT ). As a result, the first amplifier output voltage, V A , is coupled to the gate 222 G of the first switching element 222 , SW 2A , of the second output stage 220 A.

The output control circuit 230 A also selectively couples the V B input, V B — IN , to either the third switch control output, V SW2B , or the fourth switch control output, V SW1B , based upon the minimum headroom voltage, V HEADROOM , the saved charge voltage, V AB , and the parallel amplifier output voltage, V PARA — AMP . For example, when the parallel amplifier output voltage, V PARA — AMP , is greater than the saved charge voltage, V AB , plus the minimum headroom voltage, V HEADROOM , the output control circuit 230 A couples the V B input, V B — IN , to the third switch control output, V SW2B , and sets the fourth switch control output, V SW1B , to disable the second switching element 216 , SW 1B . As an example, the output control circuit 230 A may pull down the fourth switch control output, V SW1B , to ground. As a result, the second amplifier output voltage, V B , is coupled to the gate 224 G of the second switching element 224 , SW 2B , of the second output stage 220 A.

However, when the parallel amplifier output voltage, V PARA — AMP , is less than or equal to the saved charge voltage, V AB , plus the minimum headroom voltage, V HEADROOM , the output control circuit 230 A couples the fourth switch control output, V SW1B , to the V B input, V B — IN , and sets the third switch control output, V SW2B , to disable the second switching element 224 , SW 2B . As an example, the output control circuit 230 A may pull down the third switch control output, V SW2B , to ground.

FIG. 12C depicts another embodiment of the parallel amplifier 35 as the rechargeable parallel amplifier 35 C. The rechargeable parallel amplifier 35 C of FIG. 12C is similar to the rechargeable parallel amplifier 35 B of FIG. 12B . However, unlike rechargeable parallel amplifier 35 B, rechargeable parallel amplifier 35 C includes an output control circuit 230 B instead of the output control circuit 230 A and a second output stage 220 B instead of the second output stage 220 A. The output control circuit 230 B further includes a V CC input, V CC — IN , that is coupled to the power amplifier supply output 28 in order to receive the power amplifier supply voltage, V CC . In addition, unlike rechargeable parallel amplifier 35 B, in the rechargeable parallel amplifier 35 C, the drain 224 D of the second switching element 224 , SW 2B , is coupled to the power amplifier supply output 28 instead of being coupled to the parallel amplifier output node 218 , which is now labeled as the parallel amplifier output node 218 C. Furthermore, as will be explained, the operation of the output control circuit 230 B is different from the operation of output control circuit 230 A in order to accommodate the coupling of the drain 224 D of the second switching element, SW 2B , 224 to the power amplifier supply output 28 .

›DETAILED DESCRIPTION · 31 of 67

Similar to the rechargeable parallel amplifier 35 B, the rechargeable parallel amplifier 35 C must also take into consideration the minimum headroom voltage, V HEADROOM , of the first switching element 222 , SW 2A , and the second switching element 224 , SW 2B , in order to assure the first switching element 222 , SW 2A , and the second switching element 224 , SW 2B , operate in the linear mode. However, because the drain 224 D of the second switching element 224 , SW 2B is coupled to the power amplifier supply output 28 , the power amplifier supply voltage, V CC , must also be considered.

Similar to the rechargeable parallel amplifier 35 B, the first switching element 222 , SW 2A , of the rechargeable parallel amplifier 35 C may operate in the linear mode provided the parallel amplifier output node 218 C that provides the parallel amplifier output voltage, V PARA — AMP , is less than the saved charge voltage, V AB , minus the minimum headroom voltage, V HEADROOM . However, unlike the rechargeable parallel amplifier 35 B, the second switching element 224 , SW 2B , of the rechargeable parallel amplifier 35 C may operate in the linear mode provided the power amplifier supply voltage, V CC , is greater than the saved charge voltage, V AB , plus the minimum headroom voltage, V HEADROOM . Because the power amplifier supply voltage, V CC , tends to be higher than the parallel amplifier output voltage, V PARA — AMP , the rechargeable parallel amplifier 35 C may store additional charge on the charge conservation capacitor, C AB , which increases the charge voltage, V AB . As a result, the operating range of the first switching element 222 , SW 2A , is also increased.

Similar to the output control circuit 230 A of FIG. 12B , the output control circuit 230 B of FIG. 12C selectively couples the V A input, V A — IN , to either the first switch control output, V SW1A , or the second switch control output, V SW2A , based upon the minimum headroom voltage, V HEADROOM , the saved charge voltage, V AB , and the parallel amplifier output voltage, V PARA — AMP . For example, when parallel amplifier output voltage, V PARA — AMP , is greater than the saved charge voltage, V AB , minus the minimum headroom voltage, V HEADROOM , the output control circuit 230 B couples the V A input, V A — IN , to the first switch control output, V SW1A , and sets the second switch control output, V SW2A , to disable the first switching element 222 , SW 2A , of the second output stage 220 B. As an example, the output control circuit 230 B may pull up the second switch control output, V SW2A , to the saved charge voltage, V AB . As a result, the first amplifier output voltage, V A , is coupled to the gate 214 G of the first switching element 214 , SW 1A , of the first output stage 210 C.

However, when the parallel amplifier output voltage, V PARA — AMP , is less than or equal to the saved charge voltage, V AB , minus the minimum headroom voltage, V HEADROOM , the output control circuit 230 B couples the V A input, V A — IN , to the second switch control output, V SW2A , of the second output stage 220 B and sets the first switch control output, V SW1A , to disable the first switching element 214 , SW 1A , of the first output stage 210 C. As an example, the output control circuit 230 B may pull up the first switch control output, V SW1A , to the parallel amplifier supply input 30 , (V BAT ). As a result, the first amplifier output voltage, V A , is coupled to the gate 222 G of the first switching element 222 , SW 2A , of the second output stage 220 B.

However, different from the output control circuit 230 A, the output control circuit 230 B also selectively couples the V B input, V B — IN , to either the third switch control output, V SW2B , or the fourth switch control output, V SW1B , based upon the minimum headroom voltage, V HEADROOM , the saved charge voltage, V AB , and the power amplifier supply voltage, V CC . For example, when the power amplifier supply voltage, V CC , is greater than the saved charge voltage, V AB , plus the minimum headroom voltage, V HEADROOM , the output control circuit 230 B couples the V B input, V B — IN , to the third switch control output, V SW2B , and sets the fourth switch control output, V SW1B , to disable the second switching element 216 , SW 1B . As an example, the output control circuit 230 B may pull down the fourth switch control output, V SW1B , to ground. As a result, the second amplifier output voltage, V B , is coupled to the gate 224 G of the second switching element 224 , SW 2B , of the second output stage 220 B.

However, when the power amplifier supply voltage, V CC , is less than or equal to the saved charge voltage, V AB , plus the minimum headroom voltage, V HEADROOM , the output control circuit 230 B couples the fourth switch control output, V SW1B , to the V B input, V B — IN , and sets the third switch control output, V SW2B , to disable the second switching element 224 , SW 2B . As an example, the output control circuit 230 B may pull down the third switch control output, V SW2B , to ground. As a result, the second amplifier output voltage, V B , is coupled to the gate 216 G of the second switching element 216 , SW 1B , of the first output stage 210 C.

While the embodiments of the parallel amplifier 35 A, the rechargeable parallel amplifier 35 B, and the rechargeable parallel amplifier 35 C of FIGS. 12A , FIG. 12B , and FIG. 12C , respectively, depict that the source 214 S of the first switching element 214 , SW 1A , of the first output stages 210 and 210 C are coupled to parallel amplifier supply input 30 , (V BAT ), this is by way of illustration and non-limiting. In some embodiments, the supply voltage provided to the parallel amplifier 35 A, rechargeable parallel amplifier 35 B, and the rechargeable parallel amplifier 35 C of FIGS. 12A , FIG. 12B , and FIG. 12C , may be provided by a separate power supply not depicted herein. The separate power supply may provide other voltage levels to power or bias the respective parallel amplifier 35 A, rechargeable parallel amplifier 35 B, and the rechargeable parallel amplifier 35 C. As a non-limiting example, the separate power supply may provide a parallel amplifier supply voltage substantially equal to 2×V BAT . Accordingly, in these example embodiments of the parallel amplifier 35 A, the rechargeable parallel amplifier 35 B, and the rechargeable parallel amplifier 35 C, source 214 S of the first switching element 214 , SW 1A , of the first output stage 210 may be coupled to the parallel amplifier supply voltage substantially equal to 2×V BAT .

›DETAILED DESCRIPTION · 32 of 67

As an example, discussed relative to FIGS. 18A-D , FIG. 12D depicts one embodiment of a parallel amplifier 35 D, similar to the parallel amplifier 35 A, that is configured to use a parallel amplifier supply voltage, V SUPPLY — PARA — AMP . In some embodiments, the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , may be configured to come from various power supply voltage generation circuits depending upon the needs of the linear RF power amplifier 22 . As depicted in FIGS. 18A-D , the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , may be provided by a μC charge pump circuit 262 or by the multi-level charge pump circuit 258 of multi-level charge pump buck converter 12 C. In addition, as discussed below, in some embodiments of the μC charge pump circuit 262 , the μC charge pump circuit 262 generates a μC charge pump output voltage, V μC — OUT , that may be configured to provide various voltage levels dependent upon the mode of operation of the μC charge pump circuit 262 .

As depicted in FIG. 12D , unlike the parallel amplifier 35 A of FIG. 12A , the parallel amplifier 35 D may be configured to use the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , instead of the parallel amplifier supply input 30 , (V BAT ), provided by the battery 20 . The parallel amplifier supply voltage, V SUPPLY — PARA — AMP , may be a discrete ratio of the parallel amplifier supply input 30 , (V BAT ), provided by the battery 20 . In other embodiments, however, the voltage level provided by the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , may be programmatically selected depending upon the operational conditions of the mobile device or pseudo-envelope follower power management system.

For example, as depicted in FIG. 12D , the source 214 S of the first switching element 214 , SW 1A , may be coupled to the parallel amplifier supply voltage, V SUPPLY — PARA — AMP . Although not depicted in FIG. 12D , the circuitry associated with the first amplifier 206 , AMP A , and the second amplifier 208 , AMP B , may also be supplied by the parallel amplifier supply voltage, V SUPPLY — PARA — AMP .

As another example, FIG. 12E depicts an embodiment of the rechargeable parallel amplifier 35 E that is similar to the rechargeable parallel amplifier 35 B depicted in FIG. 12B . Unlike the rechargeable parallel amplifier 35 B, the rechargeable parallel amplifier 35 E is configured to use the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , instead of the parallel amplifier supply input 30 , (V BAT ), provided by the battery 20 .

Accordingly, unlike the rechargeable parallel amplifier 35 B, the rechargeable parallel amplifier 35 E is configured such that the source 214 S of the first switching element 214 , SW 1A , is coupled to the parallel amplifier supply voltage, V SUPPLY — PARA — AMP . Similar to the parallel amplifier 35 D of FIG. 12D , the rechargeable parallel amplifier 35 E may also be reconfigured to use the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , as the supply voltage of the first amplifier 206 , AMP A , the second amplifier 208 , AMP B , and the output control circuit 230 A.

FIG. 12F depicts another embodiment of the rechargeable parallel amplifier 35 C, of FIG. 12C , as a rechargeable parallel amplifier 35 F. Similar to the parallel amplifier 35 D, depicted in FIG. 12D , and the rechargeable parallel amplifier 35 E, depicted in FIG. 12E , the rechargeable parallel amplifier 35 F is configured to use the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , instead of the parallel amplifier supply input 30 , (V BAT ), supplied by the battery 20 . Also similar to the parallel amplifier 35 D and the rechargeable parallel amplifier 35 E, rechargeable parallel amplifier 35 F may be configured such that the source 214 S of the first switching element 214 , SW 1A , may be coupled to the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , instead of the parallel amplifier supply input 30 , (V BAT ). Also similar to the rechargeable parallel amplifier 35 E, depicted in FIG. 12E , the first amplifier 206 , AMP A , the second amplifier 208 , AMP B , and the output control circuit 230 B may also be further configured to use the parallel supply voltage, V SUPPLY — PARA — AMP , as a supply source instead of the parallel amplifier supply input 30 , (V BAT ).

Returning to FIG. 2A , the open loop assist circuit 39 will now be discussed. As discussed above, the parallel amplifier circuit output current, I PAWA — OUT , may be a combination of the parallel amplifier output current I PARA — AMP , and the open loop assist circuit, I ASSIST . The open loop assist circuit 39 may be used to reduce the amount of current that the parallel amplifier 35 of the parallel amplifier circuitry 32 may need to source and sink in order to regulate the power amplifier supply voltage, V CC . In particular, the parallel amplifier 35 may sink excess power inductor current, I SW — OUT , which may generate a large voltage ripple on the power amplifier supply voltage, V CC . The large voltage ripple on the power amplifier supply voltage, V CC , can be due to the interaction of the power inductor current, I SW — OUT , with the non-zero impedance of parallel amplifier 35 over frequency in the pass band of the pseudo-envelope follower power management system. The open loop assist current, I ASSIST , provided by the open loop assist circuit 39 can be configured to reduce the parallel amplifier output current, I PARA — AMP , sourced or sunk by the parallel amplifier 35 , which may reduce the ripple voltage on the power amplifier supply voltage, V CC , because the non-zero output impedance of the parallel amplifier 35 is convoluted with less current.

One embodiment of the open loop assist circuit 39 may be configured to receive an estimated power inductor inductance parameter, L EST , and a minimum power amplifier turn on a voltage parameter, V OFFSET — PA , an estimated bypass capacitor capacitance parameter, C BYPASS — EST , and an estimated power amplifier transconductance parameter, K_I OUT — EST .

›DETAILED DESCRIPTION · 33 of 67

The estimated power inductor inductance parameter, L EST , may be either the measured or estimated inductance of the power inductor 16 between a specific range of frequencies. For example, the estimated power inductor inductance parameter, L EST , may be either the measured or estimated inductance of the power inductor 16 between approximately 10 MHz and 30 MHz. The minimum power amplifier turn on voltage parameter, V OFFSET — PA , may be either the measured or estimated value of the minimum supply voltage at which the linear RF power amplifier 22 will begin to operate. The estimated bypass capacitor capacitance parameter, C BYPASS — EST , may be either the measured or estimate capacitance of the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 measured between a specific range of frequencies. For example, the estimated bypass capacitor capacitance parameter, C BYPASS — EST , may be either the measured or estimated capacitance of the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 between approximately 10 MHz and 30 MHz. The estimated power amplifier transconductance parameter, K_I OUT — EST , may be either the measured or estimated transconductance of the linear RF power amplifier 22 . Transconductance of the linear RF power amplifier 22 may be 1/R LOAD , where R LOAD , is the estimated resistive load of the linear RF power amplifier 22 . The estimated power amplifier transconductance parameter, K_I OUT — EST , may be either the measured or estimated transconductance of the linear RF power amplifier 22 between a specific range of frequencies. For example, the estimated power amplifier transconductance parameter, K_I OUT — EST , may be either the measured or estimated transconductance of the linear RF power amplifier 22 between approximately 10 MHz and 30 MHz.

The estimated power inductor inductance parameter, L EST , the minimum power amplifier turn on voltage parameter, V OFFSET — PA , the estimated bypass capacitor capacitance parameter, C BYPASS — EST , and the estimated power amplifier transconductance parameter, K_I OUT — EST may be provided by the controller 50 through the control bus 44 , as depicted in FIGS. 1A and 1B . Typically, values of the estimated power inductor inductance parameter, L EST , the minimum power amplifier turn on the voltage parameter, V OFFSET — PA , the estimated bypass capacitor capacitance parameter, C BYPASS — EST , and the estimated power amplifier transconductance parameter, K_I OUT — EST , are obtained at calibration time of the pseudo-envelope follower system.

In addition, the open loop assist circuit 39 may be configured to receive the feed forward control signal 38 , V SWITCHER , from the multi-level charge pump buck converter 12 . As discussed above, the feed forward control signal 38 , V SWITCHER , may be configured to provide either the scaled switching voltage output 38 A, V SW — SCALED , or the estimated switching voltage output 38 B, V SW — EST . The open loop assist circuit 39 may also be configured to receive the V RAMP signal, from the first control input 34 .

FIG. 9A depicts a more detailed block diagram of an embodiment of the open loop assist circuit 39 of FIG. 2A , which is depicted as an open loop assist circuit 39 A. The open loop assist circuit 39 A will be described with continuing reference to FIGS. 1A and 2A . The open loop assist circuit 39 A includes an output current estimator 240 , a bypass capacitor current estimator 242 , a power inductor current estimator 244 A, a summing circuit 246 , and a controlled current source 248 . The output current estimator 240 receives the V RAMP signal, the estimated power amplifier transconductance parameter, K_I OUT — EST , and the minimum power amplifier turn on voltage parameter, V OFFSET — PA . The output current estimator 240 generates an output current estimate, I OUT — EST , based upon the V RAMP signal, the estimated power amplifier transconductance parameter, K_I OUT — EST , and the minimum power amplifier turn on voltage parameter, V OFFSET — PA . The output current estimate, I OUT — EST , is an estimate of the output current, I OUT , provided to the linear RF power amplifier 22 .

In one embodiment, the output current estimator 240 calculates the difference between the V RAMP signal and the minimum power amplifier turn on voltage parameter, V OFFSET — PA , by subtracting the minimum power amplifier turn on voltage parameter, V OFFSET — PA , from the V RAMP signal, (V RAMP −V OFFSET — PA ). Thereafter, the difference between the V RAMP signal and the minimum power amplifier turn on voltage parameter, V OFFSET — PA , is scaled by the estimated power amplifier transconductance parameter, K_I OUT — EST , to generate the output current estimate, I OUT — EST , where I OUT — EST =K_I OUT — EST *(V RAMP −V OFFSET — PA ). Typical circuitry may include an operational amplifier to perform (V RAMP −V OFFSET — PA ) and the voltage difference is applied to a transconductance amplifier, which the transconductance amplifier gain, Gm, is programmable and equal to K_I OUT — EST .

The bypass capacitor current estimator 242 receives the V RAMP signal and the estimated bypass capacitor capacitance parameter, C BYPASS — EST . The bypass capacitor current estimator 242 generates a bypass capacitor current estimate, I BYPASS — EST , based upon the V RAMP signal and the estimated bypass capacitor capacitance parameter, C BYPASS — EST . The bypass capacitor current estimate, I BYPASS — EST , is an estimate of the bypass capacitor current, I BYPASS — CAP , delivered by the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 .

In one embodiment, the V RAMP signal is differentiated to provide a V RAMP rate of change signal, d(V RAMP )/dT, which serves as an estimate of the rate of change of the voltage across the bypass capacitor 19 . The V RAMP rate of change signal, d(V RAMP )/dT, may be an estimate of the rate of change of the V RAMP signal over time. In some embodiments, the V RAMP rate of change signal, d(V RAMP )/dT, is generated by a high pass filter having a desired time constant. A simple high-pass filter followed by a gain circuit provides a frequency response below its corner frequency that have a +6 dB/octave slope thus equivalent to “s laplace transform” and thus creating a differentiator function below the corner frequency. The high-pass filter is typically made of a series capacitor and a shunt resistor. In some embodiments, the time constant of the high pass filter may be between the range of 8 nanoseconds and 16 nanoseconds.

›DETAILED DESCRIPTION · 34 of 67

The power inductor current estimator 244 A receives the V RAMP signal, the feed forward control signal 38 , V SWITCHER , and the estimated power inductor inductance parameter, L EST . The power inductor current estimator 244 A generates a power inductor current estimate, I SW — OUT — EST , based upon the V RAMP signal, the feed forward control signal 38 , V SWITCHER , and the estimated power inductor inductance parameter, L EST . The power inductor current estimate, I SW — OUT — EST , is an estimate of the power inductor current, I SW — OUT , delivered by the power inductor 16 .

In one embodiment of the power inductor current estimator 244 A, the power inductor current estimator 244 A subtracts the V RAMP signal from the feed forward control signal 38 , V SWITCHER , to generate a difference voltage V DIFFERENCE . The power inductor current estimator 244 A may include an integrator circuit (not shown) that integrates the difference voltage V DIFFERENCE to generate an accumulated difference signal. The power inductor current estimator 244 A then scales an accumulated difference signal with a factor of 1/L EST , to generate the power inductor current estimate, I SW — OUT — EST . The bandwidth of the integrator circuit used to integrate the difference voltage V DIFFERENCE may be between 5 MHz and 45 MHz. In some embodiments, the integrator slope may be programmable. For example, the controller 50 may adjust the gain of the transistors of the integrator circuit (not shown) of the power inductor current estimator 244 A in order to adjust the integrator slope. Also, it is possible to use a low-pass filter followed by a gain which above the corner frequency the slope versus frequency is −6 dB/octave similar to “1/s Laplace transform” thus acting as an integrator in the frequencies above the corner frequency. The corner frequency can be set below 5 MHz and is made programmable.

In another embodiment of the power inductor current estimator 244 A the power inductor current estimator 244 A divides the accumulated difference signal by the estimated power inductor inductance parameter, L EST , to generate the power inductor current estimate, I SW — OUT — EST .

In still another embodiment of the power inductor current estimator 244 A, the difference voltage, V DIFFERENCE , is scaled by the factor of 1/L EST , or divided by the estimated power inductor inductance parameter, L EST , to generate a scaled difference signal, S DIFFERENCE — SCALED , (not shown) prior to integration. The power inductor current estimator 244 A then integrates a scaled difference signal, S DIFFERENCE — SCALED , (not shown) to generate the power inductor current estimate, I SW — OUT — EST . In yet another embodiment of the power inductor current estimator 244 A, the power inductor current estimator 244 A scales the V RAMP signal and the feed forward control signal 38 , V SWITCHER , by the factor of 1/L EST , or divides the V RAMP signal and the feed forward control signal 38 , V SWITCHER , by the estimated power inductor inductance parameter, L EST , prior to calculating the scaled difference signal, S DIFFERENCE — SCALED , (not shown). Thereafter, the scaled difference signal, S DIFFERENCE — SCALED , is integrated to generate the power inductor current estimate, I SW — OUT — EST .

When the feed forward control signal 38 , V SWITCHER , is configured to provide the estimated switching voltage output 38 B, V SW — EST , to the open loop assist circuit 39 , the power inductor current estimate, I SW — OUT — EST , is generated based upon the estimated switching voltage output 38 B, V SW — EST . When the feed forward control signal 38 , V SWITCHER , is configured to provide the scaled switching voltage output 38 A, V SW — SCALED , to the open loop assist circuit 39 , the power inductor current estimate, I SW — OUT — EST , is generated based upon the switching voltage output, V SW — SCALED , 38 A.

The summing circuit 246 is configured to receive the output current estimate, I OUT — EST , the bypass capacitor current estimate, I BYPASS — EST , and power inductor current estimate, I SW — OUT — EST . The summing circuit 246 subtracts the bypass capacitor current estimate, I BYPASS — EST , and the power inductor current estimate, I SW — OUT — EST , from the output current estimate, I OUT — EST , to generate an estimate of the open loop assist current, I ASSIST — EST . The open loop assist current, I ASSIST — EST , is an estimate of the open loop assist current, I ASSIST , provided by the open loop assist circuit 39 A to the parallel amplifier output 32 A in order to generate the parallel amplifier circuit output current, I PAWA — OUT , from the parallel amplifier circuit 14 .

The controlled current source 248 is a controlled current source that generates the open loop assist current, I ASSIST , based upon the open loop assist current, I ASSIST — EST . The open loop assist current can be activated when reduced voltage ripple reduction is required and can be disabled when voltage ripple reduction is not required such as when operating at lower power amplifier output power. The open loop assist current can be made of three separate controlled current sources, where each controlled current source is controlled by the power inductor current estimate, I SW — OUT — EST , the bypass capacitor current estimate, I BYPASS — EST , and the output current estimate, I OUT — EST , respectively. Also, the open loop assist current, I ASSIST , in phase may be time aligned with the parallel amplifier output current, I PARA — AMP . For example, when the open loop assist current, I ASSIST , is positive, parallel amplifier output current, I PARA — AMP , may be positive and when the open loop assist current, I ASSIST , is negative, the parallel amplifier output current, I PARA — AMP , may also be negative as such there is no wasted currents, where the parallel amplifier output current, I PARA — AMP , that is sourced is not sunk by the open loop assist circuit 39 A.

FIG. 9B depicts another embodiment of the open loop assist circuit 39 B. As depicted in FIG. 9B , the open loop assist circuit 39 B is similar to the open loop assist circuit 39 A except that the open loop assist circuit 39 B receives the estimated switching voltage output 38 B, V SW — EST , as the feed forward control signal instead of the feed forward control signal 38 , V SWITCHER . Accordingly, the estimated switching voltage output 38 B, V SW — EST , includes a power inductor current estimator 244 B instead of the power inductor current estimator 244 A. The power inductor current estimator 244 B is similar to the power inductor current estimator 244 A except the power inductor current estimator 244 B only receives estimated switching voltage output 38 B, V SW — EST , instead of the feed forward control signal 38 , V SWITCHER .

›DETAILED DESCRIPTION · 35 of 67

As a result, the power inductor current estimate, I SW — OUT — EST , generated by the power inductor current estimator 244 B is based upon the estimated switching voltage output 38 B, V SW — EST . As a result, the power inductor current estimator 244 B is functionally like the power inductor current estimator 244 A when the feed forward control signal 38 , V SWITCHER , provides the estimated switching voltage output 38 B, V SW — EST , as an output. Accordingly, the open loop assist circuit 39 B operates in a manner that is similar to the operation of the open loop assist circuit 39 A when the feed forward control signal 38 , V SWITCHER , provides the estimated switching voltage output 38 B, V SW — EST , to the open loop assist circuit 39 A.

Returning to FIG. 2A , the parallel amplifier output impedance compensation circuit 37 will now be discussed. The combination of the multi-level charge pump buck converter 12 and the parallel amplifier 35 of the parallel amplifier circuitry 32 may not have a flat frequency response across the modulation bandwidth of the power amplifier supply voltage, V CC , provided to the linear RF power amplifier 22 . In particular, the desired modulation bandwidth of the power amplifier supply voltage, V CC , is between 1.5 to 2.5 times the RF modulation bandwidth of the linear RF power amplifier 22 . As an example, the Long Term Evolution LTE 3GPP standard of the RF modulation bandwidth may be up to 20 MHz. As a result, the desired modulation bandwidth of power amplifier supply voltage, V CC , generated by the pseudo-envelope follower power management system 10 A may be between 30 MHz to 40 MHz. In some embodiments of the pseudo-envelope follower power management system 10 A, the desired modulation bandwidth of the power amplifier supply voltage, V CC , may be approximately 35 MHz. However, at higher frequencies, the output impedance of the parallel amplifier 35 that regulates the power amplifier supply voltage, V CC , may become inductive. The output impedance of the parallel amplifier 35 combines with the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 to roll off the modulation frequency response of the parallel amplifier 35 . The roll off of the modulation frequency response of the parallel amplifier 35 may result in increased ripple voltage in the power amplifier supply voltage, V CC , due to the inductor current, I SW — OUT , provided by the power inductor 16 . The parallel amplifier output impedance compensation circuit 37 may be configured to pre-compensate the V RAMP signal in order to provide a compensated V RAMP signal, V RAMP — C , to the parallel amplifier 35 in order to flatten the modulation frequency response of the parallel amplifier 35 .

The parallel amplifier output impedance compensation circuit 37 depicted in FIG. 2A is configured to receive the V RAMP signal, an estimated bypass capacitor capacitance parameter, C BYPASS — EST , and a parallel amplifier inductance estimate parameter, L CORR — EST . The parallel amplifier inductance estimate parameter, L CORR — EST , may be an estimated inductance of the parallel amplifier 35 between the frequencies 10 MHz and 30 MHz, which is measured during calibration. The parallel amplifier inductance estimate parameter, L CORR — EST , may be provided by the controller 50 via the control bus 44 at configuration time.

FIG. 10 depicts an example embodiment of the parallel amplifier output impedance compensation circuit 37 , depicted in FIG. 2A , as a parallel amplifier output impedance compensation circuit 37 A. The parallel amplifier output impedance compensation circuit 37 A may include a first differentiator circuit 250 , a second differentiator 252 , a frequency pre-distortion circuit 254 , and a summing circuit 256 .

The first differentiator circuit 250 receives the V RAMP signal and the estimated bypass capacitor capacitance parameter, C BYPASS — EST . Similar to the bypass capacitor current estimator 242 of FIGS. 9A and 9B , the first differentiator circuit 250 generates a bypass capacitor current estimate, I BYPASS — EST , based upon the V RAMP signal and the bypass capacitor capacitance parameter, C BYPASS — EST . The bypass capacitor current estimate, I BYPASS — EST , is an estimate of the bypass capacitor current, I BYPASS — CAP , delivered by the bypass capacitor capacitance, C BYPASS , of the bypass capacitor 19 . In some embodiments of the parallel amplifier output impedance compensation circuit 37 A, the parallel amplifier output impedance compensation circuit 37 A uses the bypass capacitor current estimate, I BYPASS — EST , provided by the bypass capacitor current estimator 242 and the first differentiator circuit 250 is omitted. In other embodiments of the parallel amplifier output impedance compensation circuit 37 A, the time constant of the first differentiator circuit 250 may be different than the time constant of bypass capacitor current estimator 242 of the open loop assist circuit 39 .

Similar to the bypass capacitor current estimator 242 , in one embodiment of the first differentiator circuit 250 , the V RAMP signal is differentiated to provide a V RAMP rate of change signal, d(V RAMP )/dT, which serves as an estimate of the rate of change of the voltage across the bypass capacitor 19 . The V RAMP rate of change signal, d(V RAMP )/dT, may be an estimate of the rate of change of the V RAMP signal over time. In some embodiments, the V RAMP rate of change signal, d(V RAMP )/dT, is generated by a high pass filter (not shown) having a desired time constant. As an example, a simple high-pass filter followed by a gain stage may provide a frequency response below its corner frequency that has a +6 dB/octave slope, thus equivalent to the “s Laplace transform” and thus creating a differentiator function below the corner frequency. The high-pass filter (not shown) is typically made of a series capacitor and a shunt resistor. In some embodiments, the time constant of the high pass filter may be between the range of 8 nanoseconds and 16 nanoseconds.

›DETAILED DESCRIPTION · 36 of 67

The bypass capacitor current estimate, I BYPASS — EST , and the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , are combined to create a dynamic current, I DYNAMIC , which is provided to the second differentiator circuit 252 . The dynamic current, I DYNAMIC , represents the dynamic portion of the power inductor current, I SW — OUT , delivered by the power inductor 16 . The second differentiator circuit 252 is to replicate the parallel amplifier output impedance frequency response, which exhibits an output impedance that increases at +6 dB/octave, like an inductor, at the frequency range where the switcher current is operating, up to a resonance frequency equal to 1/(2*pi*sqrt(L CORR* C BYPASS )).

The second differentiator circuit 252 is configured to receive the dynamic current, I DYNAMIC , and the parallel amplifier inductance estimate parameter, L CORR .

The second differentiator circuit 252 differentiates the dynamic current, I DYNAMIC , to provide a dynamic current rate of change signal, d/(I DYNAMIC )/dT. The dynamic current rate of change signal, d/(I DYNAMIC )/dT, estimates change of the dynamic current, I DYNAMIC , with respect to time. In some embodiments, the dynamic current rate of change signal, d(I DYNAMIC )/dT, is generated by a low pass filter (not shown) having a desired time constant. The time constants of the second differentiator circuit 252 may be configured to optimize the modulation bandwidth of the parallel amplifier 35 . The second differentiator can be made from a high-pass filter (not shown) followed by a gain to provide a frequency response below its corner frequency that has a +6 dB/octave slope thus equivalent to “s Laplace transform” and thus creating a differentiator function below the corner frequency. The high-pass filter is typically made of a series capacitor and a shunt resistor. The time constant of the high-pass filter may be between 8 nanoseconds and 16 nanoseconds. The second differentiator circuit 252 scales the dynamic current rate of change signal, d(I DYNAMIC )/dT, by the parallel amplifier inductance estimate parameter, L CORR , to generate a power amplifier supply ripple voltage estimate, V RIPPLE , at the negative input of the summing circuit 256 . The power amplifier supply ripple voltage estimate is an estimate of the ripple voltage component of the power amplifier supply voltage, V CC , at the power amplifier supply output 28 .

The frequency pre-distortion circuit 254 may be configured to receive the V RAMP signal and output a peaked V RAMP signal, V RAMP — PEAKED . The frequency pre-distortion circuit 254 may be a programmable peaking filter that may be configured to compensate for the roll off of the modulation frequency response of the parallel amplifier 35 . The frequency pre-distortion circuit 254 may include a frequency equalizer circuit that includes a programmable pole time constant, Tau_Pole, and a programmable zero time constant, Tau_Zero. The frequency pre-distortion circuit Laplace transfer function, V RAMP — C /V RAMP , may be approximately equal to [1+Tau_Zero*s]/[1+Tau_Pole*s]. The programmable pole time constant, Tau_Pole, and the programmable zero time constant, Tau_Zero, may be adjusted to increase the frequency response of the frequency pre-distortion circuit 254 , V RAMP — C /V RAMP , in order to flatten the overall modulation frequency response of the pseudo-envelope follower power management system 10 A. In some embodiments of the frequency pre-distortion circuit 254 , the programmable pole time constant, Tau_Pole, is configured to about 0.4 microseconds, (1/2.5 MHz). The programmable zero time constant, Tau_Zero, may be configured to be about 0.192 microseconds, (1/5.8 MHz). As a result, the pseudo-envelope follower power management system transfer function, V CC /V RAMPS , may be flattened up to about 35 MHz.

FIG. 13 depicts an embodiment of a pseudo-envelope follower power management system 10 G including a buck converter 13 G and a parallel amplifier circuit 14 G having an open loop assist circuit 39 and parallel amplifier circuitry 32 . In some alternative embodiments of the pseudo-envelope follower power management system of FIG. 13 , the parallel amplifier 35 may be a rechargeable parallel amplifier. As an example, the parallel amplifier 35 may be a rechargeable parallel amplifier similar to the embodiments of the rechargeable parallel amplifier depicted in FIGS. 12B-C and FIGS. 12E-F .

FIG. 14 depicts another embodiment of a pseudo-envelope follower power management system 10 H including a multi-level charge pump buck converter 12 H and a parallel amplifier circuit 14 H having an open loop assist circuit 39 and parallel amplifier circuitry 32 . In some alternative embodiments of the pseudo-envelope follower power management system of FIG. 14 , the parallel amplifier 35 may be a rechargeable parallel amplifier similar to the embodiments of the rechargeable parallel amplifier depicted in FIGS. 12B-C and FIGS. 12E-F .

FIG. 15 depicts another embodiment of a pseudo-envelope follower power management system 10 I including a multi-level charge pump buck converter 12 I and a parallel amplifier circuit 14 I having a parallel amplifier circuitry 32 and a V OFFSET loop circuit 41 E. In some embodiments, the V OFFSET loop circuit 41 E may be similar to the V OFFSET loop circuit 41 A, depicted in FIG. 18A , the V OFFSET loop circuit 41 B, depicted in FIG. 18B , or the V OFFSET loop circuit 41 , depicted in FIG. 8 . Accordingly, although not shown in FIG. 15 , in some example embodiments, the V OFFSET loop circuit 41 E may be coupled to a controller 50 , in a fashion similar to that depicted in FIGS. 18A-B . In those embodiments that include the controller 50 coupled to the V OFFSET loop circuit 41 E, the controller 50 may be used to configure the V OFFSET loop circuit 41 E. In addition, in some alternative embodiments of the pseudo-envelope follower power management system 10 I, depicted in FIG. 15 , the parallel amplifier 35 may be a rechargeable parallel amplifier similar to the embodiments of the rechargeable parallel amplifier that are depicted in FIGS. 12B-C and FIGS. 12E-F .

›DETAILED DESCRIPTION · 37 of 67

FIG. 16 depicts another embodiment of a pseudo-envelope follower power management system 10 J including a multi-level charge pump buck converter 12 J and parallel amplifier circuitry 32 having a parallel amplifier circuitry 32 , a V OFFSET loop circuit 41 F, an open loop assist circuit 39 and a parallel amplifier output impedance compensation circuit 37 . In some embodiments, the V OFFSET loop circuit 41 F may be similar to the V OFFSET loop circuit 41 A, depicted in FIG. 18A , the V OFFSET loop circuit 41 B, depicted in FIG. 18B , or the V OFFSET loop circuit 41 , depicted in FIG. 8 . Accordingly, although not shown in FIG. 16 , the V OFFSET loop circuit 41 F may be coupled to a controller 50 , (as depicted in FIGS. 18A-B ), which may be used to configure the V OFFSET loop circuit 41 F. In addition, in some alternative embodiments of the pseudo-envelope follower power management system 10 J, depicted in FIG. 16 , the parallel amplifier 35 may be a rechargeable parallel amplifier similar to the embodiments of the rechargeable parallel amplifier depicted in FIGS. 12B-C and FIGS. 12E-F .

FIG. 17A depicts another embodiment of a pseudo-envelope follower power management system 10 K including a buck converter 13 K and parallel amplifier circuitry 32 having a rechargeable parallel amplifier 35 B. The parallel amplifier output current, I PARA — AMP , may be the sole contributor to the parallel amplifier circuit output current I PAWA — OUT , of the parallel amplifier circuit 14 K. In addition, because the parallel amplifier circuit 14 K does not have an open loop assist circuit, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is equal to the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , current provided by the parallel amplifier sense circuit 36 . Also, in some alternative embodiments of the pseudo-envelope follower power management system 10 K, depicted in FIG. 17A , the rechargeable parallel amplifier 35 B may be a rechargeable parallel amplifier similar to the embodiments of the rechargeable parallel amplifier depicted in FIG. 12E .

FIG. 17B depicts another embodiment of a pseudo-envelope follower power management system 10 L including a multi-level charge pump buck converter 12 L and a parallel amplifier circuitry 32 having a parallel amplifier circuitry 32 . The parallel amplifier output current, I PARA — AMP , may be the sole contributor to the parallel amplifier circuit output current I PAWA — OUT , of the parallel amplifier circuit 14 L. In addition, because the parallel amplifier circuit 14 L does not have an open loop assist circuit, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , may be equal to the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , current provided by the parallel amplifier sense circuit 36 . In addition, in some alternative embodiments of the pseudo-envelope follower power management system 10 L, depicted in FIG. 17B , the rechargeable parallel amplifier 35 C may be a rechargeable parallel amplifier similar to the embodiments of the rechargeable parallel amplifier depicted in FIG. 12E-F .

FIG. 18B depicts another embodiment of the pseudo-envelope follower power management system 10 E, which is similar to the pseudo-envelope follower power management systems 10 A and 10 B, as depicted in FIGS. 1A-B and 2 A-B. The pseudo-envelope follower power management system 10 E includes a multi-level charge pump buck converter 12 C, a parallel amplifier circuit 14 D, a controller 50 , a clock management circuit 260 , a μC charge pump circuit 262 , a battery level sense circuit 264 , and a parallel amplifier power source selection circuit 272 operably configured to generate a parallel amplifier supply voltage, V CC , on the bypass capacitor 19 . The bypass capacitor 19 has a bypass capacitance, C BYPASS .

Similar to the embodiments of the pseudo-envelope follower power management system 10 A- 10 B of FIGS. 2A-2B , the pseudo-envelope follower power management system 10 E may include a multi-level charge pump buck converter 12 C that is similar to the multi-level charge pump buck converters 12 A-B, depicted in FIGS. 2A-B . Like the multi-level charge pump buck converters 12 A-B, the multi-level charge pump buck converter 12 C may include a switcher control circuit 52 . However, unlike the multi-level charge pump buck converters 12 A-B, the multi-level charge pump buck converter 12 C further includes a multi-level charge pump circuit 258 configured to generate an internal charge pump node parallel amplifier supply 294 . In some embodiments of the multi-level charge pump buck converter 12 C, the multi-level charge pump circuit 258 may provide 1.5×V BAT as the internal charge pump node parallel amplifier supply 294 . In other embodiments of the multi-level charge pump buck converter 12 C, the multi-level charge pump circuit 258 , the output voltage level of the internal charge pump node parallel amplifier supply 294 may vary between 1.5×V BAT and 2×V BAT depending upon the operational mode of the multi-level charge pump circuit 258 . Example embodiments of the multi-level charge pump circuit 258 may include the multi-level charge pump circuit 258 A and the multi-level charge pump circuit 258 B, depicted in the respective FIGS. 7A-B . Also similar to the multi-level charge pump buck converters 12 A-B, depicted in FIGS. 2A-B , the multi-level charge pump buck converter 12 C may include a switching voltage output 26 .

In addition, similar to the embodiments of the pseudo-envelope follower power management system 10 A- 10 B, depicted in FIGS. 2A-2B , the switching voltage output 26 of the multi-level charge pump buck converter 12 C may be coupled to a power inductor 16 . The power inductor 16 is coupled to the bypass capacitor 19 , which has a bypass capacitance, C BYPASS , to form a low pass filter for the multi-level charge pump buck converter 12 C. In addition, similar to the parallel amplifier circuit 14 A and the parallel amplifier circuit 14 B of FIGS. 2A-2B , the parallel amplifier circuit 14 D may include a parallel amplifier output 32 A that is coupled to the power amplifier supply voltage, V CC , via the coupling circuit 18 . In the case where the coupling circuit 18 provides AC (alternating current) coupling between the parallel amplifier output 32 A of the parallel amplifier circuit 14 D and the power amplifier supply voltage, V CC , an offset voltage, V OFFSET , may be developed across the coupling circuit 18 . Also, the parallel amplifier circuit 14 D may include the parallel amplifier circuitry 32 operably coupled to the parallel amplifier output 32 A.

›DETAILED DESCRIPTION · 38 of 67

However, unlike the parallel amplifier circuit 14 A, depicted in FIG. 2A , and the parallel amplifier circuit 14 B, depicted in FIG. 2B , the parallel amplifier circuit 14 D may be configured to power the parallel amplifier circuitry 32 with a parallel amplifier supply voltage, V SUPPLY — PARA — AMP , instead of the supply input 24 , (V BAT ). The parallel amplifier supply voltage, V SUPPLY — PARA — AMP , may be provided by the parallel amplifier power source selection circuit 272 . In one example embodiment of the parallel amplifier circuit 14 D, the parallel amplifier 35 may be configured similar to the parallel amplifier 35 D, depicted in FIG. 12D . Alternatively, in other embodiments, the parallel amplifier 35 may be a rechargeable parallel amplifier similar to the rechargeable parallel amplifiers 35 E-F, respectively depicted in FIGS. 12E-F .

The parallel amplifier power source selection circuit 272 may include a first input coupled to the μC charge pump output of the μC charge pump circuit 262 and a second input coupled to the internal charge pump node parallel amplifier supply 294 of the multi-level charge pump circuit 258 . The parallel amplifier power source selection circuit 272 may also be coupled to the controller 50 via a source selection control signal 296 . The parallel amplifier power source selection circuit 272 may include an output configured to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , to the parallel amplifier circuit 14 D based upon the state of the source selection control signal 296 . In addition, the parallel amplifier power source selection circuit 272 may be coupled to the controller 50 via the source selection control signal 296 . Via the source selection control signal 296 , the controller 50 may configure the parallel amplifier power source selection circuit 272 to select either the internal charge pump node parallel amplifier supply 294 or the μC charge pump output in order to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , to the parallel amplifier circuit 14 D. In some alternative embodiments of the pseudo-envelope follower power management system 10 E, the parallel amplifier power source selection circuit 272 may be eliminated. In this case, either the internal charge pump node parallel amplifier supply 294 or the μC charge pump output of the μC charge pump circuit 262 may be directly coupled to the parallel amplifier circuit 14 D in order to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP . For example, some embodiments of the multi-level charge pump buck converter 12 C may not provide an internal charge pump node parallel amplifier supply 294 as an output. In this case, the μC charge pump output of the μC charge pump circuit 262 is directly coupled to the parallel amplifier circuit 14 D to provide the parallel amplifier supply voltage V SUPPLY — PARA — AMP , as the operational voltage for the parallel amplifier 35 and associated circuitry.

In still another alternative arrangement (not shown), some embodiments of the pseudo-envelope follower power management system 10 E may eliminate the parallel amplifier power source selection circuit 272 . In this case, the μC charge pump output of the μC charge pump circuit 262 and the internal charge pump node parallel amplifier supply 294 are coupled together to form a parallel amplifier supply node that provides the parallel amplifier supply voltage, V SUPPLY — PARA — AMP . As an example, in the case where the multi-level charge pump circuit 258 is similar to either the multi-level charge pump circuit 258 A, depicted in FIG. 7B , or the multi-level charge pump circuit 258 B, depicted in FIG. 7C , the desired source for providing the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , may be managed by enabling and disabling the μC charge pump circuit 262 and controlling the switch state of the ninth switch 119 of either the multi-level charge pump circuit 258 A or the multi-level charge pump circuit 258 B. As an example, when the μC charge pump circuit 262 is disabled by setting the μC charge pump, μBB RATIO , to OFF, the μC charge pump output floats. In a similar fashion, setting the switch state of the ninth switch 119 to be open, for either the multi-level charge pump circuit 258 A or the multi-level charge pump circuit 258 B, depicted in the respective FIGS. 7B-C , operably disconnects the internal circuitry of the multi-level charge pump circuit 258 A and the multi-level charge pump circuit 258 B from the parallel amplifier supply node.

The μC charge pump circuit 262 includes a supply input coupled to supply input 24 , (V BAT ), provided by the battery and a μC charge pump output configured to provide a μC charge pump output voltage, V μC — OUT . In addition, the μC charge pump circuit 262 may be configured to receive a μC charge pump clock 276 from the clock management circuit 260 . The μC charge pump clock 276 may be used to govern the operation of the μC charge pump circuit 262 . The μC charge pump circuit 262 is also coupled via a μC charge pump control bus 278 to the controller 50 . As described below relative to FIGS. 19A-B , some embodiments of the μC charge pump circuit 262 may be configured to boost the supply input 24 , (V BAT ), provided by the battery to generate a μC charge pump output voltage, V μC — OUT , that is greater than the supply input 24 , (V BAT ). Other embodiments of the μC charge pump circuit 262 be may be configured to buck the supply input 24 , (V BAT ) to generate a μC charge pump output voltage, V μC — OUT , that is less than the supply input 24 , (V BAT ). The controller 50 may use the μC charge pump control bus 278 to configure the μC charge pump circuit 262 to operate in various operational modes in order to generate specific voltage levels at the μC charge pump output. For example, the μC charge pump circuit 262 may be configured to generate a μC charge pump output voltage, V μC — OUT , that provides various voltage levels dependent upon the mode of operation of the μC charge pump circuit 262 . This permits the multi-level charge pump buck converter 12 C to provide a desired voltage level as the μC charge pump output voltage, V μC — OUT , and dependent upon the need of the parallel amplifier 35 on the parallel amplifier circuit 14 D with different voltage output levels dependent upon the needs of the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B .

›DETAILED DESCRIPTION · 39 of 67

The clock management circuit 260 , depicted in FIG. 18B , may include a clock reference 139 , a divider circuit 266 , a clock selection circuit 268 , and an oscillator 270 . The clock management circuit 260 may be coupled to controller 50 via various control signals and/or buses. Based upon control inputs received from the controller 50 , the clock management circuit 260 may be configured to generate a μC charge pump clock 276 , which is provided to the μC charge pump circuit 262 . The controller 50 may configure the clock management circuit 260 to generate the μC charge pump clock 276 based upon a variety of clock sources.

The clock reference 139 may be operably configured to provide a clock reference signal 139 A to the FLL circuit 54 of the multi-level charge pump buck converter 12 C. The FLL circuit 54 may be configured to operate with the clock reference 139 similar to the operational description of the FLL circuit 54 A of FIG. 3A or the FLL circuit 54 B of FIG. 3B . In each case, as depicted in FIGS. 3A and 3B , the clock reference 139 may be configured to provide a clock reference signal 139 A to the FLL circuit 54 A or the FLL circuit 54 B. In addition to governing various timing aspects regarding operation of the multi-level charge pump buck converter 12 C, similar to the FLL circuit 54 A of FIG. 3A , some embodiments of the FLL circuit 54 may be configured to provide a threshold scalar 137 A signal, as depicted in FIG. 3A , to adjust the operating frequency of the multi-level charge pump buck converter 12 C. Alternatively, in other embodiments of the FLL circuit 54 , similar to the FLL circuit 54 B, depicted in FIG. 3B , the FLL circuit 54 may be configured to provide a threshold scalar′ 137 B signal, as depicted in FIG. 3B , to adjust the operating frequency of the multi-level charge pump buck converter 12 C.

In addition, as depicted in FIG. 18B , the FLL circuit 54 may be further configured to provide an FLL system clock 280 to the switcher control circuit 52 and the divider circuit 266 . The FLL system clock 280 may be synchronized or based upon the operating frequency of the multi-level charge pump buck converter 12 C, as previously described. As a result, in some embodiments of the pseudo-envelope follower power management system 10 E, the FLL circuit 54 provides an FLL system clock 280 that is synchronized to the switching of the multi-level charge pump buck converter 12 C.

The divider circuit 266 may be configured to receive a clock divider control signal 284 from the controller 50 . Based upon the clock divider control signal 284 received from the controller 50 , the divider circuit 266 may divide the FLL generated clock to provide a divided FLL clock 282 to the clock selection circuit 268 . In addition, the clock selection circuit 268 may be configured to receive the clock reference signal 139 A from the clock reference 139 and an oscillator reference clock 288 from the oscillator 270 . Alternative embodiments of the multi-level charge pump buck converter 12 C may not include an FLL circuit 54 or the FLL circuit 54 may not be configured to provide a FLL system clock 280 to the clock management circuit 260 .

The oscillator 270 may be operably coupled to the controller 50 via an oscillator control signal 286 . The controller 50 may be configured to modify the output frequency of the oscillator 270 via the oscillator control signal 286 . The controller 50 may be further configured to disable or enable the oscillator 270 in order to reduce noise generated by the clock management circuit 260 . In other embodiments of the clock management circuit 260 , the oscillator 270 may be a fixed oscillator.

Accordingly, the controller 50 may configure the clock selection circuit 268 to provide one of the divided FLL clock 282 , the clock reference signal 139 A, or the oscillator reference clock 288 to the μC charge pump clock 276 . As discussed below relative to FIGS. 19A-B , example embodiments of the μC charge pump circuit 262 may use the μC charge pump clock 276 to govern the timing between phases of operation of the μC charge pump circuit 262 .

In some embodiments of the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , the controller 50 may advantageously configure the clock selection circuit 268 to provide the divided FLL Clock 282 as the μC charge pump clock 276 . As a result, the switching operations of the μC charge pump circuit 262 may be substantially synchronous to the switching operations of the multi-level charge pump buck converter 12 C. In some embodiments of the pseudo-envelope follower power management system 10 E, the synchronicity of operations between the μC charge pump circuit 262 and the multi-level charge pump buck converter 12 C may improve or reduce the noise performance provided at the power amplifier supply voltage, V CC . Alternatively, the controller 50 may configure the clock selection circuit 268 to provide the clock reference signal 139 A as the μC charge pump clock 276 to the μC charge pump circuit 262 . In this mode of operation, the switching between various phases of operation in the μC charge pump circuit 262 may be relatively stable. Alternatively, in still other embodiments of the pseudo-envelope follower power management system 10 E, the clock selection circuit 268 is configured to provide the fixed frequency reference clock as the μC charge pump clock 276 .

In addition, the controller 50 may further provide an FLL circuit control signal 292 to govern the operation of the FLL circuit 54 of the multi-level charge pump buck converter 12 C. The FLL circuit control signal 292 may include one or more control signals used to configure the FLL circuit 54 . Via the FLL circuit control signal 292 , the controller 50 may configure various time constants and control parameters resident in the FLL circuit 54 (not shown) to optimally extract the operating frequency of the multi-level charge pump buck converter 12 C so as to reduce the overall voltage ripple that occurs at the power amplifier supply voltage V CC . The configuration of the FLL circuit 54 may depend upon various factors, including, but not limited to the maximum expected parallel amplifier supply voltage V CC — MAX , the minimum expected parallel amplifier supply voltage V CC — MIN , the expected waveform generated by the power amplifier, the envelope and signal transmission characteristics of the signal to be transmitted, the peak-to-average ratio of the envelope of the signal to be transmitted, the data rate, the bandwidth of the channel and/or the type of modulation used to the desired waveform. Moreover, controller 50 may configure the FLL circuit 54 to minimize the overall noise or output ripple.

›DETAILED DESCRIPTION · 40 of 67

The parallel amplifier power source selection circuit 272 is configured to receive the internal charge pump node parallel amplifier supply 294 from the multi-level charge pump circuit 258 , of the multi-level charge pump buck converter 12 C, or the μC charge pump circuit output voltage, V μC — OUT , which is generated at the μC charge pump output. The parallel amplifier power source selection circuit 272 may be configured to be operably coupled to the controller 50 via a source selection control signal. Via the source selection control signal 296 , the controller 50 may configure the parallel amplifier power source selection circuit 272 to select a desired input supply from either the internal charge pump node parallel amplifier supply or the μC charge pump output, to be provided as the parallel amplifier supply voltage V SUPPLY — PARA — AMP to the parallel amplifier circuitry 32 .

In an alternative embodiment of the pseudo-envelope follower power management system 10 E, the parallel amplifier power source selection circuit 272 may be eliminated in the case where the internal charge pump node parallel amplifier supply or the μC charge pump output are directly coupled to the parallel amplifier supply, V SUPPLY — PARA — AMP . For example, some embodiments of the multi-level charge pump buck converter 12 C may include a multi-level charge pump that does not provide an internal charge pump node parallel amplifier supply as an output. In this case, the μC charge pump output of the μC charge pump circuit 262 is directly coupled to the parallel amplifier circuit 14 C to provide the parallel amplifier supply voltage V SUPPLY — PARA — AMP , as the operational voltage for the parallel amplifier 35 and associated circuitry.

In addition, similar to the parallel amplifier circuit 14 A and the parallel amplifier circuit 14 B, depicted in FIGS. 2A-2B , the parallel amplifier circuit 14 D may also include an embodiment of the V OFFSET loop circuit 41 as V OFFSET load circuit 41 B. The V OFFSET load circuit 41 B may be configured to regulate the offset voltage, V OFFSET , that is developed across the coupling circuit 18 . Similar to the V OFFSET loop circuit 41 of FIGS. 2A-2B , the V OFFSET loop circuit 41 B may provide a threshold offset current 42 , I THRESHOLD — OFFSET , to the switcher control circuit 52 of the multi-level charge pump buck converter 12 C, where the threshold offset current 42 , I THRESHOLD — OFFSET , provides an estimate of the magnitude of the offset voltage, V OFFSET , appearing across the coupling circuit 18 .

The V OFFSET loop circuit 41 B may include a summing circuit 300 , a V OFFSET target signal section circuit 308 , a pre-filter 313 , and an integrator with zero compensation 314 operably configured to generate the threshold offset current 42 , I THRESHOLD — OFFSET , based upon the power amplifier supply voltage, V CC , the parallel amplifier output 32 A, and a V OFFSET target signal 302 . The V OFFSET target signal section circuit 308 may include a first input configured to receive a target offset voltage parameter, V OFFSET — TARGET , a second input configured to receive the V RAMP signal, and a third input configured to receive a filtered V RAMP signal from the pre-filter 313 . The V OFFSET target signal section circuit 308 may be configured to receive a target selection signal 310 from the controller 50 . Based upon the target selection signal 310 received from the controller 50 , the V OFFSET target signal section circuit 308 provides one of the target offset voltage parameter, V OFFSET — TARGET , the V RAMP signal, or the filtered V RAMP signal as a V OFFSET target signal 302 to the summing circuit 300 . In some alternative embodiments, the V OFFSET target signal section circuit 308 may be controlled via a V OFFSET control bus 312 that is coupled to the V OFFSET loop circuit 41 B.

The pre-filter 313 may be similar to the frequency pre-distortion circuit 254 , depicted in FIG. 10 . Similar to the frequency pre-distortion circuit 254 , the pre-filter 313 may include a frequency equalizer circuit that includes programmable time constants. Illustratively, the programmable time constants may include a programmable pole time constant, Tau P , and a programmable zero time constant, Tau Z . The controller 50 may adjust the values of the programmable pole time constant, Tau P , and a programmable zero time constant, Tau Z , to adjust the frequency response of the pre-filter 313 . In some embodiments of the parallel amplifier circuit 14 D, the output of the frequency pre-distortion circuit 254 may be used as the third input to the V OFFSET target signal section circuit 308 instead of providing a dedicated pre-filter 313 .

The summing circuit 300 may include a positive terminal operably coupled to the power amplifier supply voltage, V CC . a first negative terminal coupled to the parallel amplifier output 32 A, and a second negative terminal configured to receive the V OFFSET target signal 302 . The summing circuit 300 subtracts the parallel amplifier output 32 A and the V OFFSET target signal from the power amplifier supply voltage, V CC , to generate a V OFFSET error signal 304 . The V OFFSET error signal 304 may be provided to the integrator with zero compensation 314 , which filters the V OFFSET error signal 304 to generate a threshold offset current 42 , I THRESHOLD — OFFSET .

The V OFFSET loop circuit 41 B may be configured to create an almost constant DC voltage across the coupling circuit 18 in order to shift the power amplifier supply voltage, V CC , down by a fixed amount in order to minimize the peak voltage present at the parallel amplifier output 32 A.

As discussed with respect to the various embodiments of the switcher control circuits 52 A-C and 52 E-G, depicted in FIGS. 3A-C and E-G, FIGS. 4A-C and E-G, FIGS. 5A-C and E-G, and FIGS. 6A-C , the shunt level threshold 124 , the series level threshold 126 , the first boost level threshold 128 , and a second boost level threshold 130 may be offset by the threshold offset current 42 , I THRESHOLD — OFFSET , which is generated by the V OFFSET loop circuit 41 B to control the offset voltage, V OFFSET , across the coupling circuit 18 , as depicted in FIGS. 18A-D .

›DETAILED DESCRIPTION · 41 of 67

The integrator with zero compensation 314 may include a filter having a first time constant, Tau 0 , and a second time constant, Tau 1 . The integrator with zero compensation 314 may have a filter response that is equivalent to a Laplace transfer function equal to [(1+Tau 0 *s)/(Tau 1 *s)]. The values of the first time constant, Tau 0 , and a second time constant, Tau 1 , may be programmed by the controller 50 via the V OFFSET control bus 312 . The values of the first time constant, Tau 0 , and a second time constant, Tau 1 . may be selected to optimize the bandwidth of the V OFFSET loop circuit to provide loop stability and a desired response time depending upon the capacitance of the coupling circuit 18 across which the offset voltage, V OFFSET , is developed.

In addition, the V OFFSET loop circuit 41 B may further be configured to permit selection of the value of the first time constant, Tau 0 , and a second time constant, Tau 1 , dependent upon whether the coupling circuit 18 requires pre-charging before initiation of a data burst to be sent by the linear RF power amplifier 22 , as depicted, for example, in FIGS. 1A-B and 2 A-B. For example, if the data burst to be sent is a first data burst of the transmission, the controller 50 may determine that the coupling circuit 18 requires pre-charging prior to transmission of the first data burst.

In some embodiments of the V OFFSET loop circuit 41 B, the controller 50 may store a first startup time constant, Tau 0 — startup, and a second startup time constant, Tau 1 — startup, as local parameters. The V OFFSET loop circuit 41 B may be configured to use the first startup time constant, Tau 0 — startup, and the second startup time constant, Tau 1 — startup, during a pre-charging phase of operation of the V OFFSET loop circuit 41 B. When the V OFFSET loop circuit 41 B is configured to operate using the first startup time constant, Tau 0 — startup, as the first time constant, Tau 0 , and the second startup time constant, Tau 1 — startup, as the second time constant, Tau 1 , the operational bandwidth of the V OFFSET loop circuit 41 B is increased to permit faster pre-charging of the coupling circuit 18 .

In addition, in some embodiments of the V OFFSET loop circuit 41 B, the controller 50 may store a first normal time constant, Tau 0 — normal, and a second normal time constant, Tau 1 — normal, as local parameters in the V OFFSET loop circuit 41 B. When the V OFFSET loop circuit 41 B is configured to operate using the first normal constant, Tau 0 — normal, as the first time constant, Tau 0 , and the second normal time constant, Tau 1 — normal, as the second time constant, Tau 1 , the operational bandwidth of the V OFFSET loop circuit 41 B is decreased to operate in a normal mode of operation.

Some embodiments of the V OFFSET loop circuit 41 B may include a pre-charge mode of operation that permits the controller to place the V OFFSET loop circuit 41 B into a pre-charge mode of operation for a predetermined period of time. For example, the V OFFSET loop circuit 41 B may include a pre-charge timer (not shown) that may be programmed by the controller 50 to generate a timer event after a predetermined time period. When in the pre-charge mode of operation, the V OFFSET loop circuit 41 B uses the first startup time constant, Tau 0 — startup, as the first time constant, Tau 0 , and the second startup time constant, Tau 1 — startup, as the second time constant, Tau 1 , which increases the operational bandwidth of the V OFFSET loop circuit 41 B. As an example, when starting from power-off mode to active mode, the time constant of the V OFFSET loop circuit 41 B may be programmatically reduced by the controller 50 by up to a factor of five to allow a quick initial pre-charging of the coupling circuit 18 . For example, pre-charging may be done prior to the beginning of a transmission-slot in order to reduce the time to have the voltage completely settled to the target value for the first power-up. As an example, the transmission-slot may be a burst transmission-slot in which data is transmitted by the linear RF power amplifier. The controller 50 may configure the V OFFSET loop circuit 41 B to operate in a higher bandwidth during the initial pre-charging of reactive components of the coupling circuit 18 .

In some cases, the loop bandwidth of the V OFFSET loop circuit 41 B may be set to provide up to five times the bandwidth used at the beginning of a burst transmission time-slot. The controller 50 operably re-configures the V OFFSET loop circuit 41 B back to a lower or operational bandwidth at the beginning of the burst transmission-slot. In other alternative embodiments of the pseudo-envelope follower power management system, the controller 50 operably re-configures the V OFFSET loop circuit 41 B to have a bandwidth between 3 and 7 times the bandwidth used at the beginning of a burst transmission time-slot. Advantageously, configuring the V OFFSET loop circuit 41 B to operate with a higher loop bandwidth during initial pre-charging of the reactive components of the coupling circuit 18 decreases the startup delay of the pseudo-envelope follower power management system, which provided an improvement in overall power efficiency.

The V OFFSET loop circuit 41 B may be monitored and modified in a dynamic fashion. For example, the timing/filter parameters associated with the integrator with zero compensation circuit and desired V OFFSET voltage, set by the V OFFSET — TARGET parameter, may be monitored and modified by the controller 50 on a burst time-slot basis.

The V OFFSET loop circuit 41 B may be configured to operate in a higher loop band width mode of operation when no modulation is present on the V RAMP signal. For example, at either the beginning of the slot or between inter-slots, when the V RAMP signal is inactive, the controller 50 may configure the V OFFSET loop circuit 41 B to operate in a higher bandwidth mode of operation to improve initial startup regulation of the offset voltage, V OFFSET . Alternatively, or in addition, the V OFFSET loop circuit 41 B may be configured to switch from the V OFFSET loop lower loop bandwidth mode of operation to V OFFSET loop higher loop band width mode of operation when no modulation is present on the V RAMP signal.

›DETAILED DESCRIPTION · 42 of 67

As another example, the controller 50 may program the pre-charge timer (not shown) to trigger an event after a predetermined pre-charge time period. Upon the trigger event, the V OFFSET loop circuit 41 B may be automatically re-configured to set the first normal time constant, Tau 0 , to be equal to Tau 0 — normal and the second time constant, Tau 1 , to be equal to Tau 1 — normal. As a result, after the predetermined pre-charge time period, the V OFFSET loop circuit 41 B is re-configured to operate with a normal bandwidth to ensure loop stability. This has the advantage of permitting the V OFFSET loop circuit 41 B to operate in a higher bandwidth mode during pre-charging and in a lower bandwidth mode during normal operation without requiring the controller 50 to reconfigure the V OFFSET loop circuit 41 B after a predetermined pre-charge period of time to operate in a mode having a bandwidth that is appropriate for normal operation of the pseudo-envelope follower power management system.

In the various embodiments of the switcher control circuit depicted in FIGS. 3A-C and E-G, FIGS. 4A-C and E-G, FIGS. 5A-C and E-G, and FIGS. 6A-C , the threshold offset current 42 , I THRESHOLD — OFFSET , generated by the V OFFSET loop circuit 41 is generally used to raise and lower the point at which the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 trigger. However, in some alternative embodiment of the threshold detector and control circuits 132 A-C and E-G, the threshold offset current 42 , I THRESHOLD — OFFSET , may be used to only shift the triggering threshold of less than all of the first comparator 140 , the second comparator 142 , the third comparator 144 , and the fourth comparator 146 . For example, referring to FIG. 4C , the threshold detector and control circuit 132 C may be reconfigured such that the threshold offset current 42 , I THRESHOLD — OFFSET , only shifts the triggering threshold of the second comparator 142 . The effect is to only shift the triggering threshold of the comparator associated with the series level threshold 126 based upon the threshold offset current 42 , I THRESHOLD — OFFSET . Similarly, as another example of an alternative embodiment, the threshold detector and control circuit 132 G, depicted in FIG. 4G , may be reconfigured such that the threshold offset current 42 , I THRESHOLD — OFFSET , only shifts the triggering threshold of the first comparator 140 . The effect is to only shift the triggering threshold of the comparator associated with the shunt level threshold 124 based upon the threshold offset current 42 , I THRESHOLD — OFFSET .

The shunt level threshold 124 , the series level threshold 126 , the first boost level threshold 128 , and the second boost level threshold 130 may be offset by threshold offset current 42 , I THRESHOLD — OFFSET , which is generated by the V OFFSET loop circuit 41 B to control the offset voltage, V OFFSET , across the coupling circuit 18 , as depicted in FIGS. 18A-D .

The battery level sense circuit 264 may be coupled to the controller 50 via the battery level sense signal. The battery level sense circuit 264 may be operably configured to measure or determine the voltage level of the battery, (V BAT ). The voltage measured or determined voltage level of the battery may be provided to or obtained by the controller 50 via the battery level sense circuit. In alternative embodiments, not shown, the battery level sense circuit 264 may be configured to interface with the controller 50 via a control bus. Accordingly, the controller may use the voltage level of the battery, (V BAT ), to configure the various operational components of the pseudo-envelope follower power management system 10 E.

FIG. 18A further depicts another embodiment of a pseudo-envelope follower power management system 10 C that is similar to the embodiment of the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , except that the parallel amplifier circuit 14 D is replaced by the parallel amplifier circuit 14 C. The parallel amplifier circuit 14 C is similar to the parallel amplifier circuit 14 D, depicted in FIG. 18B , except that the V OFFSET loop circuit 41 B is replaced by the V OFFSET loop circuit 41 A. The V OFFSET loop circuit 41 A is operably configured to operate in a similar fashion as the V OFFSET loop circuit 41 B except that the integrator with zero compensation circuit is replaced with a K ERROR — GAIN circuit 306 configured to receive the V OFFSET error signal 304 from the summing circuit 300 . The K ERROR — GAIN circuit 306 may be configured to multiply the V OFFSET error signal 304 by a K ERROR — GAIN parameter to generate the threshold offset current 42 , I THRESHOLD — OFFSET . The controller 50 may be configured to modify the K ERROR — GAIN parameter dependent upon the operational needs of the linear RF power amplifier.

Illustratively, unlike the operation of the V OFFSET loop circuit 41 B described above, where the filter having a first time constant, Tau 0 , and the second time constant, Tau 1 , may be modified to optimize the bandwidth of the V OFFSET loop circuit 41 B during pre-charging of the coupling circuit 18 , prior to initiation of a data burst to be sent by the linear RF power amplifier 22 , as depicted, for example, in FIGS. 1A-B and 2 A-B, the controller 50 may selectively modify the K ERROR — GAIN value to provide a pre-charge mode of operation for a pre-determined period of time. During the pre-charge mode of operation, the controller 50 may increase the value of the K ERROR — GAIN to effectively provide higher loop bandwidth. After a predetermined period of time, the controller may decrease the K ERROR — GAIN value to provide a lower loop bandwidth to ensure stable operation of the V OFFSET loop circuit 41 A.

While the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A , and the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , only depict the respective parallel amplifier circuit 14 C and parallel amplifier circuit 14 D providing the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , as a feedback signal to the switcher control circuit 52 of the multi-level charge pump buck converter 12 C, this is by example and not limitation. Accordingly, some embodiments of the pseudo-envelope follower power management system 10 C and the pseudo-envelope follower power management system 10 E may further include an open loop assist circuit similar to the open loop assist circuit 39 , as depicted in FIG. 2A with respect to the pseudo-envelope follower power management system 10 A and depicted in FIG. 10B with respect to the pseudo-envelope follower power management system 10 B, and/or the example embodiments of the open loop assist circuit 39 , the open loop assist circuit 39 A, depicted in FIG. 9A , and the open loop assist circuit 39 B, depicted in FIG. 9B . In this case, as shown in FIGS. 2A-B , the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is combined with the open loop assist circuit output current estimate, I ASSIST — SENSE , as depicted in FIGS. 2A-B , to form the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , which is used as a feedback signal to the switcher control circuit 52 . Accordingly, the switcher control circuit 52 and operation of the multi-level charge pump buck converter 12 C depicted in FIGS. 18A-B may also incorporate various combinations of the operational features and functions of the embodiments of the switcher control circuits 52 A-D, depicted in FIGS. 3A-D , the threshold detector and control circuits 132 A-D, depicted in FIGS. 4A-D , and the circuitry and state machines associated with the logic circuits 148 A-D, depicted in FIGS. 4A-D .

›DETAILED DESCRIPTION · 43 of 67

FIG. 18C depicts an embodiment of a pseudo-envelope follower power management system 10 D that is similar to the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A and discussed below. However, unlike the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A , the multi-level charge pump buck converter 12 C is replaced by a buck converter 13 A. As depicted in FIG. 18C , the buck converter 13 A, depicted in FIG. 18C , does not include a multi-level charge pump circuit 258 .

Also similar to the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A , the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C , further includes an embodiment of a V OFFSET loop circuit 41 A configured to provide a threshold offset current 42 , I THRESHOLD — OFFSET . However, unlike the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C , the threshold offset current 42 , I THRESHOLD — OFFSET , is provided to the switcher control circuit 259 of the buck converter 13 A.

In addition, because the buck converter 13 A does not include the multi-level charge pump circuit 258 , the parallel amplifier power source selection circuit 272 is eliminated and the μC charge pump output of the μC charge pump circuit 262 is directly coupled to the parallel amplifier circuit 14 C in order to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP to the parallel amplifier 35 of the parallel amplifier circuitry 32 .

As further depicted in FIG. 18C , unlike the multi-level charge pump buck converter 12 C, depicted in FIG. 18A , the buck converter 13 A also replaces the switcher control circuit 52 with a switcher control circuit 259 . Like the switcher control circuit 52 , the switcher control circuit 259 provides a series switch control signal 66 and a shunt switch control signal 68 to the switching circuit 58 . Like the switcher control circuit 52 depicted in FIG. 18A , the switcher control circuit 259 , depicted in FIG. 18C , may be further configured to receive the threshold offset current 42 , I THRESHOLD — OFFSET , from the V OFFSET loop circuit 41 A.

Although the embodiment of the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C , only depicts that the switcher control circuit 259 is configured to receive the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , as discussed above with respect to the embodiment of the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , and discussed below, with respect to the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A , this is by example and not by limitation. Some embodiments of the parallel amplifier circuit 14 C of FIG. 18C may further include an open loop assist circuit 39 similar to the open loop assist circuit 39 depicted in FIGS. 2A-B , and/or the example embodiments of the open loop assist circuit 39 , the open loop assist circuit 39 A, depicted in FIG. 9A , and the open loop assist circuit 39 B, depicted in FIG. 9B . Accordingly, in those cases where an open loop assist circuit is included in the parallel amplifier circuit 14 C, as depicted in FIGS. 2A-B , the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is combined with the open loop assist circuit output current estimate, I ASSIST — SENSE , depicted in FIGS. 2A-B , to form the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , that may be provided as a feedback signal to the switcher control circuit 259 .

Accordingly, example embodiments of the switcher control circuit 259 of the buck converter 13 A will now be described, as further depicted in FIGS. 3E-H . One example embodiment of the switcher control circuit 259 of the buck converter 13 A is depicted in FIG. 3E as switcher control circuit 52 E. The switcher control circuit 52 E is functionally similar to the switcher control circuit 52 A, depicted in FIG. 3A , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. As a result, for example, the threshold detector and control circuit 132 E, of FIG. 3E , does not include a first boost level threshold 128 , a second boost level threshold 130 , the third comparator 144 , or the fourth comparator 146 . Also, as discussed above, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , depicted in FIG. 3E , may be provided by the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , or, in the case where an open loop assist circuit is included in the parallel amplifier circuit 14 C of FIG. 18C , the sum of the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the open loop assist circuit output current estimate, I ASSIST — SENSE .

One embodiment of the threshold detector and control circuit 132 E is depicted in FIG. 4E , which is described with continuing reference to FIG. 3E and FIG. 5E . The threshold detector and control circuit 132 E may be functionally similar to the threshold detector and control circuit 132 A, depicted in FIG. 4A , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. As a result, the logic circuit 148 E is configured to operate as a buck converter based upon the magnitude of the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , relative to the shunt level threshold 124 and the series level threshold 126 . In addition, unlike the threshold detector and control circuit 132 A depicted in FIG. 4A , the first state machine used to control the logic circuit 148 E may be simplified. Illustratively, FIG. 5E depicts an example embodiment of a first state machine of the logic circuit 148 E that may include a shunt output mode 188 E and a series output mode 190 E, and which is described with continuing reference to FIGS. 3E and 4E .

In the shunt output mode 188 E, the logic circuit 148 E configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3E , is in an open state (not conducting). The logic circuit 148 E also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 , depicted in FIG. 3E , is in a closed state (conducting). As a result, the switching voltage output 26 of FIG. 3E is configured to provide a switching voltage, V SW , substantially equal to ground. As depicted in FIG. 5E , in response to assertion of the series level indication 152 A, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is greater than or equal to the series level threshold 126 , the logic circuit 148 E configures the first state machine to transition to the series output mode 190 E. Otherwise the first state machine remains in the shunt output mode 188 E.

›DETAILED DESCRIPTION · 44 of 67

In the series output mode 190 E, the logic circuit 148 E configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3E , is in a closed state (conducting). The logic circuit 148 E also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 , depicted in FIG. 3E , is in an open state (not conducting). As a result, the switching voltage output 26 , depicted in FIG. 3E , is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT , provided by the battery 20 . In response to de-assertion of the shunt level indication 150 A, depicted in FIG. 4E , which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP , is less than the shunt level threshold 124 , the logic circuit 148 E configures the first state machine to transition to the shunt output mode 188 E, as depicted in FIG. 5E . Otherwise, the logic circuit 148 E configures the first state machine to remain in the series output mode 190 E.

Another embodiment of the switcher control circuit 259 of the buck converter 13 A is depicted in FIG. 3F as switcher control circuit 52 F. The switcher control circuit 52 F may be functionally similar to the switcher control circuit 52 B, depicted in FIG. 3B , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. As a result, for example, the threshold detector and control circuit 132 F, of FIG. 3F , does not include the first boost level threshold 128 , the second boost level threshold 130 , the third comparator 144 , or the fourth comparator 146 . Also, as discussed above, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , depicted in FIG. 3F , may be provided by the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , or, in the case where an open loop assist circuit is included in the parallel amplifier circuit 14 C of FIG. 18C , the sum of the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the open loop assist circuit output current estimate, I ASSIST — SENSE .

One embodiment of the threshold detector and control circuit 132 F of FIG. 3F is further depicted in FIG. 4F . The threshold detector and control circuit 132 F may be functionally similar to the threshold detector and control circuit 132 B, depicted in FIG. 4B , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. As a result, for example, the logic circuit 148 F is configured to operate as a buck converter based upon the magnitude of the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, relative to the scaled shunt level threshold 176 and the scaled series level threshold 178 . In addition, unlike the threshold detector and control circuit 132 B, depicted in FIG. 4B , the first state machine used to control the logic circuit 148 F may be simplified. As an example, FIG. 5F depicts an example embodiment of a first state machine of the logic circuit 148 F that includes a shunt output mode 188 F and a series output mode 190 F, which is described with continuing reference to FIGS. 3F and 4F .

In the shunt output mode 188 F, the logic circuit 148 F, depicted in FIG. 4F , configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3F , is in an open state (not conducting). The logic circuit 148 F also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 , depicted in FIG. 3F , is in a closed state (conducting). As a result, the switching voltage output 26 of FIG. 3F is configured to provide a switching voltage, V SW , substantially equal to ground. As depicted in FIG. 4F , in response to assertion of the series level indication 152 B, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the scaled series level threshold 178 , the logic circuit 148 F configures the first state machine to transition to the series output mode 190 F. Otherwise the first state machine remains in the shunt output mode 188 F.

In the series output mode 190 F, the logic circuit 148 F configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3F , is in a closed state (conducting). The logic circuit 148 F also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 , depicted in FIG. 3F , is in an open state (not conducting). As a result, the switching voltage output 26 , depicted in FIG. 3F , is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . In response to de-assertion of the shunt level indication 150 B, depicted in FIG. 4F , which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than scaled shunt level threshold 176 , the logic circuit 148 F configures the first state machine to transition to the shunt output mode 188 F, as depicted in FIG. 5F . Otherwise, the logic circuit 148 F configures the first state machine to remain in the series output mode 190 F.

Another example embodiment of the switcher control circuit 259 of the buck converter 13 A is depicted in FIG. 3G as switcher control circuit 52 G. The switcher control circuit 52 G may be functionally similar to the switcher control circuit 52 C, depicted in FIG. 3C , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. As a result, for example, the threshold detector and control circuit 132 G, of FIG. 3G , does not include a first boost level threshold 128 , a second boost level threshold 130 , the third comparator 144 , or the fourth comparator 146 . Also, as discussed above, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , depicted in FIG. 3G , may be provided by the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , or, in the case where an open loop assist circuit is included in the parallel amplifier circuit 14 C of FIG. 18C , the sum of the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the open loop assist circuit output current estimate, I ASSIST — SENSE .

›DETAILED DESCRIPTION · 45 of 67

One embodiment of the threshold detector and control circuit 132 G of FIG. 3G is further depicted in FIG. 4G . The threshold detector and control circuit 132 G may be functionally similar to the threshold detector and control circuit 132 C, depicted in FIG. 4C , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. As a result, the logic circuit 148 G is configured to operate as a buck converter based upon the magnitude of the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, relative to the shunt level threshold 124 and the series level threshold 126 . In addition, unlike the threshold detector and control circuit 132 C, depicted in FIG. 4C , the first state machine used to control the logic circuit 148 G may be simplified. As an example, FIG. 5G depicts an example embodiment of a first state machine of the logic circuit 148 G that includes a shunt output mode 188 G and a series output mode 190 G, and which is described with continuing reference to FIGS. 3G and 4G .

In the shunt output mode 188 G, the logic circuit 148 G, depicted in FIG. 4G , configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3G , is in an open state (not conducting). The logic circuit 148 G also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 is in a closed state (conducting). As a result, the switching voltage output 26 of FIG. 3G is configured to provide a switching voltage, V SW , substantially equal to ground. In response to assertion of the series level indication 152 C, which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is greater than or equal to the series level threshold 126 , the logic circuit 148 G configures the first state machine to transition to the series output mode 190 G. Otherwise the first state machine remains in the shunt output mode 188 G.

In the series output mode 190 G, the logic circuit 148 G configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3G , is in a closed state (conducting). The logic circuit 148 G also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 , depicted in FIG. 3G , is in an open state (not conducting). As a result, the switching voltage output 26 , depicted in FIG. 3G , is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . In response to de-assertion of the shunt level indication 150 C, depicted in FIG. 4G , which indicates that the compensated parallel amplifier circuit output current estimate, I PAWA — COMP ′, is less than the shunt level threshold 124 , the logic circuit 148 G configures the first state machine to transition to the shunt output mode 188 G, as depicted in FIG. 5G . Otherwise, the logic circuit 148 G configures the first state machine to remain in the series output mode 190 G.

While FIGS. 3G and 4G do not depict the presence of an FLL circuit being used in combination with the switcher control circuit 52 G, an embodiment of the FLL circuit may be provided for use in the buck converter in order to provide an FLL system clock 280 to either the switcher control circuit 52 G or the clock management system of the pseudo-envelope follower power management system.

For the sake of completeness, another example embodiment of the switcher control circuit 259 of the buck converter 13 A is depicted in FIG. 3H as switcher control circuit 52 H. The switcher control circuit 52 H may be functionally similar to the switcher control circuit 52 D, depicted in FIG. 3D , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. Like the switcher control circuit 52 D of FIG. 3D , the switcher control circuit 52 H depicts the an embodiment of the switcher control circuit 259 that may be used when either the buck converter 13 A does not use the threshold offset current 42 , I THRESHOLD — OFFSET , to control the operation of the switcher control circuit 259 or, for the sake of completeness, the corresponding parallel amplifier circuit does not provide the threshold offset current 42 , I THRESHOLD — OFFSET , to the buck converter 13 A.

Like the switcher control circuit 52 D of FIG. 3D , the switcher control circuit 52 H provides a series switch control signal 66 and a shunt switch control signal 68 to the switching circuit 58 . As a result, the threshold detector and control circuit 132 H, of FIG. 3H , include a first boost level threshold 128 , a second boost level threshold 130 , the third comparator 144 or the fourth comparator 146 . Also, as discussed above, the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , depicted in FIG. 3H , may be provided by the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , or, in the case where an open loop assist circuit is included in the parallel amplifier circuit 14 C of FIG. 18C , the sum of the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , and the open loop assist circuit output current estimate, I ASSIST — SENSE .

One embodiment of the threshold detector and control circuit 132 H of FIG. 3H is further depicted in FIG. 4H . The threshold detector and control circuit 132 H may be functionally similar to the threshold detector and control circuit 132 D, depicted in FIG. 4D , except the circuitry associated with the multi-level charge pump circuit 56 is eliminated. For example, the threshold detector and control circuit 132 D does not include a first boost level threshold 128 , a second boost level threshold 130 , the third comparator 144 , or the fourth comparator 146 . As a result, the logic circuit 148 H is configured to operate as a buck converter based upon the magnitude of the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , relative to the shunt level threshold 124 and the series level threshold 126 . In addition, unlike the threshold detector and control circuit 132 D, depicted in FIG. 4D , the first state machine used to control the logic circuit 148 H may be simplified. As an example, FIG. 5H depicts an example embodiment of a first state machine of the logic circuit 148 H that includes a shunt output mode 188 H and a series output mode 190 H, and which is described with continuing reference to FIGS. 3H and 4H .

›DETAILED DESCRIPTION · 46 of 67

In the shunt output mode 188 H, the logic circuit 148 H, depicted in FIG. 4H , configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 , depicted in FIG. 3H , is in an open state (not conducting). The logic circuit 148 H also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 , depicted in FIG. 3H , is in a closed state (conducting). As a result, the switching voltage output 26 of FIG. 3H is configured to provide a switching voltage, V SW , substantially equal to ground. In response to assertion of the series level indication 152 A, which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is greater than or equal to the series level threshold 126 , the logic circuit 148 H configures the first state machine to transition to the series output mode 190 H. Otherwise the first state machine remains in the shunt output mode 188 H.

In the series output mode 190 H, the logic circuit 148 H configures the series switch control output 162 to drive the first output buffer 158 to generate a series switch control signal 66 such that the series switch 70 is in a closed state (conducting). The logic circuit 148 H also configures the shunt switch control output 164 to drive the second output buffer 160 such that the shunt switch 72 is in an open state (not conducting). As a result, the switching voltage output 26 , depicted in FIG. 3H , is configured to provide a switching voltage, V SW , substantially equal to the direct current (DC) voltage, V BAT . In response to de-assertion of the shunt level indication 150 D, depicted in FIG. 4H , which indicates that the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is less than the shunt level threshold 124 , the logic circuit 148 H configures the first state machine to transition to the shunt output mode 188 H, as depicted in FIG. 5H . Otherwise, the logic circuit 148 H configures the first state machine to remain in the series output mode 190 H.

While FIGS. 3H and 4H do not depict the presence of an FLL circuit being used in combination with the switcher control circuit 52 H, an embodiment of the FLL circuit may be provided for use in the buck converter in order to provide an FLL system clock 280 to either the switcher control circuit 52 H or the clock management system of the pseudo-envelope follower power management system.

In addition, like the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A , the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C , includes the V OFFSET loop circuit 41 A, the operation of which is described below with respect to the V OFFSET loop circuit 41 B, depicted in FIG. 18B .

Illustratively, unlike the operation of the V OFFSET loop circuit 41 B described above with respect FIG. 18B , where the filter having a first time constant, Tau 0 , and the second time constant, Tau 1 , may be modified to optimize the bandwidth of the V OFFSET loop circuit 41 B during pre-charging of the coupling circuit 18 , prior to initiation of a data burst to be sent by the linear RF power amplifier 22 , as depicted, for example, in FIGS. 1A-B and 2 A-B, the controller 50 , depicted in FIG. 18C , may selectively modify the K ERROR — GAIN value of the V OFFSET loop circuit 41 A to provide a pre-charge mode of operation for a pre-determined period of time. During the pre-charge mode of operation, the controller 50 may increase the value of the K ERROR — GAIN to effectively provide higher loop bandwidth. After a predetermined period of time, the controller 50 may decrease the K ERROR — GAIN value to provide a lower loop bandwidth to ensure stable operation of the V OFFSET loop circuit 41 A.

FIG. 18D depicts a pseudo-envelope follower power management system 10 F that is similar to the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B . Similar to the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , the pseudo-envelope follower power management system 10 F includes the parallel amplifier circuit 14 D having the V OFFSET loop circuit 41 B. The various embodiments of the parallel amplifier circuit 14 D, the associated parallel amplifier 35 , and the V OFFSET loop circuit 41 B are described in detail relative to the pseudo-envelope follower power management system 10 E of FIG. 18B , and are therefore not repeated here.

However, unlike the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , the pseudo-envelope follower power management system 10 F replaces the multi-level charge pump buck converter 12 C with the buck converter 13 A, depicted in FIG. 18C .

As discussed before, because the buck converter 13 A does not include the multi-level charge pump buck converter 12 C, the parallel amplifier power source selection circuit 272 is eliminated and the μC charge pump output of the μC charge pump circuit 262 is directly coupled to the parallel amplifier circuit 14 D in order to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , to the parallel amplifier 35 .

In addition, like some embodiments of the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , some embodiments of the parallel amplifier circuit 14 D of the pseudo-envelope follower power management system 10 F, depicted in FIG. 18D , may further include an open loop assist circuit 39 similar to the open loop assist circuit 39 depicted in FIGS. 2A-B , and/or the example embodiments of the open loop assist circuit 39 , the open loop assist circuit 39 A, depicted in FIG. 9A , and the open loop assist circuit 39 B, depicted in FIG. 9B . Accordingly, in those cases where an open loop assist circuit is included in the parallel amplifier circuit 14 D, as depicted in FIGS. 2A-B , the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is combined with the open loop assist circuit output current estimate, I ASSIST — SENSE , to form the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , that may be provided as a feedback signal to the switcher control circuit 259 of the buck converter 13 A.

›DETAILED DESCRIPTION · 47 of 67

Also, as discussed relative to the pseudo-envelope follower power management system 10 D of FIG. 18C , although the embodiment of the pseudo-envelope follower power management system 10 F, depicted in FIG. 18D , only depicts the switcher control circuit 259 receiving the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , this is by example and not by limitation. Some embodiments of the parallel amplifier circuit 14 D, of FIG. 18D , may further include an open loop assist circuit 39 similar to the open loop assist circuit 39 , depicted in FIGS. 2A-B , the example embodiment of the open loop assist circuit 39 A, depicted in FIG. 9A , and the example embodiment of the open loop assist circuit 39 B, depicted in FIG. 9B . Accordingly, in those cases where an open loop assist circuit is included in the parallel amplifier circuit 14 D, the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , is combined with the open loop assist circuit output current estimate, I ASSIST — SENSE , (depicted in FIGS. 2A-B ), to form the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , that may be provided as a feedback signal to the switcher control circuit 259 .

The operation of the buck converter 13 A and the switcher control circuit 259 are described relative to the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C . Accordingly, a detailed description of the operation of the buck converter 13 A is omitted from the description of the pseudo-envelope follower power management system 10 F, depicted in FIG. 18D .

The μC charge pump circuit 262 , depicted in FIGS. 18A-D , will now be discussed. FIG. 19A depicts an embodiment of the μC charge pump circuit 262 of FIGS. 18A-D as a μC charge pump circuit 262 A. The μC charge pump circuit 262 A may be configured to generate a μC charge pump output voltage, V μC — OUT , at the μC charge pump output based upon an operational mode of the μC charge pump circuit 262 A. The μC charge pump circuit 262 A may include four operational modes. The μC charge pump output voltage, V μC — OUT , generated at the μC charge pump output may be based on an operational ratio of the μC charge pump, μBB RATIO . As an example, the μC charge pump circuit 262 A may include four operational modes: OFF mode, 1×V BAT mode, 4/3×V BAT mode, and 3/2×V BAT mode, where each operational mode corresponds to a particular operational ratio of the μC charge pump, μBB RATIO . Table 1 shows, in tabulated form, the relationships between the operational modes of the μC charge pump circuit 262 A, the operational ratio of the μC charge pump, μBB RATIO , and the μC charge pump output voltage, V μC — OUT , substantially generated at the μC charge pump output.

When the μC charge pump circuit 262 A is configured to operate in the OFF mode, the μC charge pump circuit 262 A is disabled and the μC charge pump output floats. When the μC charge pump circuit 262 A is configured to operate in the 1×V BAT mode, the μC charge pump circuit 262 A is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to the supply input 24 , (V BAT ). When the μC charge pump circuit 262 A is configured to operate in the 4/3×V BAT mode, the μC charge pump circuit 262 A is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to the 4/3×V BAT . When the μC charge pump circuit 262 A is configured to operate in the 3/2×V BAT mode, the μC charge pump circuit 262 A is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to 3/2×V BAT .

The μC charge pump circuit 262 A may include a μC charge pump control circuit 316 A, a first flying capacitor 318 having a first terminal 318 A and a second terminal 318 B, a second flying capacitor 320 having a first terminal 320 A, a second terminal, 320 B and a plurality of switches including a first switch 322 , (SW 1 ), a second switch 324 , (SW 2 ), a third switch 326 , (SW 3 ), a fourth switch 328 , (SW 4 ), a fifth switch 330 , (SW 5 ), a sixth switch 332 , (SW 6 ), a seventh switch 334 , (SW 7 ), an eighth switch 336 , (SW 8 ), and a ninth switch 338 , (SW 9 ). Each of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ) may be a solid state based switch implemented with field effect transistors, insulator-on-semiconductor based transistors, or bipolar based transistors, or a combination thereof. Each of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8), and the ninth switch 338 , (SW 9 ) may be a solid state transmission gate. As another example, each of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ) may be based on a GaN process. Alternatively, each of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ) may be micro-electromechanical systems (MEMS) contact type switches.

The first switch 322 may be coupled between the first terminal 320 A of the second flying capacitor 320 and the supply input 24 , (V BAT ). The first switch 322 , (SW 1 ), may include a first switch control input configured to receive a first switch control signal 340 from the μC charge pump control circuit 316 A, where the first switch control signal 340 operably opens and closes the first switch 322 , (SW 1 ), based upon the operational mode of the μC charge pump circuit 262 A. The second switch 324 , (SW 2 ), may include a second switch control input configured to receive a second switch control signal 342 from the μC charge pump control circuit 316 A, where the second switch control signal 342 operably opens and closes the second switch 324 , (SW 2 ), based upon the operational mode of the μC charge pump circuit 262 A. The second switch 324 , (SW 2 ), may be coupled between the supply input 24 , (V BAT ), and the second terminal 320 B of the second flying capacitor 320 . The third switch 326 , (SW 3 ), may include a third switch control input configured to receive a third switch control signal 344 from the μC charge pump control circuit 316 A, where the third switch control signal 344 operably opens and closes the third switch 326 , (SW 3 ), based upon the operational mode of the μC charge pump circuit 262 A. The third switch 326 , (SW 3 ), may be coupled between the second terminal 320 B of the second flying capacitor 320 and ground. The fourth switch 328 , (SW 4 ), may include a fourth switch control input configured to receive a fourth switch control signal 346 from the μC charge pump control circuit 316 A, where the fourth switch control signal 346 operably opens and closes the fourth switch 328 , (SW 4 ), based upon the operational mode of the μC charge pump circuit 262 A. The fourth switch 328 , (SW 4 ), may be coupled between the first terminal 320 A of the second flying capacitor 320 and second terminal 318 B of the first flying capacitor 318 . The fifth switch 330 , (SW 5 ), may include a fifth switch control input configured to receive a fifth switch control signal 348 from the μC charge pump control circuit 316 A, where the fifth switch control signal 348 operably opens and closes the fifth switch 330 , (SW 5 ), based upon the operational mode of the μC charge pump circuit 262 A. The fifth switch 330 , (SW 5 ), may be coupled between the second terminal 318 B of the first flying capacitor 318 and second terminal 320 B of the second flying capacitor 320 . The sixth switch 332 , (SW 6 ), may include a sixth switch control input configured to receive a sixth switch control signal 350 from the μC charge pump control circuit 316 A, where the sixth switch control signal 350 operably opens and closes the sixth switch 332 , (SW 6 ), based upon the operational mode of the μC charge pump circuit 262 A. The sixth switch 332 , (SW 6 ), may be coupled between the first terminal 318 A of the first flying capacitor 318 and first terminal 320 A of the second flying capacitor 320 . The seventh switch 334 , (SW 7 ), may include a seventh switch control input configured to receive a seventh switch control signal 352 from the μC charge pump control circuit 316 A, where the seventh switch control signal 352 operably opens and closes the seventh switch 334 based upon the operational mode of the μC charge pump circuit 262 A. The seventh switch 334 , (SW 7 ), may be coupled between the second terminal 318 B of the first flying capacitor 318 and ground. The eighth switch 336 , (SW 8 ), may include an eighth switch control input configured to receive an eighth switch control signal 354 from the μC charge pump control circuit 316 A, where the eighth switch control signal 354 operably opens and closes the eighth switch 336 , (SW 8 ), based upon the operational mode of the μC charge pump circuit 262 A. The eighth switch 336 , (SW 8 ), may be coupled between the second terminal 318 B of the first flying capacitor 318 and the supply input 24 , (V BAT ). The ninth switch 338 , (SW 9 ), may include a ninth switch control input configured to receive a ninth switch control signal 356 from the μC charge pump control circuit 316 A, where the ninth switch control signal 356 operably opens and closes the ninth switch 338 , (SW 9 ), based upon the operational mode of the μC charge pump circuit 262 A. The ninth switch 338 , (SW 9 ), may be coupled between the first terminal 318 A of the first flying capacitor 318 and the supply input 24 , (V BAT ).

›DETAILED DESCRIPTION · 48 of 67

The μC charge pump control circuit 316 A may be configured to couple to a μC charge pump clock 276 and a μC charge pump control bus 278 . The μC charge pump control bus 278 may be used to configure the μC charge pump circuit 262 A to operate in one of the four operational modes by setting an operational ratio of the μC charge pump, μBB RATIO , of the μC charge pump circuit 262 A, where the parameter corresponding to a selection of the operational ratio of the μC charge pump, μBB RATIO , may be stored locally in the μC charge pump control circuit 316 A. In addition, the μC charge pump control circuit 316 A may use the μC charge pump clock 276 to operably switch between phases of operation of the μC charge pump circuit 262 A. The switch state (open or closed) of each of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ), may be changed depending upon the phase of operation of the μC charge pump circuit 262 A. The relationship between the operational ratio of the μC charge pump, μBB RATIO , the phase of operation of the μC charge pump circuit 262 A, and the switch state of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ), is shown in TABLE 2.

As used in TABLE 2, “PHASE 1” indicates the switch state (open or closed) of the identified switch is closed during a first phase of operation of the μC charge pump circuit 262 A. “PHASE 2” indicates that the switch state (open or closed) of the identified switch is closed during a second phase of operation of the μC charge pump circuit 262 A. “PHASE 3” indicates the switch state (open or closed) of the identified switch is closed during a third phase of operation of the μC charge pump circuit 262 A. “OPEN” indicates the switch state (open or closed) of the identified switch is open during all the phases of operation of the μC charge pump circuit 262 A.

As an example, the μC charge pump circuit 262 A may be configured to operate in the OFF mode by setting the operational ratio of the μC charge pump, μBB RATIO , to OFF. When the operational ratio of the μC charge pump, μBB RATIO , is set to OFF, the first switch 322 , (SW 1 ), is configured to be open, the second switch 324 , (SW 2 ), is configured to be open, the third switch 326 , (SW 3 ), is configured to be open, the fourth switch 328 , (SW 4 ), is configured to be open, the fifth switch 330 , (SW 5 ), is configured to be open, the sixth switch 332 , (SW 6 ), is configured to be open, the seventh switch 334 , (SW 7 ), is configured to be open, the eighth switch 336 , (SW 8 ), is configured to be open, and the ninth switch 338 , (SW 9 ), is configured to be open at all times. Accordingly, the μC charge pump output voltage, V μC — OUT , at the μC charge pump output floats with respect to ground when the μC charge pump circuit 262 A is configured to operate in the OFF mode.

The μC charge pump circuit 262 A may be configured to operate in the 4/3×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 4/3. When the operational ratio of the μC charge pump, μBB RATIO , is set to 4/3, the μC charge pump circuit 262 A may operate in a first phase, (PHASE 1), a second phase, (PHASE 2), and a third phase, (PHASE 3), dependent upon the μC charge pump clock 276 . FIG. 20A depicts an example of the “effective” operation of the μC charge pump circuit 262 A when the μC charge pump circuit 262 A is configured to operate in either the first phase, (PHASE 1), the second phase, (PHASE 2), or the third phase, (PHASE 3). As depicted in FIG. 20A , some embodiments of the μC charge pump circuit 262 A may include a μC charge pump output capacitor 357 , C μC — OUT , coupled to the μC charge pump output. In some phases of operation, the μC charge pump output capacitor 357 , C μC — OUT , may store charge transferred from supply input 24 , (V BAT ), to the μC charge pump output. In other phases of operation, the μC charge pump output capacitor 357 , C μC — OUT , may source previously transferred charge to the μC charge pump output.

As depicted in FIG. 20A , during the first phase of operation, (PHASE 1), of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 4/3×V BAT mode, the switches of the μC charge pump circuit 262 A are configured to couple the first terminal 318 A of the first flying capacitor 318 to the supply input 24 , (V BAT ), the second terminal 318 B of the first flying capacitor 318 to the second terminal 320 B of the second flying capacitor 320 , and the first terminal 320 A of the second flying capacitor 320 to the μC charge pump output. As a result, during the first phase of operation, (PHASE 1), of the μC charge pump circuit 262 A, the μC charge pump circuit 262 A delivers charge to the μC charge pump output capacitor 357 , C μC — OUT .

As further depicted in FIG. 20A , during the second phase of operation, (PHASE 2), of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 4/3×V BAT mode, the switches of the μC charge pump circuit 262 A are configured to couple the second terminal 320 B of the second flying capacitor 320 to the supply input 24 , (V BAT ), the first terminal 320 A of the second flying capacitor 320 to the first terminal 318 A of the first flying capacitor 318 and the μC charge pump output, and decouple the second terminal 318 B of the first flying capacitor 318 such that to the second terminal 318 B of the first flying capacitor 318 floats relative to ground. As a result, during the second phase of operation, (PHASE 2), of the μC charge pump circuit 262 A, the μC charge pump circuit 262 A delivers charge to the μC charge pump output capacitor 357 , C μC — OUT .

›DETAILED DESCRIPTION · 49 of 67

As further depicted in FIG. 20A , during the third phase of operation, (PHASE 3), of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 4/3×V BAT mode, the switches of the μC charge pump circuit 262 A are configured to couple the first terminal 320 A of the second flying capacitor 320 to the supply input 24 , (V BAT ), the second terminal 320 B of the second flying capacitor 320 to the first terminal 318 A of the first flying capacitor 318 , and the second terminal 318 B of the first flying capacitor 318 to ground. In addition, during the third phase of operation, (PHASE 3), of the μC charge pump circuit 262 A, the μC charge pump output is decoupled from the first flying capacitor 318 , the second flying capacitor, and the supply input 24 , (V BAT ), such that the charge previously stored in the μC charge pump output capacitor 357 , C μC — OUT , sources current to the μC charge pump output.

Accordingly, returning to TABLE 2, when the μC charge pump circuit 262 A is configured to operate in the 4/3×V BAT mode, the first switch 322 , (SW 1), is configured to be closed during the first phase of operation, (PHASE 1), the second switch 324 , (SW 2 ), is configured to be closed during the second phase of operation, (PHASE 2), the third switch 326 , (SW 3 ), is configured to be closed during the third phase of operation, (PHASE 3), the fourth switch 328 , (SW 4 ), is configured to be closed during the third phase of operation, (PHASE 3), the fifth switch 330 , (SW 5 ), is configured to be closed during the first phase of operation, (PHASE 1), and the sixth switch 332 , (SW 6 ), is configured to be closed during the second phase of operation, (PHASE 2) of the μC charge pump circuit 262 A. Otherwise, the μC charge pump control circuit 316 A configures the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ), to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 4/3×V BAT .

As another example of the operation of the μC charge pump circuit 262 A depicted in FIG. 19A , the μC charge pump circuit 262 A may be configured to operate in the 3/2×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 3/2. When the operational ratio of the μC charge pump, μBB RATIO , is set to 3/2, the μC charge pump circuit 262 A may operate in a first phase of operation, (PHASE 1) and a second phase of operation, (PHASE 2) dependent upon the μC charge pump clock 276 . FIG. 20B depicts the “effective” circuit topology of the μC charge pump circuit 262 A during the first phase of operation, (PHASE 1) and a second phase of operation, (PHASE 2).

Illustratively, as depicted in FIG. 20B , during the first phase of operation, (PHASE 1), of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 3/2×V BAT mode, the switches of the μC charge pump circuit 262 A are configured to couple the second terminal 318 B of the first flying capacitor 318 and the second terminal 320 B of the second flying capacitor 320 to the supply input 24 , (V BAT ), the first terminal 318 A of the first flying capacitor 318 and the first terminal 320 A of the second flying capacitor 320 to the μC charge pump output. As a result, during the first phase of operation, (PHASE 1), of the μC charge pump circuit 262 A, the μC charge pump circuit 262 A delivers charge to the μC charge pump output capacitor 357 , C μC — OUT , from the supply input 24 , (V BAT ), the first flying capacitor 318 and the second flying capacitor 320 .

As further depicted in FIG. 20B , during the second phase of operation, (PHASE 2), of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 3/2×V BAT mode, the switches of the μC charge pump circuit 262 A are configured to couple the first terminal 320 A of the second flying capacitor 320 to the supply input 24 , (V BAT ), the second terminal 320 B of the second flying capacitor 320 to the first terminal 318 A of the first flying capacitor 318 , and the second terminal 318 B of the first flying capacitor 318 to ground in order to charge the first flying capacitor 318 and the second flying capacitor 320 from the supply input 24 , (V BAT ).

Accordingly, during the second phase of operation, (PHASE 2), of the μC charge pump circuit 262 A, depicted in FIG. 20 B, the μC charge pump output is decoupled from the first flying capacitor 318 , the second flying capacitor, and the supply input 24 , (V BAT ), such that the charge previously stored in the μC charge pump output capacitor 357 , C μC — OUT , sources current to the μC charge pump output.

Accordingly, returning to TABLE 2, when the μC charge pump circuit 262 A is configured to operate in the 3/2×V BAT mode, the second switch 324 , (SW 2 ), is configured to be closed during the first phase of operation, (PHASE 1), the third switch 326 , (SW 3 ), is configured to be closed during the second phase of operation, (PHASE 3), the fourth switch 328 , (SW 4 ), is configured to be closed during the second phase of operation, (PHASE 2), the fifth switch 330 , (SW 5 ), is configured to be closed during the first phase of operation, (PHASE 1), and the eighth switch 336 , (SW 8 ), is configured to be closed during the first phase of operation, (PHASE 1) of the μC charge pump circuit 262 A. Otherwise, the μC charge pump control circuit 316 B configures the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6 ), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ), to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 3/2×V BAT .

›DETAILED DESCRIPTION · 50 of 67

The μC charge pump circuit 262 A may also be configured to operate in the 1×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 1. When the operational ratio of the μC charge pump, μBB RATIO , is set to 1, the μC charge pump circuit 262 A has one phase of operation, PHASE 1. FIG. 20C depicts the “effective” circuit topology of the μC charge pump circuit 262 A during the first phase of operation, (PHASE 1) when the μC charge pump circuit 262 A is configured to operate in the 1×V BAT mode.

As depicted in FIG. 20C , during the first phase of operation, (PHASE 1), of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 1×V BAT mode, the switches of the μC charge pump circuit 262 A are configured to couple the first terminal 320 A of the second flying capacitor 320 to the supply input 24 , (V BAT ), the second terminal 320 B of the second flying capacitor 320 to the first terminal 318 A of the first flying capacitor 318 , and the second terminal 318 B of the first flying capacitor 318 to ground in order to charge the first flying capacitor 318 and the second flying capacitor 320 from the supply input 24 , (V BAT ). In addition, the supply input 24 , (V BAT ), is coupled to the μC charge pump output such that charge is delivered directly from the supply input 24 , (V BAT ), to the μC charge pump output capacitor 357 , C μC — OUT .

As a result, shown in TABLE 2, the switch state of the first switch 322 , (SW 1 ), the second switch 324 , (SW 2 ), the third switch 326 , (SW 3 ), the fourth switch 328 , (SW 4 ), the fifth switch 330 , (SW 5 ), the sixth switch 332 , (SW 6), the seventh switch 334 , (SW 7 ), the eighth switch 336 , (SW 8 ), and the ninth switch 338 , (SW 9 ), do not change over time. Accordingly, when the μC charge pump circuit 262 A is configured to operate in the 1×V BAT mode, the first switch 322 , (SW 1 ), is configured to be open, the second switch 324 , (SW 2 ), is configured to be open, the third switch 326 , (SW 3 ), is configured to be open, the fourth switch 328 , (SW 4 ), is configured to be open, the fifth switch 330 , (SW 5 ), is configured to be open, the sixth switch 332 , (SW 6 ), is configured to be open, the seventh switch 334 , (SW 7 ), is configured to be open, the eighth switch 336 , (SW 8 ), is configured to be open, and the ninth switch 338 , (SW 9 ), is configured to be closed at all times. As a result, the μC charge pump output generates a μC charge pump output voltage, V μC — OUT , substantially equal to 1×V BAT because closing the ninth switch 338 , (SW 9 ), couples the supply input 24 , (V BAT ), to the μC charge pump output.

FIG. 19B depicts another example embodiment of the μC charge pump circuit 262 of FIGS. 18A-D as a μC charge pump circuit 262 B. Similar to the μC charge pump circuit 262 A of FIG. 19A , the μC charge pump circuit 262 B may be configured to generate a μC charge pump output voltage, V μC — OUT , at the μC charge pump output based upon an operational mode of the μC charge pump circuit 262 B. However, unlike the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to either “boost” or “buck” the supply input 24 , (V BAT ), to generate the μC charge pump output voltage, V μC — OUT , at the μC charge pump output. As an example, the operational modes of the μC charge pump circuit 262 B may include an OFF mode, a 1/4×V BAT mode, 1/3×V BAT mode, a 1/2×V BAT mode, a 2/3×V BAT mode, 1×V BAT mode, a 4/3×V BAT mode, and a 3/2×V BAT mode, where each of the operational modes of the μC charge pump circuit 262 B corresponds to a particular operational ratio of the μC charge pump, μBB RATIO . Table 3 shows, in tabulated form, the relationships between the operational modes of the μC charge pump circuit 262 B, the operational ratio of the μC charge pump, μBB RATIO , and the μC charge pump output voltage, V μC — OUT , substantially generated at the μC charge pump output.

The operational modes of the μC charge pump circuit 262 B are now described. As an example, when the μC charge pump circuit 262 B is configured to operate in the OFF mode, the μC charge pump circuit 262 B is disabled and the μC charge pump output floats. When the μC charge pump circuit 262 B is configured to operate in the 1/4×V BAT mode, the μC charge pump circuit 262 B is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to 1/4×the supply input 24 , (V BAT ). When the μC charge pump circuit 262 B is configured to operate in the 1/3×V BAT mode, the μC charge pump circuit 262 B is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to 1/3×V BAT . When the μC charge pump circuit 262 B is configured to operate in the 1/2×V BAT mode, the μC charge pump circuit 262 B is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to 1/2×V BAT . When the μC charge pump circuit 262 B is configured to operate in the 2/3×V BAT mode, the μC charge pump circuit 262 B is configured to generate the μC charge pump output voltage, V μC — OUT , substantially equal to 2/3×V BAT . When the μC charge pump circuit 262 B is configured to operate in the 1×V BAT mode, the μC charge pump circuit 262 B is configured to generate the μC charge pump output voltage, V μC — OUT , substantially equal to 1×V BAT . When the μC charge pump circuit 262 B is configured to operate in the 4/3×V BAT mode, the μC charge pump circuit 262 B is configured to generate the μC charge pump output voltage, V μC — OUT , substantially equal to 4/3×V BAT . And, when the μC charge pump circuit 262 B is configured to operate in the 3/2×V BAT mode, the μC charge pump circuit 262 B is configured to generate a μC charge pump output voltage, V μC — OUT , substantially equal to 3/2×V BAT .

The μC charge pump circuit 262 B may include a μC charge pump control circuit 316 B, a first flying capacitor 358 having a first terminal 358 A and a second terminal 358 B, a second flying capacitor 360 having a first terminal 360 A and a second terminal 360 B, a first switch 362 , (SW 1 ), a second switch 364 , (SW 2 ), a third switch 366 , (SW 3 ), a fourth switch 368 , (SW 4 ), a fifth switch 370 , (SW 5 ), a sixth switch 372 , (SW 6 ), a seventh switch 374 , (SW 7 ), an eighth switch 376 , (SW 8 ), a ninth switch 378 , (SW 9 ), a tenth switch 380 , (SW 10 ), an eleventh switch 382 , (SW 11 ), a twelfth switch 384 , (SW 12 ), and a thirteenth switch 386 , (SW 13 ). Each of the plurality of switches of the μC charge pump circuit 262 B may be a solid state based switch implemented with field effect transistors, insulator-on-semiconductor based transistors, or bipolar based transistors, or a combination thereof. Each of the plurality of switches of the μC charge pump circuit 262 B may be a solid state transmission gate. As another example, each of the plurality of switches of the μC charge pump circuit 262 B may be based on a GaN process. Alternatively, each of the plurality of switches of the μC charge pump circuit 262 B may be micro-electromechanical systems (MEMS) contact type switches.

›DETAILED DESCRIPTION · 51 of 67

As depicted in FIG. 19B , the first switch 362 , (SW 1 ), may be coupled between the first terminal 358 A of the first flying capacitor 358 and the supply input 24 , (V BAT ). The first switch 362 , (SW 1 ), may include a first switch control input configured to receive a first switch control signal 388 from the μC charge pump control circuit 316 B, where the first switch control signal 388 operably opens and closes the first switch 362 , (SW 1 ), based upon the operational mode of the μC charge pump circuit 262 B. The second switch 364 , (SW 2 ), may include a second switch control input configured to receive a second switch control signal 390 from the μC charge pump control circuit 316 B, where the second switch control signal 390 operably opens and closes the second switch 364 , (SW 2 ), based upon the operational mode of the μC charge pump circuit 262 B. The second switch 364 , (SW 2 ), may be coupled between the first terminal 358 A of the first flying capacitor 358 and the μC charge pump output. The third switch 366 , (SW 3 ), may include a third switch control input configured to receive a third switch control signal 392 from the μC charge pump control circuit 316 B, where the third switch control signal 392 operably opens and closes the third switch 366 , (SW 3 ), based upon the operational mode of the μC charge pump circuit 262 B. The third switch 366 , (SW 3 ), may be coupled between the second terminal 358 B of the first flying capacitor 358 and ground. The fourth switch 368 , (SW 4 ), may include a fourth switch control input configured to receive a fourth switch control signal 394 from the μC charge pump control circuit 316 B, where the fourth switch control signal 394 operably opens and closes the fourth switch 368 , (SW 4 ), based upon the operational mode of the μC charge pump circuit 262 B. The fourth switch 368 , (SW 4 ), may be coupled between the second terminal 358 B of the first flying capacitor 358 and the μC charge pump output. The fifth switch 370 , (SW 5 ), may include a fifth switch control input configured to receive a fifth switch control signal 396 from the μC charge pump control circuit 316 B, where the fifth switch control signal 396 operably opens and closes the fifth switch 370 , (SW 5 ), based upon the operational mode of the μC charge pump circuit 262 B. The fifth switch 370 , (SW 5 ), may be coupled between the second terminal 358 B of the first flying capacitor 358 and first terminal 360 A of the second flying capacitor 360 . The sixth switch 372 , (SW 6 ), may include a sixth switch control input configured to receive a sixth switch control signal 398 from the μC charge pump control circuit 316 B, where the sixth switch control signal 398 operably opens and closes the sixth switch 372 , (SW 6 ), based upon the operational mode of the μC charge pump circuit 262 B. The sixth switch 372 , (SW 6 ), may be coupled between the first terminal 360 A of the second flying capacitor 360 and the supply input 24 , (V BAT ). The seventh switch 374 , (SW 7 ), may include a seventh switch control input configured to receive a seventh switch control signal 400 from the μC charge pump control circuit 316 B, where the seventh switch control signal 400 operably opens and closes the seventh switch 374 , (SW 7 ), based upon the operational mode of the μC charge pump circuit 262 B. The seventh switch 374 , (SW 7 ), may be coupled between the first terminal 360 A of the second flying capacitor 360 and the μC charge pump output. The eighth switch 376 , (SW 8 ), may include an eighth switch control input configured to receive an eighth switch control signal 402 from the μC charge pump control circuit 316 B, where the eighth switch control signal 402 operably opens and closes the eighth switch 376 , (SW 8 ), based upon the operational mode of the μC charge pump circuit 262 B. The eighth switch 376 , (SW 8 ), may be coupled between the second terminal 360 B of the second flying capacitor 360 and ground. The ninth switch 378 , (SW 9 ), may include a ninth switch control input configured to receive a ninth switch control signal 404 from the μC charge pump control circuit 316 B, where the ninth switch control signal 404 operably opens and closes the ninth switch 378 , (SW 9 ), based upon the operational mode of the μC charge pump circuit 262 B. The ninth switch 378 , (SW 9 ), may be coupled between the second terminal 360 B of the second flying capacitor 360 and the μC charge pump output. The tenth switch 380 , (SW 10 ), may include a tenth switch control input configured to receive a tenth switch control signal 406 from the μC charge pump control circuit 316 B, where the tenth switch control signal 406 operably opens and closes the tenth switch 380 , (SW 10 ), based upon the operational mode of the μC charge pump circuit 262 B. The tenth switch 380 , (SW 10 ), may be coupled between the first terminal 358 A of the first flying capacitor 358 and the first terminal 360 A of the second flying capacitor 360 . The eleventh switch 382 , (SW 11 ), may include an eleventh switch control input configured to receive an eleventh switch control signal 408 from the μC charge pump control circuit 316 B, where the eleventh switch control signal 408 operably opens and closes the eleventh switch 382 , (SW 11 ), based upon the operational mode of the μC charge pump circuit 262 B. The eleventh switch 382 , (SW 11 ), may be coupled between the second terminal 358 B of the first flying capacitor 358 and the supply input 24 , (V BAT ). The twelfth switch 384 , (SW 12 ), may include a twelfth switch control input configured to receive a twelfth switch control signal 410 from the μC charge pump control circuit 316 B, where the twelfth switch control signal 410 operably opens and closes the twelfth switch 384 , (SW 12 ), based upon the operational mode of the μC charge pump circuit 262 B. The twelfth switch 384 , (SW 12 ), may be coupled between the second terminal 360 B of the second flying capacitor 360 and the supply input 24 , (V BAT ). The thirteenth switch 386 , (SW 13 ), may include a thirteenth switch control input configured to receive a thirteenth switch control signal 412 from the μC charge pump control circuit 316 B, where the thirteenth switch control signal 412 operably opens and closes the thirteenth switch 386 , (SW 13 ), based upon the operational mode of the μC charge pump circuit 262 B. The thirteenth switch 386 , (SW 13 ), may be coupled between the second terminal 358 B of the first flying capacitor 358 and the second terminal 360 B of the second flying capacitor 360 . Although not depicted in FIG. 19B , some embodiments of the μC charge pump circuit 262 B may further include a μC charge pump output capacitor 357 , C μC — OUT , coupled to the μC charge pump output in order to either store charge transferred from the supply input 24 , (V BAT ), to the μC charge pump output or may source previously transferred charge to the μC charge pump output, as previously described relative to the operation of the μC charge pump circuit 262 A.

›DETAILED DESCRIPTION · 52 of 67

Similar to the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in a respective operational mode based upon selection of an operational ratio of the μC charge pump, μBB RATIO , that corresponds to the respective operational mode. Also, similar to TABLE 2, TABLE 4 provides the relationship between the operational ratio of the μC charge pump, μBB RATIO , the phase of operation, and the switch state (open or closed) of the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ).

Similar to TABLE 2, in TABLE 4, “PHASE 1” indicates the switch state (open or closed) of the identified switch is closed during a first phase of operation of the μC charge pump circuit 262 B. “PHASE 2” indicates the switch state (open or closed) of the identified switch is closed during a second phase of operation of the μC charge pump circuit 262 B. “PHASE 3” indicates the switch state (open or closed) of the identified switch is closed during a third phase of operation of the μC charge pump circuit 262 B. “OPEN” indicates the switch state (open or closed) of the identified switch is open during all the phases of operation of the μC charge pump circuit 262 B.

Similar to the μC charge pump control circuit 316 A, the controller 50 , depicted in FIGS. 18A-D , may configure the μC charge pump control circuit 316 B via the μC charge pump control bus 278 to operate in one of the operational modes, as shown in TABLE 3, by setting an operational ratio of the μC charge pump, μBB RATIO , of the μC charge pump circuit 262 B. Also similar to the μC charge pump control circuit 316 A, the μC charge pump control circuit 316 B may store one or more parameters corresponding to a selection of the operational ratio of the μC charge pump, μBB RATIO , locally in the μC charge pump control circuit 316 B.

As an example, similar to the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in the OFF mode by setting the operational ratio of the μC charge pump, μBB RATIO , to OFF. When the operational ratio of the μC charge pump, μBB RATIO , is set to OFF, the first switch 362 , (SW 1 ), is configured to be open, the second switch 364 , (SW 2 ), is configured to be open, the third switch 366 , (SW 3 ), is configured to be open, the fourth switch 368 , (SW 4 ), is configured to be open, the fifth switch 370 , (SW 5 ), is configured to be open, the sixth switch 372 , (SW 6 ), is configured to be open, the seventh switch 374 , (SW 7 ), is configured to be open, the eighth switch 376 , (SW 8 ), is configured to be open, the ninth switch 378 , (SW 9 ), is configured to be open, the tenth switch 380 , (SW 10 ), is configured to be open, the eleventh switch 382 , (SW 11 ), is configured to be open, the twelfth switch 384 , (SW 12 ), is configured to be open, and the thirteenth switch 386 , (SW 13 ), is configured to be open at all times. Accordingly, the μC charge pump output voltage, V μC — OUT , at the μC charge pump output floats with respect to ground when the μC charge pump circuit 262 A is configured to operate in the OFF mode.

Also similar to the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in the 3/2×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 3/2. As indicated in Table 4, similar to the operation of the μC charge pump circuit 262 A, when the operational ratio of the μC charge pump, μBB RATIO , is set to 3/2, the μC charge pump circuit 262 B may operate in a first phase of operation, (PHASE 1) and a second phase of operation, (PHASE 2) dependent upon the μC charge pump clock 276 .

Accordingly, as indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 3/2×V BAT mode, the first switch 362 , (SW 1 ), the fifth switch 370 , (SW 5 ), and the eighth switch 376 , (SW 8 ), are configured to be closed when the μC charge pump circuit 262 B operates in a first phase of operation, (PHASE 1). In addition, the second switch 364 , (SW 2 ), the seventh switch 374 , (SW 7 ), the eleventh switch 382 , (SW 11 ) and the twelfth switch 384 , (SW 12 ), are configured to be closed when the μC charge pump circuit 262 B operates in a second phase of operation, (PHASE 2). Otherwise, the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), are configured to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 3/2×V BAT when the μC charge pump circuit 262 B is configured to operate in the 3/2×V BAT mode.

Also similar to the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in the 4/3×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 4/3. As indicated in TABLE 4, similar to the operation of the μC charge pump circuit 262 A, when the operational ratio of the μC charge pump, μBB RATIO , is set to 4/3, the μC charge pump circuit 262 B may operate in a first phase of operation, (PHASE 1), a second phase of operation, (PHASE 2), and third phase of operation, (PHASE 3), dependent upon the μC charge pump clock 276 .

Accordingly, as indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 4/3×V BAT mode, the first switch 362 , (SW 1 ), the fifth switch 370 (SW 5 ), and the eighth switch 376 , (SW 8 ), are configured to be closed when the μC charge pump circuit 262 B operates in a first phase of operation, (PHASE 1). In addition, the second switch 364 (SW 2 ), the sixth switch 372 , (SW 6 ), and the thirteenth switch 386 , (SW 13 ), are configured to be closed when the μC charge pump circuit 262 B operates in a second phase of operation, (PHASE 2). Likewise, the seventh switch 374 , (SW 7 ), and the twelfth switch 384 , (SW 12 ), are configured to be closed when the μC charge pump circuit 262 B operates in a third phase of operation, (PHASE 3). Otherwise, the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), are configured to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 4/3×V BAT when the μC charge pump circuit 262 B is configured to operate in the 4/3×V BAT mode.

›DETAILED DESCRIPTION · 53 of 67

Also similar the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in the 1×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 1. As indicated in TABLE 4, similar to the operation of the μC charge pump circuit 262 A, when the operational ratio of the μC charge pump, μBB RATIO , is set to 1, the μC charge pump circuit 262 B only operates in a first phase of operation, (PHASE 1) because the switches are statically switched into a configuration that provides a minimum impedance between the supply input 24 , (V BAT ), and the μC charge pump output. In other words, when the μC charge pump circuit 262 B is configured to operate in the 1×V BAT mode, the switch states of the indicated switches remain in either an open state or a closed state and do not change over time. The minimum impedance is provided by selectively turning on various switches to form parallel paths between the supply input 24 , (V BAT ), and the μC charge pump output. Advantageously, the parallel paths lower the drop in voltage seen across the switches of the μC charge pump circuit 262 B and reduce power consumption from the battery 20 . However, for the sake of consistency with the other operational modes of the μC charge pump circuit 262 B, the operation of the μC charge pump circuit 262 B, when configured to operate in the 1×V BAT mode, is described as operating only in a first phase of operation (PHASE 1).

Accordingly, as indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 1×V BAT mode, the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the fourth switch 368 , (SW 4 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the ninth switch 378 , (SW 9 ), the eleventh switch 382 , (SW 11 ), and the twelfth switch 384 , (SW 12 ), are configured to be closed. In addition, the third switch 366 , (SW 3 ), the fifth switch 370 , (SW 5 ), the eighth switch 376 , (SW 8 ), the tenth switch 380 , (SW 10 ), and the thirteenth switch 386 , (SW 13 ), are configured to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 1×V BAT when the μC charge pump circuit 262 B is configured to operate in the 1×V BAT mode.

Also similar the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in the OFF mode by setting the operational ratio of the μC charge pump, μBB RATIO , to OFF. When the μC charge pump circuit 262 B is configured to operate in the OFF mode, the μC charge pump circuit 262 B is disabled and the μC charge pump output floats. As indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the OFF mode, the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), are configured to be open by the μC charge pump control circuit 316 B. Accordingly, the μC charge pump output voltage, V μC — OUT , at the μC charge pump output floats with respect to ground when the μC charge pump circuit 262 B is configured to operate in the OFF mode.

Unlike the μC charge pump circuit 262 A, the μC charge pump circuit 262 B may be configured to operate in a 1/4×V BAT mode, 1/3×V BAT mode, a 1/2×V BAT mode, and a 2/3×V BAT mode,

The μC charge pump circuit 262 B may be configured to operate in the 2/3×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 2/3. As indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 2/3×V BAT mode, the first switch 362 , (SW 1 ), the fourth switch 368 , (SW 4 ), the sixth switch 372 , (SW 6 ), and the ninth switch 378 , (SW 9 ), are configured by the μC charge pump control circuit 316 B to be closed when the μC charge pump circuit 262 B operates in a first phase of operation, (PHASE 1). In addition, the μC charge pump control circuit 316 B configures the second switch 364 , (SW 2 ), the fifth switch 370 , (SW 5 ), and the eighth switch 376 , (SW 8 ), to be closed when the μC charge pump circuit 262 B operates in a second phase of operation, (PHASE 2). Otherwise, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 2/3×V BAT when the μC charge pump circuit 262 B is configured to operate in the 2/3×V BAT mode.

The μC charge pump circuit 262 B may be configured to operate in the 1/2×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 1/2. As indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 1/2×V BAT mode, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the fourth switch 368 , (SW 4 ), the sixth switch 372 , (SW 6 ), and the ninth switch 378 , (SW 9 ), to be closed when the μC charge pump circuit 262 B operates in a first phase of operation, (PHASE 1). In addition, the μC charge pump control circuit 316 B configures the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the seventh switch 374 , (SW 7 ), and the eighth switch 376 , (SW 8 ), to be closed when the μC charge pump circuit 262 B operates in a second phase of operation, (PHASE 2). Otherwise, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 1/2×V BAT when the μC charge pump circuit 262 B is configured to operate in the 1/2×V BAT mode.

›DETAILED DESCRIPTION · 54 of 67

The μC charge pump circuit 262 B may be configured to operate in the 1/3×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 1/3. As indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 1/3×V BAT mode, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the fifth switch 370 , (SW 5 ), and the ninth switch 378 , (SW 9 ), to be closed when the μC charge pump circuit 262 B operates in a first phase of operation, (PHASE 1). In addition, the μC charge pump control circuit 316 B configures the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the seventh switch 374 , (SW 7 ), and the eighth switch 376 , (SW 8 ), to be closed when the μC charge pump circuit 262 B operates in a second phase of operation, (PHASE 2). Otherwise, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 1/3×V BAT when the μC charge pump circuit 262 B is configured to operate in the 1/3×V BAT mode.

The μC charge pump circuit 262 B may be configured to operate in the 1/4×V BAT mode by setting the operational ratio of the μC charge pump, μBB RATIO , to 1/4. Similar to the operation of the μC charge pump circuit 262 A, when the μC charge pump circuit 262 A is configured to operate in the 1/4×V BAT mode, the μC charge pump circuit 262 B may include a first phase of operation, (PHASE 1), a second phase of operation, (PHASE 2), and a third phase of operation, (PHASE 3). As indicated by TABLE 4, when the μC charge pump circuit 262 B is configured to operate in the 1/4×V BAT mode, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the fifth switch 370 , (SW 5 ), and the ninth switch 378 , (SW 9 ), to be closed when the μC charge pump circuit 262 B operates in a first phase of operation, (PHASE 1). The μC charge pump control circuit 316 B configures the seventh switch 374 , (SW 7 ), and the eighth switch 376 , (SW 8 ), to be closed when the μC charge pump circuit 262 B operates in a second phase of operation, (PHASE 2). The μC charge pump control circuit 316 B configures the third switch 366 , (SW 3 ), and the ninth switch 378 , (SW 9 ), to be closed when the μC charge pump circuit 262 B operates in a third phase of operation, (PHASE 3). Otherwise, the μC charge pump control circuit 316 B configures the first switch 362 , (SW 1 ), the second switch 364 , (SW 2 ), the third switch 366 , (SW 3 ), the fourth switch 368 , (SW 4 ), the fifth switch 370 , (SW 5 ), the sixth switch 372 , (SW 6 ), the seventh switch 374 , (SW 7 ), the eighth switch 376 , (SW 8 ), the ninth switch 378 , (SW 9 ), the tenth switch 380 , (SW 10 ), the eleventh switch 382 , (SW 11 ), the twelfth switch 384 , (SW 12 ), and the thirteenth switch 386 , (SW 13 ), to be open. As a result, the μC charge pump output provides a μC charge pump output voltage, V μC — OUT , substantially equal to 1/4×V BAT when the μC charge pump circuit 262 B is configured to operate in the 1/4×V BAT mode.

FIG. 21 depicts a method 1000 to permit the controller 50 , depicted in FIGS. 18A-D , to selectively configure the μC charge pump prior to transmission of a data burst by a linear RF power amplifier. Accordingly, the description of method 1000 will be done with continuing reference to FIGS. 18A-D .

Prior to transmission of the data burst, the pseudo-envelope follower power management systems 10 C-F may configure the μC charge pump circuit 262 and the V OFFSET loop circuit 41 A-B in order to provide a power amplifier supply voltage, V CC , that is sufficient to power the linear RF power amplifier during the transmission of the data burst. Accordingly, prior to initiation of a transmission of data by the linear RF power amplifier, the controller 50 may determine the expected envelope characteristics of the signal to be transmitted. An example transmission of data may occur in a burst transmission time-slot. To determine the expected envelope characteristics of the signal to be transmitted, the controller 50 may consider the impact of data rate, the bandwidth of the channel and/or the type of modulation. Example types of modulation may include, but are not limited to quadrature phase shift keys (QPSK), or quadrature amplitude modulation (QAM). Alternatively, or in addition, the controller 50 may determine and consider the peak-to-average ratio characteristic of the waveform to be generated by the power amplifier.

Based upon an expected envelope characteristic of a signal to be transmitted by a power amplifier and a battery voltage, V BAT , the controller 50 may be configured to determine a minimum operational ratio of a μC charge pump, uBB RATIO — MIN . (Step 1002 ). In order to determine the minimum operational ratio of a μC charge pump, uBB RATIO — MIN , the controller uses the expected envelope characteristics of the signal to be transmitted to determine the expected peak to peak swing of the power amplifier supply voltage, V CC — PKPK , and obtains the voltage level of the battery, as present on the supply input 24 , (V BAT ). The expected peak to peak swing of the power amplifier supply voltage, V CC — PKPK , represents the dynamic range of voltages that the controller 50 expects to be generated on the power amplifier supply voltage, V CC , during the transmission of data. Effectively, the expected peak to peak swing of the power amplifier supply voltage, V CC — PKPK , equals the difference between maximum expected power amplifier supply voltage, V CC — MAX and the minimum expected power amplifier supply voltage, V CC — MIN , that the controller 50 expects to be generated on the power amplifier supply voltage, V CC , during the data transmission.

›DETAILED DESCRIPTION · 55 of 67

In addition to the expected peak to peak swing of the power amplifier supply voltage, V CC — PKPK , the controller may also take into consideration the minimum headroom voltage, V HEADROOM , of the switching elements of the parallel amplifier 35 . As an example, referring to FIGS. 12E-F , the controller 50 may consider the minimum headroom voltage, V HEADROOM , for the first switching element, SW 1A , 214 , and a second switching element, SW 1B , 216 . In addition, in some embodiments, the controller 50 may consider the minimum headroom for each of the switching devices (SW 1A , 214 and SW 1B , 216 ) individually. As an example, for the case where the first switching element, SW 1A , 214 is a PFET device, the controller 50 may use the minimum PFET headroom voltage, V HEADROOM — P , to determine the operational ratio of a μC charge pump, uBB RATIO . In the case where the second switching element, SW 1B , 216 is an NFET device, the controller 50 may use the minimum NFET headroom voltage, V HEADROOM — N to determine the operational ratio of a μC charge pump, uBB RATIO .

Accordingly, in the general case, the controller 50 may determine the minimum operational ratio of a μC charge pump, uBB RATIO — MIN , as shown in equation (1) as follows:

uBB RATIO — MIN =[V CC — PKPK +V HEADROOM — N +V HEADROOM — P )/ V BAT (1)

Based on the minimum operational ratio of the μC charge pump, uBB RATIO — MIN , the controller 50 may be configured to select an operational ratio of the μC charge pump, uBB RATIO , that is greater than the minimum operational ratio of the μC charge pump, uBB RATIO — MIN . (Step 1004 ). As indicated by TABLES 1 and 3, the available values of operational ratios of the μC charge pump, uBB RATIO , depend upon the embodiment of the μC charge pump circuit 262 . As an example, the embodiment of the μC charge pump circuit 262 A, depicted in FIG. 19A , provides several modes of operation where each mode of operation is associated with an operational ratio of the μC charge pump, uBB RATIO , as shown in TABLE 1. Likewise, the example embodiment of the μC charge pump circuit 262 B, depicted in FIG. 19B , provides a number of modes of operation where each mode of operation is associated with an operational ratio of the μC charge pump, uBB RATIO , as shown in TABLE 3. Depending upon the calculated value of the minimum operational ratio of a μC charge pump, uBB RATIO — MIN , the controller 50 initially selects the smallest available operational ratio of the μC charge pump, uBB RATIO , of the μC charge pump circuit 262 that is greater than the minimum operational ratio of a μC charge pump, uBB RATIO — MIN . As an example, in the case where the μC charge pump circuit 262 is similar to the μC charge pump circuit 262 B of FIG. 19B (TABLE 3), if the minimum operational ratio of a μC charge pump, uBB RATIO — MIN , is greater than 1/4 but less than 1/3, the controller initially selects the operational ratio of the μC charge pump, uBB RATIO , to be 1/3.

Thereafter, the controller 50 may be configured to calculate an expected value for an offset voltage, V OFFSET , to be generated across a coupling device, V OFFSET — EXPECTED , based upon the operational ratio of the μC charge pump, uBB RATIO , of the μC charge pump, selected by the controller 50 (Step 1006 ). The expected value for an offset voltage, V OFFSET — EXPECTED , may be calculated as shown in equation (2) as follows:

V OFFSET — EXPECTED =V CC — PKPK −V BAT ×uBB RATIO +V HEADROOM — P (2)

Thereafter, the controller 50 may be configured to determine whether the expected value for the offset voltage, V OFFSET — EXPECTED , to be generated across the coupling device is greater than zero, V OFFSET — EXPECTED , >0. (Step 1008 ). In some alternative embodiments of method 1000 , the controller 50 may determine whether the expected value for the offset voltage, V OFFSET — EXPECTED , to be generated across the coupling device is greater than a minimum offset voltage, V OFFSET — MIN , where the minimum offset voltage, V OFFSET — MIN , is a configurable parameter. In this example embodiment of method 1000 , it will be understood that the minimum offset voltage, V OFFSET — MIN , is zero.

If the expected value for the offset voltage, V OFFSET , to be generated across the coupling device is less than zero, V OFFSET — EXPECTED , <0, the controller 50 increments the value of the operational ratio of the μC charge pump, uBB RATIO , to the next highest value of the operational ratio of the μC charge pump, uBB RATIO , available for the μC charge pump circuit 262 . (Step 1010 ). For example, in the case where the μC charge pump circuit 262 is similar to the μC charge pump circuit 262 B of FIG. 19B , if the initially determined value of the operational ratio of the μC charge pump, uBB RATIO , of the μC charge pump circuit 262 B is 1/3, the controller 50 will increment the value of the operational ratio of the μC charge pump, uBB RATIO , to 1/2. Thereafter, method 1000 returns to Step 1008 to recalculate the expected value for an offset voltage, V OFFSET — EXPECTED , using the new value of the operational ratio of the μC charge pump, uBB RATIO . This process continues until the controller 50 identifies the minimum value of the operational ratio of the μC charge pump, uBB RATIO , of the μC charge pump circuit 262 for which V OFFSET — EXPECTED >0.

After identifying the minimum value of the operational ratio of the μC charge pump, uBB RATIO , of the μC charge pump circuit 262 for which V OFFSET — EXPECTED >0, the controller selects the operational ratio of the μC charge pump, uBB RATIO , as a selected operational ratio of a μC charge pump, uBB RATIO — SEL , to be used during the transmission of data by the linear RF power amplifier. (Step 1012 ). Via the μC charge pump control bus 278 , the controller 50 configures the μC charge pump circuit 262 to generate a μC charge pump output voltage, V μC — OUT , on the μC charge pump output based upon the selected operational ratio of a μC charge pump, uBB RATIO — SEL . (Step 1014 ).

›DETAILED DESCRIPTION · 56 of 67

Thereafter, in some embodiments of method 1000 , the controller 50 configures the V OFFSET loop circuit 41 A-B to generate an offset voltage, V OFFSET , substantially equal to an expected value for the target offset voltage, V OFFSET — EXPECTED , when the μC charge pump circuit 262 uses the selected operational ratio of a μC charge pump, uBB RATIO — SEL . (Step 1016 ). Accordingly, the controller 50 may be configured to calculate the value of an expected target offset voltage, V OFFSET — TARGET — EXPECTED , when the μC charge pump circuit 262 is configured to operate using the selected operational ratio of a μC charge pump, uBB RATIO — SEL . The value of the target offset voltage, V OFFSET — TARGET — EXPECTED , may be calculated as shown in equation (3) as follows:

V OFFSET — TARGET — EXPECTED =V CC — PKPK −V BAT ×uBB RATIO — SEL +V HEADROOM — P (3)

Thereafter, the controller 50 may be configured to use the value of the expected target offset voltage, V OFFSET — TARGET — EXPECTED , to determine the parameter value of V OFFSET — TARGET to be provided to the V OFFSET loop circuit 41 A-B. Via the μC charge pump control bus 278 , the controller 50 provides the V OFFSET — TARGET parameter to the V OFFSET loop circuit 41 A-B.

A method 1100 , depicted in FIG. 22 , is described with continuing reference to FIGS. 18B and 18D . The method 1100 provides for the configuration of a V OFFSET loop circuit 41 B, depicted in FIGS. 18B and 18D , to minimize a pre-charging time period of the coupling circuit 18 to a desired offset voltage, V OFFSET , prior to commencing a transmission, by the linear RF power amplifier 22 ( FIG. 1A-B ) of a data burst in a transmission-slot. As an example, prior to commencing the transmission of the data burst, the controller 50 may determine whether a coupling circuit 18 coupled between a parallel amplifier output 32 A and a power amplifier supply voltage, V CC , requires pre-charging prior to initiation of the transmission by a radio frequency power amplifier, (Step 1102 ). Illustratively, the controller 50 may determine whether a data burst to be transmitted is a first data burst of a transmission of data by the linear RF power amplifier 22 . If the data burst to be transmitted is a first data burst of the transmission, the controller 50 may determine that the coupling circuit 18 requires pre-charging prior to transmission of the first data burst.

Alternatively, the controller 50 may determine whether the coupling circuit 18 requires pre-charging based upon the V OFFSET error signal 304 generated by the summing circuit 300 . As an example, the controller 50 may set the value of the V OFFSET — TARGET parameter for the V OFFSET loop circuit 41 B. Thereafter, the controller 50 may obtain the V OFFSET error signal 304 from the V OFFSET loop circuit 41 B via the V OFFSET control bus 312 . If the V OFFSET error signal 304 is greater than a maximum V OFFSET error threshold parameter, the controller 50 determines that the power amplifier supply voltage, V CC , requires pre-charging prior to initiation of transmission of the first burst.

In response to the determination that the coupling circuit between the parallel amplifier and the power amplifier supply voltage, V CC , requires pre-charging, the controller 50 may configure the V OFFSET loop circuit 41 B such that the V OFFSET loop circuit 41 B operates in a first bandwidth mode, where the first bandwidth mode increases the operable bandwidth of the V OFFSET loop circuit 41 B. (Step 1104 ).

As discussed relative to the description of FIGS. 18B and 18D , the integrator with zero compensation 314 may include a first time constant, Tau 0 , and a second time constant, Tau 1 . During normal operation of the V OFFSET loop circuit 41 B, the values of the first time constant, Tau 0 , and a second time constant, Tau 1 , may be configured to optimize regulation of the offset voltage, V OFFSET , that is developed across the coupling circuit 18 . For example, the controller 50 may configure the V OFFSET loop circuit 41 B to operate with a normal frequency bandwidth. Illustratively, to configure the V OFFSET loop circuit 41 B to operate with a normal frequency bandwidth, the controller 50 may configure the first time constant, Tau 0 , to be equal to Tau 0 — normal and the second time constant, Tau 1 , to be equal to Tau 1 — normal. In some embodiments of the V OFFSET loop circuit 41 B, the values of time constants Tau 0 — normal and Tau 1 — normal, may be stored locally with the V OFFSET loop circuit 41 B.

To decrease the time for pre-charging the coupling circuit 18 , the controller may configure the first time constant, Tau 0 , to be equal to a first startup time constant, Tau 0 — startup, and the second time constant, Tau 1 , to be equal to a second startup time constant, Tau 1 — startup. Alternatively, some embodiments of the V OFFSET loop circuit 41 B may be configured to automatically set the first time constant, Tau 0 , equal to the first startup time constant, Tau 0 — startup, and the second time constant, Tau 1 , when the V OFFSET loop circuit 41 B is placed in a pre-charge mode of operation.

In some embodiments of method 1100 , the controller 50 may configure the V OFFSET loop circuit 41 B to initially operate using the first startup time constant, Tau 0 — startup, and the second startup time constant, Tau 1 — startup, by configuring the V OFFSET loop circuit 41 B operate in the pre-charge mode of operation for a period of time. As an example, in some embodiments of the V OFFSET loop circuit 41 B, the period of time in which the V OFFSET loop circuit 41 B operates in a pre-charge mode of operation may be configured by the controller 50 via the V OFFSET control bus 312 . In some embodiments of the V OFFSET loop circuit 41 B, the period of time in which the V OFFSET loop circuit 41 B operates in a pre-charge mode of operation is a predetermined time period that may be configured by the controller 50 via V OFFSET control bus 312 . As an example, the V OFFSET loop circuit 41 B may include a pre-charge timer (not shown) that may be set to trigger a timer event after the predetermined time period.

›DETAILED DESCRIPTION · 57 of 67

Once the coupling circuit 18 is pre-charged, the V OFFSET loop circuit 41 B may be placed into a normal mode of operation. As an example, after a predetermined time period, the V OFFSET loop circuit 41 B may be re-configured such that the V OFFSET loop circuit operates 41 B in a second bandwidth mode, where the second bandwidth mode decreases the operable bandwidth of the V OFFSET loop circuit 41 B. (Step 1106 ). Accordingly, the bandwidth of the V OFFSET loop circuit 41 B that operates in the first bandwidth mode is greater than the bandwidth of the V OFFSET loop circuit 41 B that operates in the second bandwidth mode.

As an example, in order to place the V OFFSET loop circuit 41 B into the second bandwidth mode for normal operation during transmission of data by the linear RF power amplifier 22 , the controller 50 may configure the first time constant, Tau 0 , to be equal to Tau 0 — normal and the second time constant, Tau 1 , to be equal to Tau 1 — normal via the V OFFSET control bus 312 . Alternatively, as an example, V OFFSET loop circuit 41 B may automatically switch from the pre-charge mode of operation to a normal mode of operation upon triggering of the timer event by the pre-charge timer.

Embodiments of an open loop ripple compensation assist circuit 414 , depicted in FIGS. 23A-23D , will now be described. In order to provide context and not by way of limitation, the open loop ripple compensation assist circuit 414 will be described in the context of the example embodiments of a pseudo-envelope follower power management system 10 MA, depicted in FIG. 23A and FIG. 23C , and a pseudo-envelope follower power management system 10 MB, depicted in FIG. 23B and FIG. 23D .

FIGS. 23A-D depict the pseudo-envelope follower power management system 10 MA and pseudo-envelope follower power management system 10 MB, employ a switch mode power supply converter in combination with either an embodiment of the parallel amplifier circuit 14 MA or an embodiment of the parallel amplifier circuit 14 MB to provide techniques for modulating the power amplifier supply voltage, V CC , generated at the power amplifier supply output 28 for use by the linear RF power amplifier 22 .

As an example of a switch mode power supply converter, as depicted in FIG. 23A , the pseudo-envelope follower power management system 10 MA may include an embodiment of a multi-level charge pump buck converter 12 M configured to interface with the parallel amplifier circuit 14 MA. As another example of a configuration that includes a switch mode power supply converter, as depicted in FIG. 23C , an alternative embodiment of the pseudo-envelope follower power management system 10 MA may include an embodiment of a multi-level charge pump buck converter 12 M configured to interface with the parallel amplifier circuit 14 MB. As depicted in both FIG. 23A and FIG. 23C , the interface between the multi-level charge pump buck converter 12 M and either the parallel amplifier circuit 14 MA or the parallel amplifier circuit 14 MB may be configured to provide a parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , the threshold offset current 42 , I THRESHOLD — OFFSET , or a combination thereof, to the multi-level charge pump buck converter 12 M.

As depicted in FIG. 23A and FIG. 23C , and not by way of limitation, some embodiments of the multi-level charge pump buck converter 12 M may include an FLL circuit 54 similar to the FLL circuit 54 of the multi-level charge pump buck converter 12 B, depicted in FIG. 2B . For example, some embodiments of the multi-level charge pump buck converter 12 M may include a switcher control circuit 52 similar to the switcher control circuit 52 A, depicted in FIG. 3A , or the switcher control circuit 52 B, depicted in FIG. 3B . However, alternative embodiments of the multi-level charge pump buck converter 12 M, similar to the embodiments of the multi-level charge pump buck converter 12 B that include an embodiment of the switcher control circuit 52 similar to the switcher control circuit 52 C, depicted in FIG. 3C , and/or the switcher control circuit 52 D, depicted in FIG. 3D , may not include an FLL circuit 54 . Accordingly, operation of the multi-level charge pump buck converter 12 M and the switcher control circuit 52 , depicted in FIG. 23A and FIG. 23C , may also incorporate various combinations of the operational features and functions of the embodiments of the switcher control circuits 52 A-D, depicted in FIGS. 3A-D , the threshold detector and control circuits 132 A-D, depicted in FIGS. 4A-D , and the circuitry and state machines depicted in FIGS. 5A-D and FIG. 6A-D that are associated with the logic circuits 148 A-D, depicted in FIGS. 4A-D .

As another example of a switch mode power supply converter, as depicted in FIG. 23B , an embodiment of the pseudo-envelope follower power management system 10 MB may include an embodiment of a buck converter 13 L configured to interface with the parallel amplifier circuit 14 MA. As another example of a configuration that includes a switch mode power supply converter, as depicted in FIG. 23D , an alternative embodiment of the pseudo-envelope follower power management system 10 MB may include an embodiment of the buck converter 13 L configured to interface with the parallel amplifier circuit 14 MB. As depicted in both FIG. 23B and FIG. 23D , the interface between the buck converter 13 L and either the parallel amplifier circuit 14 MA or the parallel amplifier circuit 14 MB may be configured to provide a parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , the threshold offset current 42 , I THRESHOLD — OFFSET , or a combination thereof, to the buck converter 13 L. Likewise, similar to the buck converter 13 A depicted in FIG. 18C and FIG. 18D , and not by way of limitation, some embodiments of the buck converter 13 L may also include the FLL circuit 54 , as depicted in FIG. 23B and FIG. 23D . For example, some embodiments of the buck converter 13 L may include a switcher control circuit 259 similar to the switcher control circuit 52 E, depicted in FIG. 3E , or the switcher control circuit 52 F, depicted in FIG. 3F . Alternatively, some embodiments of the buck converter 13 L similar to the embodiments of the buck converter 13 A, depicted in FIG. 18C and FIG. 18D that include an embodiment of the switcher control circuit 259 similar to the switcher control circuit 52 G, depicted in FIG. 3G , or the switcher control circuit 52 H, depicted in FIG. 3H , may not include the FLL circuit 54 . Accordingly, operation of the buck converter 13 L and the switcher control circuit 259 , depicted in FIG. 23B and FIG. 23D , may also incorporate various combinations of the operational features and functions of the embodiments of the switcher control circuits 52 E-H, depicted in FIGS. 3E-H , the threshold detector and control circuits 132 E-H, depicted in FIGS. 4E-H , and the circuitry and state machine depicted in FIGS. 5E-H that are associated with the logic circuits 148 E-H, depicted in FIGS. 4E-H .

›DETAILED DESCRIPTION · 58 of 67

Similar to the various example pseudo-envelope follower power management systems described above, the embodiments of the pseudo-envelope follower power management system 10 MA and the pseudo-envelope follower power management system 10 MB, depicted respectively in FIG. 23A , FIG. 23C , FIG. 23B , and FIG. 23D , may be configured to use modulated supply techniques to control the power amplifier supply voltage, V CC , generated on the power amplifier supply output 28 in order to meet various communication system standards implemented in various communication devices. Example communication devices may include mobile terminals and mobile phones. Some of the communication system standards may include the use of wide-band modulation to send and receive information and data over a communication network.

As an example, the Long Term Evolution (LTE) communication standard may use wide-bandwidth modulation in specified transmission frequency bands and receive frequency bands to communicate information and data via the linear RF power amplifier 22 . In addition, the width of each band allocated for wide-band modulation may vary depending upon the transmission frequency band and the receive frequency band that an example communication device is assigned to use in the communication network. For example, the Long Term Evolution (LTE) standard may specify LTE band numbers, where each of the LTE band number corresponds to a specific transmit channel frequency band and a specific receive channel frequency band. As a non-limiting example, the LTE band number corresponds to a band of operation in which a communication device is assigned to operate in a mobile communication network. Thus, in some cases, the band of operation may include a transmit channel and a receive channel. The transmit channel may have a transmit channel frequency band. The receive channel may have a receive channel frequency band. In addition, each band of operation may be assigned a specified duplex spacing, also referred to as a duplex offset, between the specific transmit channel frequency band and the specific receive channel frequency associated the band of operation. For example, the transmit channel and the receive channel for a band of operation may be spaced apart by a duplex offset. The transmit channel may have a transmit channel frequency band. The receive channel may have a receive channel frequency band. For example, each respective LTE band number may be assigned a specific duplex offset. As used herein, the term transmit to receive duplex offset is defined as a frequency having a magnitude substantially equal to the duplex offset between a transmit channel frequency band and a receive channel frequency band for a band of operation within a frequency spectrum. For example, an example band of operation assigned to a communication device may include a transmit channel and corresponding receive channel. The transmit channel may have a transmit channel frequency band between 1920 MHz and 1980 MHz. The corresponding receive channel may have a receive channel frequency band between 2110 MHz and 2170 MHz. As a result, the width of band for the transmit channel frequency band is 60 MHz and the width of band for the receive channel frequency band is 60 MHz. The duplex offset between the transmit channel and the receive channel is 190 MHz. As a result, the transmit to receive duplex offset is 190 MHz.

However, due to the non-ideal, (non-zero), output impedance of the parallel amplifier 35 and the large ripple currents associated with the power inductor currents, the modulated supply techniques implemented by the different embodiments of the pseudo-envelope follower power management system 10 MA and the pseudo-envelope follower power management system 10 MB, depicted in FIGS. 23A-D , may result in generation of ripple voltages in the power amplifier supply voltage, V CC , at the power amplifier supply output 28 supplied to the linear RF power amplifier 22 . Some of the generated ripple voltages may include high frequency ripple voltages that are located near a frequency substantially equal to the transmit to receive duplex offset of a communication device. The high frequency ripple voltages may be spread out over a frequency band that is near the transmit to receive duplex offset associated for the band of operation of a communication device. For example, the high frequency ripple voltages may be within a frequency band centered about the frequency substantially equal to the transmit to receive duplex offset for the band of operation of the communication device. As a result, the high frequency ripple voltages that are within a band of frequencies substantially equal to at least the bandwidth of the receive channel frequency band, where the band of frequencies are is centered at the transmit to receive duplex offset associated with the band of operation of a communication device may be modulated into the RF signal being generated for transmission by the linear RF power amplifier 22 .

To compensate for the ripple voltages in the power supply voltage, V CC , the parallel amplifier will attempt to source or sink current to cancel out the ripple voltage on the power amplifier supply voltage, V CC . However, because the parallel amplifier 35 , depicted in FIGS. 23A-D , may exhibit a non-ideal output impedance in the operating frequency range of the linear RF power amplifier 22 . In addition, the non-ideal output impedance of the parallel amplifier 35 may also be non-linear. As a result, the parallel amplifier 35 may generate high frequency ripple voltages at the parallel amplifier output 32 A. The generated high frequency ripple voltages generated by the parallel amplifier 35 may give rise to the generation of high frequency ripple voltages in the power amplifier supply voltage, V CC , supplied to the linear RF power amplifier 22 . The frequencies of the high frequency ripple voltages may include frequencies that are near or within a band of frequencies substantially equal to at least the bandwidth of the receive channel frequency band that is centered at the transmit to receive duplex offset associated with the band of operation of a communication device. Thus, the high frequency ripple voltages may be near or in the operational bandwidth of the linear RF power amplifier 22 . FIGS. 23A-23D depict that the open loop ripple compensation assist circuit 414 is in communication with the power amplifier supply output 28 via the coupling circuit 18 . As will be described below, embodiments of the open loop ripple compensation assist circuit 414 , depicted in FIGS. 23A-23D , may be configured by the controller 50 to generate or provide a high frequency ripple compensation current 416 , I COR , at the parallel amplifier output 32 A to reduce or cancel out the high frequency ripple currents at the power amplifier supply output 28 to minimize the high frequency ripple voltages generated by the parallel amplifier 35 in response to high frequency ripple currents at the power amplifier supply output 28 , where the high frequency ripple currents are at frequencies that are near or within a band of frequencies centered near or at the transmit to receive duplex offset associated with the band of operation of a communication device and having a bandwidth substantially equal to at least the bandwidth of the receive channel frequency band for a mode operation. The high frequency ripple compensation current 416 , I COR , may be injected into the parallel amplifier output 32 A to cancel out high frequency ripple currents at the power amplifier supply output 28 that are induced by the switching action of the switching voltage output 26 . A ripple rejection response is a measure of the ability of the pseudo-envelope follower power management system to attenuate ripple voltages at the power amplifier power supply 28 that are due to the switching action at the switching voltage output 26 . In other words, the ripple rejection response of the pseudo-envelope follower power management system is a measurement of the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC , with respect to the peak-to-peak switching voltage, V SW . The high frequency ripple compensation current 416 , I COR , injected into the parallel amplifier output 32 A cancels out high frequency ripple currents such that a ripple rejection response of the pseudo-envelope follower power management system includes a notch located in a frequency band within an operational bandwidth of a linear RF power amplifier. For example, the notch of the ripple rejection response may be located at or near the transmit to receive duplex offset for a band of operation in which the linear radio frequency power amplifier is configured to be used. In addition, as will be described, some embodiments of the open loop ripple compensation assist circuit 414 , depicted in FIGS. 23A-23D , may be configured to generate the high frequency ripple compensation current 416 , I COR , independent of the non-ideal output impedance of the parallel amplifier 35 .

›DETAILED DESCRIPTION · 59 of 67

Operationally, the open loop ripple compensation assist circuit 414 effectively develops an estimate of the high frequency current components in the inductor current, I SW — OUT , to be cancelled out. The open loop ripple compensation assist circuit 414 is in communication with the power amplifier supply output 28 via the coupling circuit 18 . The high frequency ripple compensation current 416 , I COR , is injected into the parallel amplifier output 32 A to substantially cancel out the high frequency current ripple currents in the inductor current, I SW — OUT , that correspond to a V RAMP signal, where the high frequency current ripple currents are at frequencies that are near or within a band of frequencies centered near or at the transmit to receive duplex offset associated with the band of operation of a communication device, and where the band of frequencies has a bandwidth substantially equal to at least the bandwidth of the receive channel frequency band for a mode operation of the communication device. As a result, the high frequency ripple compensation current 416 , I COR , cancel out the high frequency ripple currents that would create noise on the transmit signal generated by the linear RF power amplifier 22 . To limit the frequency band of the portion of the inductor current, I SW , to be cancelled out by the injection of the high frequency ripple compensation current 416 , I COR , the open loop ripple compensation assist circuit 414 high pass filters an estimate of the inductor current, I SW — OUT , based on the transmit to receive duplex offset and the bandwidth of the receive channel frequency band for the band of operation the communication device is configured to used.

In contrast, as described above, FIG. 10 depicts an embodiment of the parallel amplifier output impedance compensation circuit 37 A that uses an estimated inductance of the parallel amplifier 35 at the frequencies near or within operational bandwidth of the linear RF power amplifier 22 to generate a compensated V RAMP signal, V RAMP — C . For example, the parallel amplifier output impedance compensation circuit 37 A may use a programmable value of the parallel amplifier inductance estimate parameter, L CORR — EST , as the estimated inductance of the parallel amplifier 35 at the frequencies near or within operational bandwidth of the linear RF power amplifier 22 . Accordingly, as described above with respect to the operation of the parallel amplifier output impedance compensation circuit 37 A, the compensated V RAMP signal, V RAMP — C , is used by the parallel amplifier 35 instead of the V RAMP signal in order to reduce the high frequency ripple voltages present in the parallel amplifier output voltage, V- PARA — AMP , generated by the parallel amplifier 35 in the parallel amplifier output 32 A due to the non-ideal output impedance characteristics of the parallel amplifier. Thus, the effectiveness of the cancellation or reduction of the high frequency ripple voltages generated by the parallel amplifier 35 by the parallel amplifier output impedance compensation circuit 37 A may be dependent on the frequency dependent output impedance characteristics of the parallel amplifier 35 measure at the time of calibration of the communication device.

FIG. 23A depicts an embodiment of a pseudo-envelope follower power management system 10 MA that that is similar to the pseudo-envelope follower power management system 10 B, depicted in FIG. 2B . However, unlike the pseudo-envelope follower power management system 10 B, depicted in FIG. 2B , the pseudo-envelope follower power management system 10 MA, depicted in FIG. 23A includes an embodiment of a multi-level charge pump buck converter 12 M instead of multi-level charge pump buck converter 12 B. Also, unlike the pseudo-envelope follower power management system 10 B, depicted in FIG. 2B , the pseudo-envelope follower power management system 10 MA, depicted in FIG. 23A includes an embodiment of a parallel amplifier circuit 14 MA.

However, similar to the embodiment of the parallel amplifier circuit 14 B, depicted in FIG. 2B , the embodiment of the parallel amplifier circuit 14 MA, depicted in FIG. 23A , includes parallel amplifier circuitry 32 and a V OFFSET loop circuit 41 . The embodiment of the parallel amplifier circuitry 32 , depicted in FIG. 23A , may include an embodiment of the parallel amplifier 35 and an embodiment of the parallel amplifier sense circuit 36 , similar to the parallel amplifier 35 and the parallel amplifier sense circuit 36 depicted in FIG. 2B . In addition, some embodiments of the parallel amplifier 35 , depicted in FIG. 23A , may be similar to one of the embodiments of the parallel amplifier 35 . Example embodiments of the parallel amplifier 35 may include the parallel amplifier 35 A, the rechargeable parallel amplifier 35 B, the rechargeable parallel amplifier 35 C, the parallel amplifier 35 D, the rechargeable parallel amplifier 35 E, and the rechargeable parallel amplifier 35 F, as depicted in the respective FIGS. 12A-F .

Accordingly, although not depicted in FIG. 23A for the sake of convenience, and not by way of limitation, some embodiments of the parallel amplifier circuit 14 MA may be advantageously similar to the parallel amplifier circuit 14 C, depicted in FIG. 18A , and the parallel amplifier circuit 14 D, depicted in FIG. 18B , where a parallel amplifier supply voltage, V SUPPLY — PARA — AMP , is provided to provide a supply voltage to the parallel amplifier, parallel amplifier sense circuit 36 , some portions of the parallel amplifier circuitry 32 , and/or a combination thereof.

Thus, although not depicted in FIG. 23A for the sake of simplicity and not by way of limitation, similar to the embodiments of the pseudo-envelope follower power management system 10 C, depicted in FIG. 18A , and the pseudo-envelope follower power management system 10 E, depicted in FIG. 18B , some embodiments of the pseudo-envelope follower power management system 10 MA may be configured to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP . For example, some embodiments of the pseudo-envelope follower power management system 10 MA may further include an embodiment of the μC charge pump circuit 262 , depicted in FIGS. 18A-D , the μC charge pump circuit 262 A, depicted in FIG. 19A , or the μC charge pump circuit 262 B, depicted in FIG. 19B . Furthermore, although not depicted in FIG. 23A for the sake of simplicity, and not by way of limitation, some embodiments of the multi-level charge pump buck converter 12 M may replace the multi-level charge pump circuit 56 with an embodiment of the multi-level charge pump circuit 258 of the multi-level charge pump buck converter 12 C, depicted in FIG. 18A and FIG. 18B . In those embodiments of the multi-level charge pump buck converter 12 M that are adapted to include an embodiment of the multi-level charge pump circuit 258 , the multi-level charge pump buck converter 12 M may be similar to either the example embodiment of the multi-level charge pump circuit 258 A, depicted in FIG. 7B , or the example embodiment of the multi-level charge pump circuit 258 B, depicted in FIG. 7C . Accordingly, the alternative embodiments of the multi-level charge pump buck converter 12 M that include an embodiment of the multi-level charge pump circuit 258 , (not depicted in FIG. 23A ), may generate an internal charge pump node parallel amplifier supply 294 ( FIGS. 18A-D ) to provide the parallel amplifier supply voltage, V SUPPLY — PARA — AMP , to an embodiment of the parallel amplifier 35 similar to the parallel amplifier 35 D, the rechargeable parallel amplifier 35 E, or the rechargeable parallel amplifier 35 F, respectively depicted in FIGS. 12D-F .

›DETAILED DESCRIPTION · 60 of 67

In the embodiments of the pseudo-envelope follower power management system 10 MA, depicted in FIG. 23A , the parallel amplifier circuit 14 MA may include an embodiment of the V OFFSET loop circuit 41 similar to the V OFFSET loop circuit 41 A, depicted in FIG. 18A , the V OFFSET loop circuit 41 B, depicted in FIG. 18B , or the V OFFSET loop circuit 41 , depicted in FIG. 8 . Accordingly, the parallel amplifier circuit 14 MA may be configured to provide the threshold offset current 42 , I THRESHOLD — OFFSET , to the switcher control circuit 52 of the multi-level charge pump buck converter 12 M. Accordingly, similar to the embodiment of the multi-level charge pump buck converter 12 B, depicted in FIG. 2B , the multi-level charge pump buck converter 12 M may use the threshold offset current 42 , I THRESHOLD — OFFSET , to adjust the switching operation of the multi-level charge pump buck converter 12 M.

Continuing with the description of FIG. 23A , as discussed above, the parallel amplifier circuit 14 MA may further include an embodiment of the open loop ripple compensation assist circuit 414 . The open loop ripple compensation assist circuit 414 may be configured by the controller 50 via the control bus 44 . The open loop ripple compensation assist circuit 414 may include or be associated with programmable filter parameter(s), programmable gain parameter(s), and programmable delay parameter(s). In some embodiments, some of the programmable filter parameter(s), the programmable gain parameter(s), and the programmable delay parameter(s) are determined at calibration. However, in some embodiments of the open loop ripple compensation assist circuit 414 , at least some of the programmable filter parameter(s), the programmable gain parameter(s), and the programmable delay parameter(s) may be optimized by the controller 50 based on the operational mode of the pseudo-envelope follower power management system 10 MA.

The open loop ripple compensation assist circuit 414 may be configured to inject the high frequency ripple compensation current 416 , I COR , at or into the parallel amplifier output 32 A to provide the high frequency ripple compensation current 416 , I COR , to the power amplifier supply output 28 . As will be discussed in further detail below, the open loop ripple compensation assist circuit 414 generates the high frequency ripple compensation current 416 , I COR , to minimize the high frequency ripple voltages on the power amplifier supply voltage, V CC , supplied to the linear RF power amplifier 22 .

In some embodiments, the open loop ripple compensation assist circuit 414 may use the V RAMP signal and an estimate of the switching voltage, V SW , provided at the switching voltage output 26 of the multi-level charge pump buck converter 12 M, to determine or generate an estimate of the ripple currents present at the power amplifier supply output 28 . The open loop ripple compensation assist circuit 414 may be configured to high pass filter the estimate of the ripple currents present at the power amplifier supply output 28 to obtain an estimate of the high-frequency ripple currents located near or within a band of frequencies centered near or at the transmit to receive duplex offset associated with the band of operation in which the linear RF power amplifier 22 is being used, where the band of frequencies has a bandwidth substantially equal to at least the bandwidth of the receive channel frequency band for a band of operation at the power amplifier supply output 28 . For example, some embodiments of the open loop ripple compensation assist circuit 414 may include programmable filters or filtering circuits, where the filter characteristics of the programmable filters may be adjusted based on the programmable filter parameter(s). For example, the programmable filters may provide a first high pass filter response and a second high pass filter response, where the first high pass filter response is associated with a first corner frequency, f C1 , and the second high pass filter response is associated with a second corner frequency, f c2 . The controller 50 may be configured to adjust the programmable filter parameter(s) associated with each of the first high pass filter response and a second high pass filter response. In addition, the magnitude of the high frequency ripple compensation current 416 , I COR , may be adjusted based on the programmable gain parameter(s). In some embodiments, the programmable gain parameter(s) may be parameters used to set a programmable transconductance related parameter.

Based on the estimate of the high-frequency ripple currents that include frequencies near or within a band of frequencies centered near or at the transmit to receive duplex offset associated with the band of operation in which the linear RF power amplifier 22 is being used, where the band of frequencies has a bandwidth substantially equal to at least the bandwidth of the receive channel frequency band for the band of operation, the open loop ripple compensation assist circuit 414 may generate the high frequency ripple compensation current 416 , I COR . In addition, as will be discussed, the open loop ripple compensation assist circuit 414 may adjust the magnitude of the high frequency ripple compensation current 416 , I COR , and time align the generation of the high frequency ripple compensation current 416 , I COR , such that the high frequency ripple compensation current 416 , I COR , maximally cancels out the high-frequency ripple currents, present at the power amplifier supply output 28 , that are near or within operational bandwidth of the linear RF power amplifier 22 . In other words, the controller 50 may configure the open loop ripple compensation assist circuit 414 to inject the high frequency ripple compensation current 416 , I COR , at the parallel amplifier output 32 A to create a notch in the ripple rejection response, measured at the power amplifier supply output 28 , that is located near a transmit to receive duplex offset for a band of operation in which the linear radio frequency power amplifier is configured to be used. As an example, the controller 50 may adjust the programmable delay parameter(s) to move the location of the notch in the ripple rejection response a function of the transmit to receive duplex offset for the band of operation for which the linear RF power amplifier 22 is configured to be used. For example, the controller 50 may be configured to adjust the programmable delay parameter(s) to temporally align the injection of the high frequency ripple compensation current 416 , I COR , at parallel amplifier output 32 A to create a notch in a ripple rejection response of the power amplifier supply output that is located near a transmit to receive duplex offset for a band of operation in which the linear radio frequency power amplifier is configured to be used.

›DETAILED DESCRIPTION · 61 of 67

In addition, in some embodiments, the controller 50 may be configured to adjust the programmable filter parameter(s) to adjust the width, depth, shape, and/or a combination thereof such that the high frequency ripple compensation current 416 maximally cancels out the high-frequency ripple currents generated by the parallel amplifier 35 in frequencies near or within the operational bandwidth of the linear RF power amplifier 22 .

In addition, the open loop ripple compensation assist circuit 414 may be further configured to generate a scaled high frequency ripple compensation current estimate 418 , I COR — SENSE . The scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , may be a fractional representation of the high frequency ripple compensation current 416 , I COR , provided to the output of the parallel amplifier output 32 A. For example, the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , may be linearly related to the high frequency ripple compensation current 416 , I COR , by the sense scaling factor, C SENSE — SCALING . As depicted in FIG. 23A , the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , may be combined with the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , generated by the parallel amplifier sense circuit 36 to form the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST . The parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , including the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , and the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , may be provided to the multi-level charge pump buck converter 12 M. Accordingly, similar to the embodiment of the multi-level charge pump buck converter 12 B, depicted in FIG. 2B , the multi-level charge pump buck converter 12 M may use the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , to adjust the switching operation of the multi-level charge pump buck converter 12 M.

For the sake of simplicity of description, and not by way of limitation, FIG. 23A depicts the embodiment of the parallel amplifier circuit 14 MA, as not including an open loop assist circuit 39 , which is included as part of the parallel amplifier circuit 14 B depicted in FIG. 2B . Also, unlike the multi-level charge pump buck converter 12 B depicted in FIG. 2B , for the sake of simplicity of description, and not by way of limitation, the embodiment of the multi-level charge pump buck converter 12 M depicted in FIG. 23A does not depict the multi-level charge pump buck converter 12 M providing an estimated switching voltage output 38 B, V SW — EST , as an output to the parallel amplifier circuit 14 MA.

However, FIG. 23C depicts an example embodiment of the pseudo-envelope follower power management system 10 MA that includes a multi-level charge pump buck converter 12 M and an embodiment of a parallel amplifier circuit 14 MB that includes an open loop ripple compensation assist circuit 414 in combination with an open loop assist circuit 39 , where the open loop assist circuit 39 may be similar to the embodiment of the open loop assist circuit 39 depicted in FIG. 2B . Accordingly, as depicted in FIG. 23C , embodiments of the pseudo-envelope follower power management system 10 MA that include the parallel amplifier circuit 14 MB, may provide a parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , to adjust the switching operation of the multi-level charge pump buck converter 12 M, where the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , is generated by combining the scaled parallel amplifier output current estimate, I PARA — AMP — SENSE , the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , and the scaled open loop assist circuit output current estimate, I ASSIST — SENSE .

As further depicted in FIG. 23A , the multi-level charge pump buck converter 12 M is further configured to provide a delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , to a programmable delayed switching voltage input (not shown) of the parallel amplifier circuit 14 MA. The programmably delayed switching voltage input is in communication with the open loop ripple compensation assist circuit 414 of the parallel amplifier circuit 14 MA and configured to receive the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR . Similar to the estimated switching voltage output 38 B, V SW — EST , generated by the multi-level charge pump buck converter 12 B, depicted in FIG. 2B , the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , is a feed forward signal generated based on the state of the switcher control circuit 52 , where the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , provides an early indication of what the switching voltage output, V SW , will become based on the state of the switcher control circuit 52 . Thus, the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , may be a feed forward signal that indicates a future voltage level of the switching voltage output, V SW , at the switching voltage output 26 based on the state of the switcher control circuit 52 before the switching voltage output 26 is configured to provide a switching voltage output, V SW , substantially equal to the future voltage level. In other words, delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , provides a switching output voltage estimate that that may be programmably delayed by the programmable delay circuitry 432 . In this way, the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , may be considered a version of the estimated switching voltage output 38 B, V SW — EST , that may be programmably delayed by the programmable delay circuitry 432 to time align generation of the high frequency ripple compensation current 416 , I COR . For example, the programmable delay circuitry 432 may be configured to have a programmable delay period such that the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , is delayed in time by substantially the programmable delay period relative to the estimated switching voltage output 38 B, V SW — EST . The controller 50 may programmatically configure programmable delay circuitry in the multi-level charge pump buck converter 12 M to provide a programmable delay period between generation of the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , relative to generation of the estimated switching voltage output 38 B, V SW — EST . The controller 50 may adjust the programmable delay period to align the generation of the high frequency ripple compensation current 416 , I COR , to cancel out the high frequency ripple currents generated by the parallel amplifier 35 in response to the V RAMP signal. Illustratively, the controller 50 may be configured to adjust the programmable delay period to temporally align the injection of the high frequency ripple compensation current 416 , I COR , at parallel amplifier output 32 A, to create a notch in a ripple rejection response of the power amplifier supply output that is located near a transmit to receive duplex offset for a band of operation in which the linear radio frequency power amplifier is configured to be used.

›DETAILED DESCRIPTION · 62 of 67

As will be discussed below, the controller 50 may be further configured to programmatically change the values of the programmable filter parameter(s), programmable gain parameter(s), and programmable delay parameter(s) to obtain an optimized overall system response of the pseudo-envelope follower power management system 10 MA to place a notch in the ripple rejection response at the power amplifier supply output 28 as a function of the duplex offset for each band of operation. Thus, depending on the band of operation in which the linear RF power amplifier 22 is configured to be used, the controller 50 may configure the notch in the ripple rejection response to be located near or at the transmit to receive duplex offset associated with the selected band of operation. In addition, the bandwidth of the receiver channel frequency band for the band of operation is used to configure the ripple rejection response to substantially cancel output the high frequency ripple currents that could be modulated onto the transmit signal generated by the linear RF power amplifier. For example, FIG. 25 depicts the notch response of example pseudo-envelope follower power management system 10 MA and 10 MB, as depicted in FIGS. 23A-D , as a function of the programmable delay period.

As previously discussed, FIG. 23B depicts an embodiment of a pseudo-envelope follower power management system 10 MB that includes a buck converter 13 L and an embodiment of the parallel amplifier circuit 14 MA. As discussed above, the buck converter 13 L interfaces with the parallel amplifier circuit 14 MA. The operation of the parallel amplifier circuit 14 MA in conjunction with the buck converter 13 L is substantially similar to the operation of the embodiments of the parallel amplifier circuit 14 MA with the multi-level charge pump buck converter 12 M. Likewise, the pseudo-envelope follower power management system 10 MB may include the features and functions of the various embodiments and alternative embodiments of the pseudo-envelope follower power management system 10 MA, as described above, except, similar to the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C , and the pseudo-envelope follower power management system 10 F, depicted in FIG. 18D , the buck converter 13 L may not generate an internal charge pump node parallel amplifier supply 294 because the buck converter 13 L does not include an embodiment of the multi-level charge pump circuit 56 that is included in the multi-level charge pump buck converter 12 M of the pseudo-envelope follower power management system 10 MA, depicted in FIG. 23A . Even so, although not depicted in FIG. 23B , some alternative embodiments of the pseudo-envelope follower power management system 10 MB may include an embodiment of the μC charge pump circuit 262 and associated circuitry similar to the pseudo-envelope follower power management system 10 D, depicted in FIG. 18C , and the pseudo-envelope follower power management system 10 F, depicted in FIG. 18D , in order to provide a parallel amplifier supply voltage, V SUPPLY — PARA — AMP , to an embodiment of the parallel amplifier 35 similar to the parallel amplifier 35 D, the rechargeable parallel amplifier 35 E, or the rechargeable parallel amplifier 35 F, respectively depicted in FIGS. 12D-F .

FIG. 23C depicts an alternative embodiment of the pseudo-envelope follower power management system 10 MA that is similar in form and function to the embodiments of the pseudo-envelope follower power management system 10 MA discussed with reference to FIG. 23A . However, unlike the alternative embodiment of the pseudo-envelope follower power management system 10 MA depicted in FIG. 23A , the pseudo-envelope follower power management system 10 MA depicted in FIG. 23C includes the parallel amplifier circuit 14 MB instead of the parallel amplifier circuit 14 MA. As previously discussed, the parallel amplifier circuit 14 MB is similar in form and function to the parallel amplifier circuit 14 MA, described previously, except that the parallel amplifier circuit 14 MB include an embodiment of the open loop assist circuit 39 . Accordingly, the alternative embodiment of the pseudo-envelope follower power management system 10 MA depicted in FIG. 23C is functionally similar to the embodiment of the pseudo-envelope follower power management system 10 MA depicted in FIG. 23A except the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , further includes the scaled open loop assist circuit output current estimate, I ASSIST — SENSE , and the open loop assist circuit 39 provides the open loop assist circuit current, I ASSIST , at the parallel amplifier output 32 A.

FIG. 23D depicts an alternative embodiment of the pseudo-envelope follower power management system 10 MB that is substantially similar in form and function to the embodiment of the pseudo-envelope follower power management system 10 MB depicted in FIG. 23B except the alternative embodiment of the pseudo-envelope follower power management system 10 MB depicted in FIG. 23D includes the parallel amplifier circuit 14 MB instead of the parallel amplifier circuit 14 MA. Accordingly, the alternative embodiment of the pseudo-envelope follower power management system 10 MB depicted in FIG. 23D is functionally similar to the pseudo-envelope follower power management system 10 MB, depicted in FIG. 23B , except the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST , further includes the scaled open loop assist circuit output current estimate, I ASSIST — SENSE , and the open loop assist circuit 39 provides the open loop assist circuit current, I ASSIST , at the parallel amplifier output 32 A.

FIG. 24 depicts an embodiment of the open loop ripple compensation assist circuit 414 A and a portion of a switch mode power supply converter 420 . The switch mode power supply converter 420 may be similar in form and function to the embodiment of the multi-level charge pump buck converter 12 M, depicted in FIG. 23A and FIG. 23C , or the buck converter 13 L, depicted in FIG. 23B and FIG. 23D . The switcher control circuit (not shown) of the switch mode power supply converter 420 may be configured as one of the embodiments of the switcher controller 52 when the switch mode power supply converter 420 is configured as one of the embodiments of a multi-level charge pump buck converter as described herein. Alternatively, the switcher control circuit (not shown) of the switch mode power supply converter 420 may be configured as one of the embodiments of the switcher controller 52 when the switch mode power supply converter 420 is configured as one of the embodiments of a buck converter as described herein. Accordingly, similar to the previously described embodiments of the multi-level charge pump buck converter 12 M and the buck converter 13 L, the switch mode power supply converter 420 may be configured to provide a delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , to the open loop ripple compensation assist circuit 414 A. Although not depicted in FIG. 24 , it will be understood that controller 50 , depicted in FIGS. 23A-D , may be configured to control or configure the elements of the open loop ripple compensation assist circuit 414 A.

›DETAILED DESCRIPTION · 63 of 67

The open loop ripple compensation assist circuit 414 A may include an embodiment of a combined filter and gain assist circuitry 422 A. The combined filter and gain assist circuitry 422 A may include a ripple cancellation circuit 424 and a Gm assist circuit 426 . The Gm assist circuit 426 may include an input port 426 A, a Gm assist I COR output 426 B, and a Gm assist I COR — SENSE output 426 C. The controller 50 may be configured to adjust the transconductance of the Gm assist circuit 426 .

The combined filter and gain assist circuitry 422 A may include an integrator circuit 428 and high pass filter circuitry 430 . The high pass filter circuitry 430 may include a high pass filter circuitry input 430 A and a high pass filter circuitry output 430 B. The controller 50 may configure the high pass filter circuitry 430 to provide a desired high pass frequency response by adjusting the time constants associated with the high pass filter circuitry 430 . The integrator circuit 428 may include a non-inverting input 428 A configured to receive the V RAMP signal and an inverting input 428 B configured to receive the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR . Although not depicted in FIG. 24 , in some embodiments of the open loop ripple compensation assist circuit 414 A, the V RAMP signal may be scaled by a scaling factor, K VRAMP — SCALE , such that the non-inverting input 428 A of the integrator circuit 428 receives a scaled V RAMP signal, V RAMP — SCALED , where V RAMP — SCALED =K×V RAMP . The integrator output 428 C is coupled to the high pass filter circuitry input 430 A of the high pass filter circuitry 430 . The high pass filter circuitry output 430 B of the high pass filter circuitry 430 is coupled to the input port 426 A of the Gm assist circuit 426 . Based on the integrated and high pass filtered signal generated by the ripple cancellation circuit 424 , the Gm assist circuit 426 generates the high frequency ripple compensation current 416 , I COR , at the Gm assist I COR output 426 B and the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , at the Gm assist I COR — SENSE output 426 C.

In order to place a notch in the ripple rejection response of the power amplifier supply output 28 as a function of the transmit to receive duplex offset for each band of operation, the open loop ripple compensation assist circuit 414 A may be configured to generate a predicted estimated inductor current, I SW — OUT — EST , for the inductor current, I SW — OUT , that is provided by the power inductor 16 , as depicted in FIG. 23A , based on a difference between the V RAMP signal and the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , and the inductance value of the power inductor 16 , depicted in FIGS. 23A-D . The predicted estimated inductor current, I SW — OUT — EST , is an estimate of the inductor current, I SW — OUT , in the power inductor 16 corresponding temporally to when the switching voltage, V SW , to be generated at the switching voltage output 26 which is represented by the value of the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , and the V RAMP signal reflects the voltage level of the power amplifier supply voltage, V CC . However, in order to simplify circuitry, and because the high frequency ripple compensation current 416 , I COR , is injected at or into the parallel amplifier output 32 A to cancel out the high frequency ripple components of the inductor current, I SW — OUT , near or within a band of frequencies substantially equal to at least the bandwidth of the receive channel frequency band that is centered at the transmit to receive duplex offset associated with the band of operation in which the of the linear RF power amplifier 22 is being used, the ripple cancellation circuit generates the negative of the predicted estimated inductor current, I SW — OUT — EST . As an example, the integrator circuit 428 may be configured to integrate the difference between the V RAMP signal and the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , to generate the negative of the predicted estimated inductor current, I SW — OUT — EST . The negative of the predicted estimated inductor current, I SW — OUT — EST , may be represented by the Laplace transfer function of the integrator circuit 428 , shown in equation (4) as follows:

- I SW_OUT ⁢ _EST ⁡ ( s ) = ( V RAMP - V SW ⁢ _ ⁢ OUT ⁢ _ ⁢ EST ) L POWER_INDUCTOR ⁢ s ( 4 )

where L POWER — INDUCTOR represents the inductance of the power inductor 16 depicted in FIGS. 23A-D .

Thus, referring to FIGS. 23A-D , the predicted estimated inductor current, I SW — OUT — EST , provides an estimate of the current through the power inductor 16 corresponding to the time when the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , reflects the voltage level of the switching voltage, V SW , provided at the switching voltage output 26 and the V RAMP signal reflects the voltage level of the power amplifier supply voltage, V CC . The negative of the predicted estimated inductor current, I SW — OUT — EST , is provided to the high pass filter circuitry 430 , which high pass filters the negative of the predicted estimated inductor current, I SW — OUT — EST , to generate an estimate of the predicted high frequency ripple currents, I HIGH — FREQUENCY — RIPPLE , to be cancelled out, at the power amplifier supply output 28 when the switching voltage, V SW , to be generated at the switching voltage output 26 is represented by the value of the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , and the V RAMP signal represents the power amplifier supply voltage, V CC . The pass band characteristics of the high pass filter circuitry 430 may be adjusted by the controller 50 based on the programmable filter parameter(s) such that the frequency content of the predicted high frequency ripple currents I HIGH — FREQUENCY — RIPPLE , to be cancelled out, at the power amplifier supply output 28 , includes frequencies that are near or within a band of frequencies substantially equal to at least the bandwidth of the receive channel frequency band that is centered at the transmit to receive duplex offset associated with the band of operation for which the linear RF power amplifier 22 is being used.

›DETAILED DESCRIPTION · 64 of 67

As an example, the high pass filter circuitry 430 may provide a first high pass filter response and a second high pass filter response, where the first high pass filter response corresponds to a first corner frequency, f C1 , and the second high pass filter response corresponds to a second corner frequency, f C2 . In some embodiments, the first corner frequency, f C1 , and the second corner frequency, f C2 , may be configured by the controller 50 (not shown). The first corner frequency, f C1 , and the second corner frequency, f C2 , may be adjusted based on the bandwidth of the receive channel frequency band associated with each band of operation of the linear RF power amplifier 22 .

The high pass filter circuitry 430 provides the predicted high frequency ripple currents to be cancelled out, I HIGH — FREQUENCY — RIPPLE , to the Gm assist circuit 426 . The Gm assist circuit 426 gain scales the predicted high frequency ripple currents to be cancelled out, I HIGH — FREQUENCY — RIPPLE , to generate the high frequency ripple compensation current 416 , I COR , based on the predicted high frequency ripple currents, I HIGH — FREQUENCY — RIPPLE , to be cancelled out, and the programmable gain parameter(s) provided by the controller 50 . In addition, the Gm assist circuit 426 also generates the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , which is a fractional representation of the high frequency ripple compensation current 416 , I COR , used to generate the parallel amplifier circuit output current estimate 40 , I PAWA — OUT — EST . Because the predicted estimated inductor current, I SW — OUT — EST , is high pass filtered, the predicted high frequency ripple currents, I HIGH — FREQUENCY — RIPPLE , to be cancelled out, do not reflect the low-frequency modulation of the power amplifier supply output 28 . As a result, the high frequency ripple compensation current 416 , I COR , does not conflict with the efforts of the parallel amplifier 35 to compensate for the low-frequency modulation of the power amplifier supply voltage, V CC , due to the change in the switching voltage, V SW , at the switching voltage output 26 , depicted in FIGS. 23A-D .

As further depicted in FIG. 24 , the switch mode power supply converter 420 includes programmable delay circuitry 432 and a buffer scalar 434 . For the sake of simplicity, and not by way of limitation, the generation of the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , by the switch mode power supply converter 420 will now be discussed with reference to the embodiment of the threshold detector and control circuit 132 A, depicted in FIG. 4A . As depicted in FIG. 4A , the threshold detector and control circuit 132 A may generate one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s). The one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), indicate the state of the switch control circuit (not shown) of the switch mode power supply converter 420 before the switch mode power supply converter 420 transitions to provide the switching voltage output, V SW , represented by the switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s). For example, in the case where the switch mode power supply converter 420 is similar to the embodiment of the multi-level charge pump buck converter 12 B, depicted in FIG. 2B , the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), may be used by the third output buffer 161 to generate one of the various embodiments of the estimated switching voltage output 38 B, V SW — EST , depicted in FIGS. 11A-11F . As depicted in FIG. 11A , in the simplest form, the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), may be a single digital signal that represents the future state of the switching voltage output 26 as being in either the shunt level or providing a voltage greater than ground to the power inductor 16 , as depicted in FIG. 2B . Similarly, in the case where the switch mode power supply converter 420 is similar to the buck converter 13 L depicted in FIG. 23B , the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), may be a single digital signal that represents the future state of the switching voltage output 26 as being in either the shunt level or the series level.

Returning to FIG. 24 , the programmable delay circuitry 432 is configured to receive the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s). The controller 50 may use the programmable delay parameter(s) to delay the propagation of the one or more switching voltage output cmos signal(s) 166 , V SW — EST — CMOS — SIGNAL (s), through the programmable delay circuitry 432 by a programmable delay period to generate the one or more programmably delayed switching voltage output cmos signal(s) 166 A, V SW — EST — CMOS — DELAYED — SIGNAL (s). The one or more programmably delayed switching voltage output cmos signal(s) 166 A, V SW — EST — CMOS — DELAYED — SIGNAL (s) are provided to the buffer scalar 434 . The controller 50 (not shown) may provide a scaling factor, M, based on a scaling factor parameter stored in association with the controller 50 , the parallel amplifier circuit, or the switch mode power supply converter 420 . Accordingly, based on the scaling factor parameter, the controller 50 may set the value of the scaling factor, M, received by the buffer scalar 434 . Similar to the third output buffer 161 , depicted in FIG. 4A , the buffer scalar 434 generates the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , based on the one or more programmably delayed switching voltage output cmos signal(s) 166 A, V SW — EST — CMOS — DELAYED — SIGNAL (s), and the scaling factor, M, provided by the controller 50 . The controller 50 (not shown) may adjust the value of the scaling factor, M, to account for variations in the magnitude of the V RAMP signal and to ensure proper performance of the ripple cancellation circuit 424 . In other embodiments, the controller 50 (not shown) may adjust the scaling factor, M, to compensate for changes in the direct current (DC) voltage, V BAT , from the battery 20 . Example embodiments of the programmable delay circuitry 432 are depicted in FIGS. 29A-B and FIG. 30 .

›DETAILED DESCRIPTION · 65 of 67

To time align the generation of the high frequency ripple compensation current 416 , I COR , the controller 50 programmatically adjusts the delay provided by the programmable delay circuitry 432 based on the programmable delay parameter(s). The controller 50 may configure the delay time through the programmable delay circuitry 432 to move the placement of the notch in the ripple rejection response of the pseudo-envelope follower power management system 10 MA. As an example, the controller 50 may adjust the delay to place the notch in the ripple rejection response of the pseudo-envelope follower power management system 10 MA as function of the transmit to receive duplex offset for each band of operation in which the linear RF power amplifier 22 is configured to be used. Accordingly, as discussed above, the controller 50 may be configured to programmatically change the values of the programmable filter parameter(s), programmable gain parameter(s), and programmable delay parameter(s) to obtain an optimized notch depth, a notch width, and a notch frequency of the notch in the ripple rejection response of the embodiments of the pseudo-envelope follower power management system 10 MA, depicted in FIG. 23A and FIG. 23C , and the pseudo-envelope follower power management system 10 MB, depicted in FIG. 23B and FIG. 23D , as a function of the transmit to receive duplex offset for each band of operation for which the linear RF power amplifier 22 is configured to be used.

FIG. 25 depicts three example ripple rejection responses of an embodiment of the pseudo-envelope follower power management system similar to the pseudo-envelope follower power management system 10 MA and the pseudo-envelope follower power management system 10 MB, depicted in FIGS. 23A-D , where the desired maximum ripple rejection response is near 30 MHz.

The first ripple rejection response depicted in FIG. 25 may be obtained by the controller 50 configuring the programmable delay circuitry 432 to provide a first programmable delay period substantially equal to DELAY 1 in order to temporally align the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , to provide a maximum ripple rejection response near 30 MHz. The second ripple rejection response depicted in FIG. 25 may be obtained by the controller 50 configuring the programmable delay circuitry 432 to provide a second programmable delay period substantially equal to DELAY 2 , where DELAY 2 >DELAY 1 . This results in the second ripple rejection response having a maximum ripple rejection response at a frequency less than the desired 30 MHz and the depth of the notch in the ripple rejection response is reduced. The third ripple rejection response depicted in FIG. 25 may be obtained by the controller 50 configuring the programmable delay circuitry 432 to provide a third programmable delay period substantially equal to DELAY 3 , where DELAY 1 >DELAY 3 . This results in the third ripple rejection response having a maximum ripple rejection response at a frequency greater than the desired 30 MHz and locates the notch in the ripple rejection response at a frequency that is higher than the desired 30 MHZ. As depicted in FIG. 25 , the controller 50 may configure the programmable delay provided by the programmable delay circuitry 432 to locate the notch in the ripple rejection response of the pseudo-envelope follower power management systems 10 MA and 10 MB at or near the receive duplex offset for each band of operation for which the linear RF power amplifier 22 is configured to be used.

FIG. 26 depicts an embodiment of the high pass filter circuitry 430 that may include a first high pass filter circuit 435 A and a second high pass filter circuit 435 B. The first high pass filter circuit 435 A may have a first corner frequency, f C1 , which is determined by the first high pass filter time constant, τ C1 . The second high pass filter circuit 435 B may have a second corner frequency, f- C2 , which is determined by the second high pass filter time constant, τ C2 . Accordingly, the combined transfer function of the first high pass filter circuit 435 A and the second high pass filter circuit 435 B may provide a first high pass filter response and a second high pass filter response, where the first high pass filter response corresponds to a first corner frequency, f C1 , and the second high pass filter response corresponds to a second corner frequency, f C2 . The combined transfer function of the first high pass filter circuit 435 A and the second high pass filter circuit 435 B, H HP (s), may be represented by the Laplace transfer function shown in equation (5) as follows:

The first high pass filter time constant, τ C1 and the second high pass filter time constant, τ C2 , may be independently set such that the first corner frequency, f C1 , does not equal the second corner frequency, f C2 . For example, the first high pass filter time constant, τ C1 , may be configured by the controller 50 (not shown) such that the first corner frequency, f C1 , has a range between 3M Hz and 11.5 MHz. In some embodiments, the first corner frequency, f C1 , may have a range between 3 MHz and 3 MHz. Similarly, the controller may configure the second high pass filter time constant, τ C2 , such that the second corner frequency, f C2 , has a range between 3 MHz and 11.5 MHz. In some embodiments, the second corner frequency, f C2 , may have a range between 3 MHz and 8 MHz.

In some embodiments of the high pass filter circuitry 430 , the first corner frequency, f C1 , of the first high pass filter circuit 435 A and the second corner frequency, f C2 , of the second high pass filter circuit 435 B are each set to be approximately 6 MHz. In some embodiments, the controller 50 (not shown) may configure the first high pass filter time constant, τ C1 , and the second high pass filter time constant, τ C2 . For example, the first high pass filter time constant, τ C1 , may be configured by the controller 50 (not shown) such that the first corner frequency, f C1 , has a range between 3 MHz and 11.5 MHz. In some embodiments, the first corner frequency, f C1 , may have a range between 3 MHz and 11.5 MHz. In still other embodiments the first corner frequency, f C1 , and the second corner frequency, f C2 , may be configured to be substantially the same. For example, the first corner frequency, f C1 , may be configured to be around 6 MHz, and the second corner frequency, f C2 , may be configured to be around 6 MHz. In some embodiments, the first corner frequency, f C1 , and the second corner frequency, f C2 , are configured by the controller 50 as a function of the bandwidth of the receive channel frequency band associated with each band of operation.

›DETAILED DESCRIPTION · 66 of 67

Returning to FIG. 24 , assuming that the high pass filter circuitry 430 includes both the first high pass filter circuit 435 A and the second high pass filter circuit 435 B, the desired Laplace transfer function for the high frequency ripple compensation current 416 , I COR , provided at the Gm assist I COR output 426 B of the Gm assist circuit 426 is shown in equation (6) as follows:

I COR ⁡ ( s ) = ( V RAMP - V SW_OUT ⁢ _EST ) L POWER_INDUCTOR ⁢ s ⁢ τ C ⁢ ⁢ 1 ⁢ s 1 + τ C ⁢ ⁢ 1 ⁢ s ⁢ τ C ⁢ ⁢ 2 ⁢ s 1 + τ C ⁢ ⁢ 2 ⁢ s ( 6 )

where V RAMP represents the future value of the power amplifier supply voltage, V CC , the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , represents the future value of the switching voltage, V SW , at the switching voltage output 26 based on the operational state of the switcher control circuit (not shown) of the switch mode power supply converter 420 , and L POWER — INDUCTOR represents the inductance of the power inductor 16 . In some embodiments of the open loop ripple compensation assist circuit 414 A, the inductance of the power inductor 16 may be represented by the estimated power inductor inductance parameter, L EST , discussed above with reference to the open loop assist circuit 39 , depicted in FIG. 2A and FIG. 2B , where the estimated power inductor inductance parameter, L EST , may be either the measured or estimated inductance of the power inductor 16 between a specific range of frequencies. For example, the estimated power inductor inductance parameter, L EST , may be either the measured or estimated inductance of the power inductor 16 between approximately 10 MHz and 30 MHz. As another example, the estimated power inductor inductance parameter, L EST , may be either the measured or estimated inductance of the power inductor 16 within a band of frequencies near or within operational bandwidth of the linear RF power amplifier 22 . In this case, the Laplace transfer function for the high frequency ripple compensation current 416 , I COR , provided by the Gm assist circuit 426 may be given by equation (7) as follows:

I COR ⁡ ( s ) = ( V RAMP - V SW_OUT ⁢ _EST ) L EST ⁢ τ C ⁢ ⁢ 1 1 + τ C ⁢ ⁢ 1 ⁢ s ⁢ τ C ⁢ ⁢ 2 ⁢ s 1 + τ C ⁢ ⁢ 2 ⁢ s ( 7 )

As shown in equation (7), the Laplace transfer function for the high frequency ripple compensation current 416 includes a low pass filter having a low pass time constant, τ C1 , and a high pass filter having a high pass time, τ C2 .

FIG. 27A depicts another embodiment of the open loop ripple compensation assist circuit 414 B which is similar to the open loop ripple compensation assist circuit 414 depicted in FIGS. 23A-D . For the sake of brevity, and not by way of limitation, the switch mode power supply converter 420 and circuitry associated with generation of the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , depicted in FIG. 24 , are not depicted in FIG. 27A . Also, while controller 50 is not depicted in FIG. 27A , it will be understood that as depicted in FIGS. 23A-D , controller 50 (not shown) may configure the various elements of the open loop ripple compensation assist circuit 414 B depicted in FIG. 27A .

The open loop ripple compensation assist circuit 414 B includes combined filter and gain assist circuitry 422 B, a filter network 436 , and a feedback network 438 . The combined filter and gain assist circuitry 422 B includes operational amplifier circuitry 440 A having an operational amplifier 442 , a Gm bias circuit 444 , and an operational amplifier output isolation circuit 446 .

The operational amplifier 442 includes a non-inverting input 442 A, an inverting input 442 B, and an operational amplifier output 442 C. The operational amplifier 442 may include a first operational amplifier push-pull output stage circuit (not shown) that generates the operational amplifier output 442 C. The non-inverting input 442 A of the operational amplifier 442 is configured to receive the V RAMP signal. The operational amplifier output 442 C may be configured to source an operational amplifier output current, I AMP , to produce an operational amplifier output voltage, V AMP , across the Gm bias circuit 444 .

In addition, the operational amplifier 442 may be further configured to generate or provide the high frequency ripple compensation current 416 , I COR , and the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE . As an example, the operational amplifier 442 may further include a second operational amplifier push-pull output stage circuit (not shown) configured to generate the high frequency ripple compensation current 416 , I COR . In addition, as another example, the operational amplifier 442 may further include a third operational amplifier push-pull output stage circuit (not shown) configured to generate the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE .

In some embodiments of the operational amplifier 442 , the high frequency ripple compensation current 416 , I COR , generated by the second operational amplifier output state circuit may be substantially a mirrored current of the operational amplifier output current, I AMP , provided by the first operational amplifier push-pull output stage circuit (not shown). Similarly, in some embodiments of the operational amplifier 442 , the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , may be a mirrored current of the operational amplifier output current, I AMP , provided by the first operational amplifier push-pull output stage circuit (not shown).

In the cases where the high frequency ripple compensation current 416 , I COR , and the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE , are related to the operational amplifier output current, I AMP , by a current mirroring arrangement, the relative dimensional relationships of the channel widths of the respective transistor elements may be used to implement the first operational amplifier push-pull output stage circuit (not shown), the second operational amplifier push-pull output stage circuit (not shown), and the third operational amplifier push-pull output stage circuit (not shown), may be configured to relate the magnitudes of the operational amplifier output current, I AMP , to the magnitudes of the high frequency ripple compensation current 416 , I COR , and the scaled high frequency ripple compensation current estimate 418 , I COR — SENSE .

›DETAILED DESCRIPTION · 67 of 67

The operational amplifier output isolation circuit 446 includes a follower NFET 448 , NFET FOLLOWER , and an I BIAS — FOLLOWER current source 450 . The drain of the follower NFET 448 , NFET FOLLOWER , is coupled to a circuit supply voltage, V DD . The gate of the follower NFET 448 , NFET FOLLOWER , provides a high impedance input of the operational amplifier output isolation circuit 446 , and is coupled to the operational amplifier output 442 C. As a result, the gate voltage at the gate of the follower NFET 448 , NFET FOLLOWER is equal to the operational amplifier output voltage, V AMP . The follower NFET 448 , NFET FOLLOWER , may be configured such that the input gate impedance of the follower NFET 448 , NFET FOLLOWER , is very high relative to other impedances coupled to the operational amplifier output 442 C in the operational frequency range of the open loop ripple compensation assist circuit 414 B. As a result, the gate current, I GATE , flowing into the gate of the follower NFET 448 , NFET FOLLOWER , approaches zero. The source of the follower NFET 448 , NFET FOLLOWER , is coupled to the first node 450 A of the I BIAS — FOLLOWER current source 450 . The second node 450 B of the I BIAS — FOLLOWER current source 450 is coupled to ground. The I BIAS — FOLLOWER current source 450 may be configured to sink an NFET FOLLOWER bias current, I BIAS — FOLLOWER , to provide a bias current for the follower NFET 448 , NFET FOLLOWER . The gate-to-source voltage of the follower NFET 448 , NFET FOLLOWER , is V GS — NFET — FOLLOWER . The source voltage on the source of the follower NFET 448 , NFET FOLLOWER , is the feedback voltage, V e , where V e =V AMP −V GS — NFET — FOLLOWER . Thus, from a small signal modeling perspective, the follower NFET 448 , NFET FOLLOWER , effectively isolates the feedback voltage, V e , from the operational amplifier output 442 C. As a result, the operational amplifier circuitry 440 A includes an isolated feedback node 451 at the node created at the connection of the source of the follower NFET 448 , NFET FOLLOWER , and the first node 450 A of the I BIAS — FOLLOWER current source 450 . The isolated feedback node 451 provides the feedback voltage, V e , to the feedback network 438 .

The feedback network 438 may be coupled between the inverting input 442 B of the operational amplifier 442 and the isolated feedback node 451 to provide the feedback path for the feedback current 456 , I FEEDBACK . The inverting input 442 B of the operational amplifier 442 is also coupled to the delayed I COR estimated switching voltage output 38 C, V SW — EST — DELAY — ICOR , via the filter network 436 , as depicted in FIG. 27A . The filter network 436 includes a filter resistor 458 coupled in series with a filter capacitor 460 . The filter resistor 458 may have a filter resistance substantially equal to R 1 . The filter capacitor 460 may have a filter capacitance substantially equal to C 1 . The feedback network 438 may include a feedback resistor 462 coupled in parallel with a feedback capacitor 464 . The feedback resistor 462 may have a feedback resistance substantially equal to R 2 . The feedback capacitor 464 may have a feedback capacitance substantially equal to C 2 . In some embodiments, the filter resistor 458 and/or the feedback resistor 462 may be configured to be programmable by the controller 50 (not shown). For example, the filter resistor 458 and/or the feedback resistor 462 may be a binary weighted resistor array configured to be controlled by the controller 50 . As an example, the filter resistor 458 and/or the feedback resistor 462 may each be implemented as a resistor array including switches that may be programmed to be open or closed by the controller 50 (not shown). As a result, the controller 50 may selectively set the resistance value of the filter resistance, R 1 of the filter resistor 458 , and the resistance value of the feedback resistance, R 2 , of the feedback resistor 462 , to change the frequency response of the open loop ripple compensation assist circuit 414 B. In a similar fashion, or in addition to, in some embodiments, the filter capacitor 460 and/or the feedback capacitor 464 may each be implemented as a capacitor array that may be configured by the controller 50 . For example, the filter capacitor 460 and/or the feedback capacitor 464 may be a binary weighted capacitor array configured to be controlled by the controller 50 . The effective capacitance of the capacitor array may be configured by the controller 50 by selectively switching in and out different capacitors in each respective capacitor array. As a result, in some embodiments, the controller 50 may be configured to selectively set the capacitance value of the filter capacitance, C 1 , of the filter capacitor 460 and the capacitance value of the feedback capacitance, C 2 , of the feedback capacitor 464 , to change the frequency response of the open loop ripple compensation assist circuit 414 B.

In addition, in some embodiments of the open loop ripple compensation assist circuit 414 B, the filter resistance, R 1 , of the filter resistor 458 , the feedback resistance, R 2 , of the feedback resistor 462 , the filter capacitance, C 1 , of the filter capacitor 460 , and the feedback capacitance, C 2 , of the feedback capacitor 464 , are independently programmable by the controller 50 .

Alternatively, in some embodiments, the capacitance value of the filter capacitance, C 1 , of the filter capacitor 460 may be a fixed value. Similarly, in some embodiments, the feedback capacitance, C 2 , of the feedback capacitor 464 may be a fixed value. Likewise, in other embodiments, the resistance value of the filter resistance, R 1 , of the filter resistor 458 may be a fixed value and/or the resistance value of the feedback resistance, R 2 , of the feedback resistor 462 may be a fixed value. Moreover, in some embodiments, different combinations of the filter resistance, R 1 the feedback resistance, R 2 , the filter capacitance, C 1 , and the feedback capacitance, C 2 , of the respective filter resistor 458 , the filter capacitor 460 , the feedback resistor 462 , and the feedback capacitor 464 may have either fixed value

›Tables in the description — 6

TABLE 1 — μC CHARGE PUMP

	OPERATIONAL	OUTPUT VOLTAGE,
MODE OF	RATIO OF μC	(V μC — OUT ), GENERATED
OPERATION OF μC	CHARGE PUMP,	AT μC CHARGE
CHARGE PUMP	(μBB RATIO )	PUMP OUTPUT
OFF Mode	OFF	FLOATING
1 X V BAT Mode	1	1 X V BAT
4/3 X V BAT Mode	4/3	4/3 X V BAT
3/2 X V BAT Mode	3/2	3/2 X V BAT

TABLE 2 — OPERATIONAL RATIO OF μC CHARGE PUMP, (μBB RATIO )

SWITCHES	OFF	1	4/3	3/2
SW 1	OPEN	OPEN	PHASE 1	OPEN
SW 2	OPEN	OPEN	PHASE 2	PHASE 1
SW 3	OPEN	OPEN	PHASE 3	PHASE 2
SW 4	OPEN	OPEN	PHASE 3	PHASE 2
SW 5	OPEN	OPEN	PHASE 1	PHASE 1
SW 6	OPEN	OPEN	PHASE 2	OPEN
SW 7	OPEN	OPEN	OPEN	OPEN
SW 8	OPEN	OPEN	OPEN	PHASE 1
SW 9	OPEN	PHASE 1	OPEN	OPEN

TABLE 3 — μC CHARGE PUMP

	OPERATIONAL	OUTPUT VOLTAGE,
OPERATIONAL	RATIO OF μC	(V μC — OUT ), GENERATED
MODES OF μC	CHARGE PUMP,	AT μC CHARGE
CHARGE PUMP	(μBB RATIO )	PUMP OUTPUT
OFF Mode	OFF	FLOATING
1/4 X V BAT Mode	1/4	1/4 X V BAT
1/3 X V BAT Mode	1/3	1/3 X V BAT
1/2 X V BAT Mode	1/2	1/2 X V BAT
2/3 X V BAT Mode	2/3	2/3 X V BAT
1 X V BAT Mode	1	1 X V BAT
4/3 X V BAT Mode	4/3	4/3 X V BAT
3/2 X V BAT Mode	3/2	3/2 X V BAT

TABLE 4 — OPERATIONAL RATIO OF μC CHARGE PUMP, (μBB RATIO )

SWITCHES	OFF	¼	⅓	½	⅔	1	4/3	3/2
SW 1	OPEN	PHASE 1	PHASE 1	PHASE 1	PHASE 1	PHASE 1	PHASE 1	PHASE 1
						(CLOSED)
SW 2	OPEN	OPEN	PHASE 2	PHASE 2	PHASE 2	PHASE 1	PHASE 2	PHASE 2
						(CLOSED)
SW 3	OPEN	PHASE 3	PHASE 2	PHASE 2	OPEN	OPEN	OPEN	OPEN
SW 4	OPEN	OPEN	OPEN	PHASE 1	PHASE 1	PHASE 1	OPEN	OPEN
						(CLOSED)
SW 5	OPEN	PHASE 1	PHASE 1	OPEN	PHASE 2	OPEN	PHASE 1	PHASE 1
SW 6	OPEN	OPEN	OPEN	PHASE 1	PHASE 1	PHASE 1	PHASE 2	OPEN
						(CLOSED)
SW 7	OPEN	PHASE 2	PHASE 2	PHASE 2	OPEN	PHASE 1	PHASE 3	PHASE 2
						(CLOSED)
SW 8	OPEN	PHASE 2	PHASE 2	PHASE 2	PHASE 2	OPEN)	PHASE 1	PHASE 1
SW 9	OPEN	PHASE 1 & PHASE 3	PHASE 1	PHASE 1	PHASE 1	PHASE 1	OPEN	OPEN
						(CLOSED)
SW 10	OPEN	PHASE 3	OPEN	OPEN	OPEN	OPEN	OPEN	OPEN
SW 11	OPEN	OPEN	OPEN	OPEN	OPEN	PHASE 1	OPEN	PHASE 2
						(CLOSED)
SW 12	OPEN	OPEN	OPEN	OPEN	OPEN	PHASE 1	PHASE 3	PHASE 2
						(CLOSED)
SW 13	OPEN	OPEN	OPEN	OPEN	OPEN	OPEN	PHASE 2	OPEN

R	0
=
L	EST
τ
C	⁢
⁢	1
=
L	EST
R	1
⁢	C

I	BIAS_REF
=
V	DD
-
	V	DD	2
R	3
=
V	DD
2	×
R	3
(	17	)

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Classifications

5 codes

IPC · International Patent Classification

Section H — Electricity

H03G3/00

USPC · US Patent Classification

330/127323/222455/127.1330/297

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