Gate driving circuit and display panel having the same

This application claims priority from and the benefit of Korean Patent Application No. 10-2011-0066245 filed in the Korean Intellectual Property Office on Jul. 5, 2011, which is incorporated herein by reference for all purposes as if fully set forth herein.

1. Field of the Invention

A display panel is provided.

2. Discussion of the Background

A display device includes multiple pairs of field generating electrodes and an electro-optical active layer interposed therebetween. Such display device may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display, and the like. The liquid crystal display may include a liquid crystal layer as the electro-optical active is layer and the organic light emitting diode display may include an organic emission layer as the electro-optical active layer. Generally, one of a pair of field generating electrodes is connected to a switching element to receive an electric signal and the electro-optical active layer converts the electric signal into an optical signal to display images.

The display device typically includes a gate driver and a data driver. The gate driver applies to a gate line a gate signal that turns a pixel on or off and the data driver converts image data into a data voltage and then applies the converted data voltage to a data line.

The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.

An exemplary embodiment of the present invention provides a display panel including: a display area; and a gate driver to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage to respectively apply a first gate voltage and a second gate voltage to the display area, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, the first stage is discharges the first gate voltage based on the first clock signal and a first transfer signal, and the second stage outputs the first transfer signal based on the second clock bar signal.

Another exemplary embodiment of the present invention provides a display panel including: a display area; and a gate driver configured to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a plurality of stages configured to respectively apply a gate voltage to the display area, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, and the plurality of stages comprise a first stage configured to receive the first clock signal and output a first transfer signal, and a second stage configured to receive the second clock signal and outputting a second transfer signal.

Yet another exemplary embodiment of the present invention provides a display panel including: a display area; and a gate driver comprising a driving transistor configured to output a gate voltage to the display area, wherein a first clock signal and a first clock bar signal have opposite phases to each other, a second clock signal and a second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock signal, the driving transistor receives the first clock signal, and a control terminal of the driving transistor is discharged by the second clock bar signal.

Yet another exemplary embodiment of the present invention provides a method for driving a display panel including: receiving a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal; applying, by a first stage, a first gate voltage to a first gate line; applying, by a second stage, a second gate voltage to a second gate line; is outputting a first transfer signal from the second stage based on the second clock bar signal; and discharging the first gate voltage on the first gate line based on the first clock signal and the first transfer signal, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, and the second clock bar signal has phases later than the first clock bar signal.

It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.

FIG. 1 is a plan view of a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram to show a gate driver and its gate lines according to an exemplary embodiment of the present invention in detail.

FIG. 3 is a waveform diagram of a clock signal according to an exemplary embodiment of the present invention.

FIG. 4 is an enlarged circuit diagram to show a stage according to an exemplary embodiment of the present invention.

FIG. 5 is an enlarged circuit diagram to show a stage according to an exemplary is embodiment of the present invention.

FIG. 6A is a signal waveform diagram of a Q node and gate voltage according to the exemplary embodiment of the present invention and FIG. 6B is a signal waveform diagram of a Q node and gate voltage according to a comparative example.

FIG. 7 is a signal waveform diagram of gate voltage according to an exemplary embodiment of the present invention and a comparative example.

FIG. 8 is a signal waveform diagram of gate voltage according to an exemplary embodiment of the present invention and a comparative example.

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope of the invention to those skilled in the art.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present. In contrast, It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “beneath” another element, it can be directly beneath the other element or intervening elements may also be present. Meanwhile, when an element is referred to as being “directly beneath” another element, there are no intervening elements present.

FIG. 1 is a plan view of a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a display panel 100 according to an exemplary embodiment of the present invention may include a display area 300 to display images, a gate driver 500 to apply gate voltages to gate lines G 1 to Gn, and data driver ICs 460 each to apply a data voltage to one of the data lines D 1 to Dm. Each data driver IC 460 may be disposed on a flexible printed circuit film (FPC) 450 attached to the display panel 100 . The gate driver 500 and the data driver IC 460 may be controlled by a signal controller 600 . A printed circuit board (PCB) may be formed outside the flexible printed circuit film 450 to transfer signals from the signal controller 600 to the data driver IC 460 and the gate driver 500 . Signals provided from the signal controller 600 may include signals such as clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 , a scan start signal STVP, and signals to provide low voltages Vss 1 and Vss 2 each having predetermined levels.

Hereinafter, an exemplary embodiment will be described with respect to a liquid crystal panel as the display panel, but the display panel is not limited to the liquid crystal panel and may be an organic light emitting panel, a plasma display panel, an electrophoretic display panel, and the like. The display area 300 in the liquid crystal panel may include a thin film transistor Trsw, a liquid crystal capacitor Clc, and a storage capacitor Cst. The display area 300 in the organic light emitting panel may include a thin film transistor and an organic light emitting diode. The display area 300 in other display panels may include elements such as a thin film transistor and the like.

The display area 300 may include a pixel, gate lines G 1 to Gn, and data lines D 1 to Dm. The gate lines G 1 to Gn and the data lines D 1 to Dm are insulated from each other while crossing each other.

The pixel may include a thin film transistor Trsw, a liquid crystal capacitor Clc, and a storage capacitor Cst. The storage capacitor Cst may be omitted. A control terminal of the thin film transistor Trsw may be connected to a gate line, an input terminal of the thin film transistor Trsw may be connected to a data line, and an output terminal of the thin film transistor Trsw may be connected to a terminal of the liquid crystal capacitor Clc and a terminal of the storage capacitor Cst. Another terminal of the liquid crystal capacitor Clc may be connected to a common electrode, and another terminal of the storage capacitor Cst may receive a storage voltage Vcst applied from the signal controller 600 .

Each of the data lines D 1 to Dm may receive a data voltage from one of the data driver ICs 460 , and each of the gate lines G 1 to Gn may receive a gate voltage from the gate driver 500 .

Each of the data driver IC 460 may be disposed above or below the display panel 100 . The data driver ICs 460 may be connected to the data lines D 1 to Dm respectively, which extend in a column direction.

The gate driver 500 may receive the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 , the scan start signal STVP, the first low voltage Vss 1 , and the second low voltage Vss 2 to generate gate voltages and applies gate-on voltages to the gate lines G 1 to Gn in sequence. The first low voltage Vss 1 may be a gate-off voltage and the second low voltage may be a voltage lower than the gate-off voltage. The gate voltage may be the gate-on voltage or the gate-off voltage.

Signal lines applying the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 , the scan start signal STVP, the first low voltage Vss 1 , and the second low voltage Vss 2 to the gate driver 500 may be disposed outside the display area 300 . The clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 , the scan start signal STVP, the first low voltage Vss 1 , and the second low voltage Vss 2 may be transferred to the flexible printed circuit film 450 from outside or the signal controller 600 through the printed circuit board 400 .

FIG. 2 is a block diagram to show the gate driver and its gate lines according to an exemplary embodiment of the present invention in detail.

As shown in FIG. 2 , the display area 300 may be represented as a resistor Rp and a capacitor Cp for a gate line. The gate lines G 1 to Gn, the liquid crystal capacitor Clc, and the storage capacitor Cst may be represented by the resistor Rp and the capacitor Cp. The gate voltage outputted from a stage SR may be transferred through one of the gate lines G 1 to Gn.

The gate driver 500 may include a plurality of stages SR 1 , SR 2 , SR 3 , SR 4 , and SR 5 which are connected in cascade. Each of the stages SR 1 , SR 2 , SR 3 , SR 4 , and SR 5 may include first to third input terminals IN 1 , IN 2 , and IN 3 , a clock input terminal CK, two voltage input terminals Vin 1 and Vin 2 , a gate voltage output terminal OUT to output the gate voltage, and a transfer signal output terminal CRout. Each of the stages SR 1 , SR 2 , SR 3 , SR 4 , and SR 5 may include a transistor and the transistor may include amorphous silicon, an oxide semiconductor, and the like. The oxide semiconductor may comprise an oxide material including at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and hafnium (Hf). For example, the oxide semiconductor may include GIZO (here, G is gallium, I is indium, Z is zinc, and O is oxygen), XIZO (here, X is hafnium, I is indium, Z is zinc, and O is oxygen), and the like.

The gate driver 500 may further include a dummy stage. The gate voltages outputted from normal stages SR 1 , SR 2 , SR 3 , SR 4 , and SR 5 may be transferred to the gate lines, and data voltages may be applied to the pixel to display images. The dummy stage (not shown) may not be connected to a gate line. Although the dummy stage may be connected to a gate line, the dummy stage may be connected to a gate line of a dummy pixel (not shown) which does not display the images, such that the images will not be displayed.

Each of the first to the third input terminals IN 1 , IN 2 , and IN 3 of a stage may receive a transfer signal outputted from another stage.

A transfer signal of the (n−2)-th stage may be inputted to the first input terminal IN 1 of the n-th stage (herein, n is an integer). For example, the transfer signal outputted from the output terminal CRout of the first stage SR 1 may be inputted to the first input terminal IN 1 of the third stage SR 3 , the transfer signal outputted from the output terminal CRout of the second stage SR 2 may be inputted to the first input terminal IN 1 of the fourth stage SR 4 , and the transfer signal of outputted from the output terminal CRout of the third stage SR 3 may be inputted to the first input terminal IN 1 of the fifth stage SR 5 . However, the scan start signal STVP may be inputted to the first input terminal IN 1 of the first stage SR 1 and the first input terminal IN 1 of the second stage SR 2 .

The transfer signal of the (n+3)-th stage may be inputted the second input terminal IN 2 of the n-th stage (here, n is an integer). For example, the transfer signal outputted from the output terminal CRout of the fourth stage SR 4 may be inputted to the second input terminal IN 2 of the first stage SR 1 , the transfer signal outputted from the output terminal CRout of the fifth stage SR 5 may be inputted to the second input terminal IN 2 of the second stage SR 2 , the transfer signal of the sixth stage SR 6 may be inputted to the second input terminal IN 2 of the is third stage SR 3 , the transfer signal of the seventh stage SR 7 may be inputted to the second input terminal IN 2 of the fourth stage SR 4 , and the transfer signal of the eighth stage SR 8 may be inputted to the second input terminal IN 2 of the fifth stage SR 5 .

The transfer signal of the (n+4)-th stage may be inputted to the third input terminal IN 3 of the n-th stage (here, n is an integer). For example, the transfer signal of the fifth stage SR 5 may be inputted to the third input terminal IN 3 of the first stage SR 1 , the transfer signal of the sixth stage SR 6 may be inputted to the third input terminal IN 3 of the second stage SR 2 , the transfer signal of the seventh stage SR 7 may be inputted to the third input terminal IN 3 of the third stage SR 3 , the transfer signal of the eighth stage SR 8 may be inputted to the third input terminal IN 3 of the fourth stage SR 4 , and the transfer signal of the ninth stage SR 9 may be inputted to the third input terminal IN 3 of the fifth stage SR 5 .

The clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 may be applied to the clock input terminals CKs of a plurality of stages. The first clock signal CKV 1 may be inputted to the clock terminal of the (4n−3)-th stage, the first clock bar signal CKVB 1 may be inputted to the clock terminal of the (4n−1)-th stage, the second clock signal CKV 2 may be inputted to the clock terminal of the (4n−2)-th stage, and the second clock bar signal CKVB 2 may be inputted to the clock terminal of the 4n-th stage (here, n is an integer). The first clock signal CKV 1 and the first clock bar signal CKVB 1 have phases opposite to each other and the second clock signal CKV 2 and the second clock bar signal CKVB 2 have phases opposite to each other.

The first low voltage Vss 1 may be applied to the first voltage input terminal Vin 1 of the plurality of stages, and the second low voltage Vss 2 may be applied to the second voltage input terminal Vin 2 of the plurality of stages. For example, the first low voltage Vss 1 may be −5 V and the second low voltage Vss 2 may be −10 V, but the low voltages are not particularly is limited thereto.

A stage may receive one of the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 , the first low voltage Vss 1 , and the second low voltage Vss 2 to output a gate voltage to its corresponding gate line and transfer the transfer signal to another stage. The first stage SR 1 and the second stage SR 2 may also receive the scan start signal STVP.

For example, after receiving the first clock signal CKV 1 provided from outside through the clock input terminal CK, the scan start signal STVP through the first input terminal IN 1 , the first and the second low voltages Vss 1 and Vss 2 through the first and the second voltage input terminals Vin 1 and Vin 2 , and the transfer signals provided from each of the fourth stage SR 4 and the fifth stage SR 5 through the second and the third input terminals IN 2 and IN 3 , the first stage SR 1 may output the gate voltage to the first gate line G 1 through the gate voltage output terminal OUT. The first stage SR 1 may output the transfer signal from the transfer signal output terminal CRout and then, may transfer the outputted transfer signal to the first input terminal IN 1 of the third stage SR 3 .

After receiving the second clock signal CKV 2 provided from outside through the clock input terminal CK, the scan start signal STVP through the first input terminal IN 1 , the first and the second low voltages Vss 1 and Vss 2 through the first and the second voltage input terminals Vin 1 and Vin 2 , and the transfer signals provided from each of the fifth stage SR 5 and the sixth stage SR 6 through the second and the third input terminals IN 2 and IN 3 , the second stage SR 2 may output the gate voltage to the second gate line G 2 through the gate voltage output terminal OUT. The second stage SR 2 may output the transfer signal from the transfer signal output terminal CRout to transfer the outputted transfer signal to the first input terminal IN 1 of the fourth stage SR 4 .

After receiving the first clock bar signal CKVB 1 provided from outside through the clock input terminal CK, the transfer signal provided from the first stage SR 1 through the first input terminal IN 1 , the first and the second low voltages Vss 1 and Vss 2 through the first and the second voltage input terminals Vin 1 and Vin 2 , and the transfer signals provided from each of the sixth stage SR 6 and the seventh stage SR 7 through the second and the third input terminals IN 2 and IN 3 , the third stage SR 3 may output the gate voltage to the third gate line G 3 through the gate voltage output terminal OUT. The third stage SR 3 may output the transfer signal from the transfer signal output terminal CRout to transfer the outputted transfer signal to the first input terminal IN 1 of the fifth stage SR 5 .

After receiving the second clock bar signal CKVB 2 provided from outside through the clock input terminal CK, the transfer signal provided from the second stage SR 2 through the first input terminal IN 1 , the first and the second low voltages Vss 1 and Vss 2 through the first and the second voltage input terminals Vin 1 and Vin 2 , and the transfer signals provided from each of the seventh stage SR 7 and the eighth stage SR 8 through the second and the third input terminals IN 2 and IN 3 , the fourth stage SR 4 may output the gate voltage to the fourth gate line G 4 through the gate voltage output terminal OUT. The fourth stage SR 4 may output the transfer signal from the transfer signal output terminal CRout to transfer the outputted transfer signal to the first input terminal IN 1 of the sixth stage SR 6 and the second input terminal IN 2 of the first stage SR 1 .

After receiving the first clock signal CKV 1 provided from outside through the clock input terminal CK, the transfer signal provided from the third stage SR 3 through the first input terminal IN 1 , the first and the second low voltages Vss 1 and Vss 2 through the first and the second voltage input terminals Vin 1 and Vin 2 , and the transfer signals provided from each of the is eighth stage SR 8 and the ninth stage SR 9 through the second and the third input terminals IN 2 and IN 3 , the fifth stage SR 5 may output the gate voltage to the fifth gate line G 5 through the gate voltage output terminal OUT. The fifth stage SR 5 may output the transfer signal from the transfer signal output terminal CRout to transfer the outputted transfer signal to the first input terminal IN 1 of the seventh stage SR 7 , the second input terminal IN 2 of the second stage SR 1 , and the third input terminal IN 3 of the first stage SR 1 .

FIG. 3 is a waveform diagram of a clock signal according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , an on-pulse of the second clock signal CKV 2 may be applied later than an on-pulse of the first clock signal CKV 1 and an on-pulse of the second clock bar signal CKVB 2 may be applied later than an on-pulse of the first clock bar signal CKVB 1 . In other words, a rising time of the second clock signal CKV 2 may be later than a rising time of the first clock signal CKV 1 and a rising time of the second clock bar signal CKVB 2 may be later than a rising time of the first clock bar signal CKVB 1 . Since the stage receiving the first clock signal CKV 1 receives the transfer signal from the stage driven by the second clock bar signal CKVB 2 , as compared with receiving the transfer signal from the stage driven by the first clock bar signal CKVB 1 , a falling characteristic of the gate-on voltage applied to the gate line may be improved and an accurate data voltage may be applied to the pixel. The first clock signal CKV 1 and the first clock bar signal CKVB 1 have phases opposite to each other and the second clock signal CKV 2 and the second clock bar signal CKVB 2 have phases opposite to each other.

For example, when a period of the first clock signal CKV 1 and the first clock bar signal CKVB 1 is referred to as T, the on-pulse of the second clock signal CKV 2 may be applied later than the on-pulse of the first clock signal CKV 1 by T/4 and the on-pulse of the second clock is bar signal CKVB 2 may be applied later than the on-pulse of the first clock bar signal CKVB 1 by T/4.

FIG. 4 is an enlarged circuit diagram to show a stage according to an exemplary embodiment of the present invention, and FIG. 5 is an enlarged circuit diagram to show a stage according to an exemplary embodiment of the present invention.

As shown in FIGS. 4 and 5 , a stage SR of the gate driver 500 may include an input unit 511 , a pull-up driving unit 512 , a transfer signal generating unit 513 , an output unit 514 , and a pull-down driving unit 515 .

The input unit 511 may include a fourth transistor Tr 4 and an input terminal, and a control terminal of the fourth transistor Tr 4 may be common-connected (diode-connected) to the first input terminal IN 1 . An output terminal of the fourth transistor Tr 4 may be connected to a Q contact point (hereinafter, also called a first node). When a high level voltage is applied to the first input terminal IN 1 , the input unit 511 transfers the high level voltage to the Q contact point.

The pull-up driving unit 512 may include a seventh transistor Tr 7 and a twelfth transistor Tr 12 . A control terminal and an input terminal of the twelfth transistor Tr 12 may be common-connected to each other to receive one of the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 through the clock input terminal CK. An output terminal of the twelfth transistor Tr 12 may be connected to a control terminal of the seventh transistor Tr 7 and the pull-down driving unit 515 . An input terminal of the seventh transistor Tr 7 may also be connected to the clock input terminal CK, and an output terminal thereof may be connected to a Q′ contact point (hereinafter, also called a second node) and the pull-down driving unit 515 . A control terminal of the seventh transistor Tr 7 may be connected to the output terminal of the twelfth transistor Tr 12 and the pull-down driving unit 515 . A parasite capacitor (not shown) may be formed between the input terminal and the control terminal and between the control terminal and the output terminal of the seventh transistor Tr 7 , respectively. When a high level signal is applied from the clock input terminal CK, the pull-up driving unit 512 transfers the high level signal to the control terminal of the seventh transistor Tr 7 and the pull-down driving unit 515 through the twelfth transistor Tr 12 . Since the high level signal transferred to the seventh transistor Tr 7 turns on the seventh transistor Tr 7 , the high level signal applied from the clock input terminal CK may be applied to the Q′ contact point.

The transfer signal generating unit 513 may include a fifteenth transistor Tr 15 . An input terminal of the fifteenth transistor Tr 15 may be connected to the clock input terminal CK and one of the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 may be inputted to the input terminal of the fifteenth transistor Tr 15 . A control terminal of the fifteenth transistor Tr 15 may be connected to the Q contact point corresponding to the output of the input unit 511 and an output terminal of the fifteenth transistor Tr 15 may be connected to the transfer signal output terminal CRout to output the transfer signal. A parasite capacitor (not shown) may be formed between the control terminal and the output terminal of the fifteenth transistor Tr 15 . The output terminal of the fifteenth transistor Tr 15 may be connected to the pull-down driving unit 515 to receive the second low voltage Vss 2 . Accordingly, the voltage of the low level transfer signal may be the second low voltage Vss 2 .

The output unit 514 may include a first transistor Tr 1 and a first capacitor C 1 . The first transistor Tr 1 is also called a driving transistor. A control terminal of the first transistor Tr 1 may be connected to the Q contact point and an input terminal of the first transistor Tr 1 may receive one of the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 through the clock input is terminal CK. An output terminal of the first transistor Tr 1 may be connected to the gate voltage output terminal OUT. The first capacitor C 1 may be formed between the control terminal and the output terminal of the first transistor Tr 1 and the output terminal may be connected with the gate voltage output terminal OUT. The output terminal of the first transistor Tr 1 may also be connected to the pull-down driving unit 515 to receive the first low voltage Vss 1 . Accordingly, the voltage of the gate-off voltage may be the first low voltage Vss 1 . The output unit 514 may output the gate voltage according to the voltage on the Q contact point and one of the clock signals CKV 1 , CKVB 1 , CKV 2 , and CKVB 2 . The first transistor Tr 1 may receive the first clock signal CKV 1 , and the control terminal of the first transistor Tr 1 may be discharged by the second clock bar signal CKVB 2 . Therefore, a falling characteristic of the gate-on voltage applied to the gate line may be improved and an accurate data voltage may be applied to the pixel.

The pull-down driving unit 515 may remove charges on the stage SR, such that the gate-off voltage and the low level voltage of the transfer signal may be smoothly outputted. For example, the pull-down driving unit 515 may lower a potential of the Q contact point, a potential of the Q′ contact point, the voltage outputted to the transfer signal, and the voltage outputted to the gate line. The pull-down driving unit 515 may include a second transistor Tr 2 , a third transistor Tr 3 , a fifth transistor Tr 5 , a sixth transistor Tr 6 , an eighth transistor Tr 8 to an eleventh transistor Tr 11 , a thirteenth transistor Tr 13 , and a sixteenth transistor Tr 16 .

The transistors pulling-down the Q contact point in the pull-down driving unit 515 are the sixth transistor Tr 6 , the ninth transistor Tr 9 , the tenth transistor Tr 10 , and the sixteenth transistor Tr 16 .

A control terminal of the sixth transistor Tr 6 may be connected to the third input terminal IN 3 , an output terminal of the sixth transistor Tr 6 may be connected to the second is voltage input terminal Vin 2 , and an input terminal of the sixth transistor Tr 6 may be connected to the Q contact point. Accordingly, the sixth transistor Tr 6 may be turned-on according to the transfer signal applied through the third input terminal IN 3 , so as to lower the voltage of the Q contact point to the second low voltage Vss 2 .

The ninth transistor Tr 9 and the sixteenth transistor Tr 16 operate together to pull-down the Q contact point. A control terminal of the ninth transistor Tr 9 may be connected to the second input terminal IN 2 , an input terminal of the ninth transistor Tr 9 may be connected to the Q contact point, and an output terminal of the ninth transistor Tr 9 may be connected to an input terminal and a control terminal of the sixteenth transistor Tr 16 . The control terminal and the input terminal of the sixteenth transistor Tr 16 may be common-connected (diode-connected) with the output terminal of the ninth transistor Tr 9 . The sixteenth transistor Tr 16 is a diode-connected transistor and slows down the discharge of the control terminal of the first transistor. An output terminal of the sixteenth transistor Tr 16 may be connected to the second voltage input terminal Vin 2 . Accordingly, the ninth transistor Tr 9 and the sixteenth transistor Tr 16 may be turned-on according to the transfer signal applied through the second input terminal IN 2 so as to lower the voltage of the Q contact point to the second low voltage Vss 2 .

As shown in FIG. 5 , the diode connected sixteenth transistor Tr 16 may be omitted. In other words, the output terminal of the ninth transistor Tr 9 may be directly connected to the second voltage input terminal Vin 2 . In the case where the sixteenth transistor Tr 16 includes an oxide semiconductor, as compared with amorphous silicon, a current characteristic of the sixteenth transistor Tr 16 may be improved, such that the capacity of lowering the voltage of the Q contact point to the second low voltage Vss 2 may be reduced and as a result, the role of the sixteenth transistor Tr 16 may be diminished. Accordingly, the is sixteenth transistor Tr 16 may be omitted in the stage SR, such that an area of the gate driver 500 may be reduced and the utilization of the display area 300 may be increased.

An input terminal of the tenth transistor Tr 10 may be connected to the Q contact point, an output terminal of the tenth transistor Tr 10 may be connected to the second voltage input terminal Vin 2 , and a control terminal of the tenth transistor Tr 10 may be connected to the Q′ contact point (also called an inverse terminal because the Q′ contact point has an opposite phase to the voltage of the Q contact point). Accordingly, in a normal period where the Q′ contact point has the high level voltage, the tenth transistor Tr 10 continuously pulls down the voltage of the Q contact point to the second low voltage Vss 2 and, only in a period where the Q′ contact point has the low level voltage, the tenth transistor Tr 10 does not pull down the voltage of the Q contact point. When the voltage of the Q contact point is not pulled down, the corresponding stage outputs the gate-on voltage and the transfer signal.

The transistors pulling-down the Q′ contact point in the pull-down driving unit 515 are the fifth transistor Tr 5 , the eighth transistor Tr 8 , and the thirteenth transistor Tr 13 .

A control terminal of the fifth transistor Tr 5 may be connected to the first input terminal IN 1 , an input terminal of the fifth transistor Tr 5 may be connected to the Q′ contact point, and an output terminal of the fifth transistor Tr 5 may be connected to the second voltage input terminal Vin 2 . Accordingly, the fifth transistor Tr 5 may lower the voltage of the Q′ contact point to the second low voltage Vss 2 according to the transfer signal inputted through the first input terminal IN 1 .

A control terminal of the eighth transistor Tr 8 may be connected to the transfer signal output terminal CRout of a current terminal stage, an input terminal of the eighth transistor Tr 8 may be connected to the Q′ contact point, and an output terminal of the eighth transistor Tr 8 is may be connected to the second voltage input terminal Vin 2 . Accordingly, the eighth transistor Tr 8 may lower the voltage of the Q′ contact point to the second low voltage Vss 2 according to the transfer signal of the current terminal stage.

A control terminal of the thirteenth transistor Tr 13 may be connected to the transfer signal output terminal CRout of the current terminal stage, an input terminal of the thirteenth transistor Tr 13 may be connected to the output terminal of the twelfth transistor Tr 12 of the pull-up driving unit 512 , and an output terminal of the thirteenth transistor Tr 13 may be connected to the second voltage input terminal Vin 2 . Accordingly, the thirteenth transistor Tr 13 may lower a potential in the pull-up driving unit 512 to the second low voltage Vss 2 according to the transfer signal of the current terminal stage and also lower the voltage of the Q′ contact point connected to the pull-up driving unit 512 to the second low voltage Vss 2 . The thirteenth transistor Tr 13 may discharge the internal charge of the pull-up driving unit 512 to the second low voltage Vss 2 , but since the pull-up driving unit 512 is connected to the Q′ contact point, the thirteenth transistor Tr 13 may not pull-up the voltage of the Q′ contact point and may indirectly lower the voltage of the Q′ contact point to the second low voltage Vss 2 .

The eleventh transistor Tr 11 may lower the voltage outputted as the transfer signal in the pull-down driving unit 515 . A control terminal of the eleventh transistor Tr 11 may be connected to the Q′ contact point, an input terminal of the eleventh transistor Tr 11 may be connected to the transfer signal output terminal CRout, and an output terminal of the eleventh transistor Tr 11 may be connected to the second voltage input terminal Vin 2 . Accordingly, when the voltage of the Q′ contact point is a high level, the eleventh transistor Tr 11 may lower the voltage of the transfer signal output terminal CRout to the second low voltage Vss 2 and the transfer signal may be changed to a low level.

The second transistor Tr 2 and the third transistor Tr 3 may lower the voltage outputted to the gate line in the pull-down driving unit 515 . The second transistor Tr 2 may include a control terminal connected to the second input terminal IN 2 , an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin 1 . Accordingly, when the transfer signal inputted through the second input terminal IN 2 is outputted, the second transistor Tr 2 may change the outputted gate voltage to the first low voltage Vss 1 .

The third transistor Tr 3 may include a control terminal connected to the Q′ contact point, an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin 1 . Accordingly, when the voltage of the Q′ contact point is a high-level, the third transistor Tr 3 may change the outputted gate voltage to the first low voltage Vss 1 .

The pull-down driving unit 515 may lower the voltage of the gate voltage output terminal OUT to the first low voltage Vss 1 and lower the voltages of the Q contact point, the Q′ contact point, and the transfer signal output terminal CRout to the second low voltage Vss 2 lower than the first low voltage Vss 1 . Accordingly, the gate-on voltage and the high-level voltage of the transfer signal may have substantially the same voltage as each other and the gate-off voltage and the low-level voltage of the transfer signal may have different values. The gate-off voltage may be the first low voltage Vss 1 and the low-level voltage of the transfer signal may be the second low voltage Vss 2 .

For example, the gate-on voltage may be 25 V, the gate-off voltage and the first low voltage Vss 1 may be −5 V, the high-level voltage of the transfer signal may be 25 V, and the low-level voltage of the transfer signal and the second low voltage Vss 2 may be −10 V.

The transfer signal generating unit 513 and the output unit 514 may operate by the voltage of the Q contact point, such that the stage SR outputs the high-level voltage of the transfer signal and the gate-on voltage. By the transfer signals inputted through the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3 , the high-level voltage of the transfer signal may be lowered to the second low voltage Vss 2 and the gate-on voltage may be lowered to the first low voltage Vss 1 to be changed to the gate-off voltage. The stage SR may lower the voltage of the Q contact point to the second low voltage Vss 2 by the transfer signal, such that power consumption of the stage SR may be reduced. In addition, since the second low voltage Vss 2 may be lower than the first low voltage Vss 1 as the gate-off voltage, although the voltage of the transfer signal applied in another stage may be changed due to a ripple, a noise, and the like, the value of the second low voltage Vss 2 may be sufficiently lowered and as a result, a leakage current of the transistors included in the stage SR may be reduced, such that the power consumption of the stage SR may be reduced.

FIG. 6A is a signal waveform diagram of a Q node and a gate voltage according to an exemplary embodiment of the present invention, and FIG. 6B is a signal waveform diagram of a Q node and a gate voltage according to a comparative example.

The gate driver according to an exemplary embodiment of the present invention may include, as shown in FIG. 2 , a stage receiving the first clock signal CKV 1 that receives the transfer signal from a stage driven by the second clock bar signal CKVB 2 , and a stage SR including a sixteenth transistor Tr 16 as shown in FIG. 4 . The gate driver shows a signal waveform diagram as shown in FIG. 6A . A gate driver of a comparative example includes a stage receiving the first clock signal CKV 1 that receives the transfer signal from a stage driven by the first clock bar signal CKVB 1 , and the stage SR including the sixteenth transistor as shown is in FIG. 4 . A gate driver of the comparative example shows a signal waveform diagram as shown in FIG. 6B . Both the gate driver according to the exemplary embodiment of the present invention and the gate driver of the comparative example may include amorphous silicon. The on-pulse of the second clock bar signal CKVB 2 may be applied later than the on-pulse of the first clock bar signal CKVB 1 , such that a discharging speed of the Q contact point may be decreased and a turn-on time of the first transistor Tr 1 may be increased. Accordingly, the gate voltage output terminal OUT may use the second transistor Tr 2 for the discharge of the gate voltage and the low-level voltage of the first clock signal CKV 1 for the discharge of the gate voltage through the first transistor Tr 1 , thereby reducing a falling time of the gate-on voltage. For example, since a falling time of the gate-on voltage in the gate driver of the comparative example is about 24 μsec and a falling time of the gate-on voltage in the gate driver according to an exemplary embodiment of the present invention is about 4 μsec, the falling time of the gate-on voltage may be decreased by about ⅙ and a falling characteristic of the gate-on voltage may be improved by about six times.

FIG. 7 is a signal waveform diagram of gate voltage according to an exemplary embodiment of the present invention and the comparative example.

According to a structure of the proposed gate driver, the stage that receives the first clock signal CKV 1 may receive the transfer signal from the stage driven by the second clock bar signal CKVB 2 as shown in FIG. 2 , and the proposed gate may include a stage SR without the sixteenth transistor Tr 16 as shown in FIG. 5 . In a gate driver of the comparative example, the stage that receives the first clock signal CKV 1 receives the transfer signal from the stage driven by the first clock bar signal CKVB 1 , and includes the stage SR including the sixteenth transistor as shown in FIG. 4 . Both the proposed gate driver and the gate driver of the comparative is example include amorphous silicon. The on-pulse of the second clock bar signal CKVB 2 may be applied later than the on-pulse of the first clock bar signal CKVB 1 , such that the falling time of the gate-on voltage may be lowered. The sixteenth transistor Tr 16 may be omitted in the stage SR, such that an area of the gate driver 500 may be decreased and the utilization of the display area 300 may be increased. For example, the sixteenth transistor Tr 16 may be omitted, such that the area of the gate driver 500 may be decreased by about 9% based on a panel of 18.5 inches.

FIG. 8 is a signal waveform diagram of gate voltage according to the exemplary embodiment of the present invention and the comparative example.

According to a structure of the proposed gate driver, the stage that receives the first clock signal CKV 1 may receive the transfer signal from the stage driven by the second clock bar signal CKVB 2 as shown in FIG. 2 , and may include the stage SR without the sixteenth transistor Tr 16 as shown in FIG. 5 . A gate driver of a comparative example receives the transfer signal from the stage driven by the first clock bar signal CKVB 1 at the stage thereof receiving the first clock signal CKV 1 and may include the stage SR including the sixteenth transistor as shown in FIG. 4 . Both the proposed gate driver and the gate driver of the comparative example may include GIZO which is an oxide semiconductor. The on-pulse of the second clock bar signal CKVB 2 may be applied later than the on-pulse of the first clock bar signal CKVB 1 , such that a falling time of the gate-on voltage may be lowered. In addition, a falling characteristic of the gate-on voltage of the proposed gate driver including the oxide semiconductor in FIG. 8 may be more improved than a falling characteristic of the gate-on voltage of the gate driver of the comparative example including amorphous silicon in FIG. 7 . The sixteenth transistor Tr 16 may be omitted in the stage SR, such that an area of the gate driver 500 may be decreased and the utilization of the display area 300 may be increased.

According to exemplary embodiments of the present invention, a falling characteristic of gate-on voltage of the gate driver may be improved, accurate data voltages may be applied to a pixel, an area of the gate driver may decrease, and the utilization of the display area may increase.

While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.