Bridgeless PFC converter and the method thereof

This application claims priority to and the benefit of Chinese Patent Application No. 201010578957.6, filed Dec. 2, 2010, which is incorporated herein by reference in its entirety.

The present invention relates generally to electronic circuit, and more particularly but not exclusively to electronic circuit with PFC (Power Factor Corrector) control.

The utility power is AC (alternating voltage and alternating current), while the power consumed by most electrical and electronic equipment is DC (direct voltage and direct current), hence there is need for an AC-to-DC power conversion. A suitable controlled PFC (Power Factor Correction) converter forces an input AC current wave shape to be sinusoidal, in phase, and proportional with input AC voltage thus resulting in desirable low harmonic content and maximum available real power drawn from the AC line.

FIG. 1 schematically shows a prior art PFC converter 50 . which comprises a full bridge rectifier and a boost converter. The full bridge rectifier comprises diodes D 1 ˜D 4 . The boost converter comprises an inductor L, a switch S, a diode D 5 and an output capacitor C coupled as shown. FIG. 1 shows the typical topology of the PFC converter which is known to persons of ordinary skill in the art. The control circuit which keeps an input current in phase with an input voltage is not shown. The boost converter supplies power to a load R. The full bridge rectifier folds an AC line voltage into a uni-directional voltage and folds an AC line current into a uni-directional current. The boost converter converts the uni-directional voltage into a DC output voltage and converts the uni-directional current into a DC output current.

In addition to boost converter losses, the input alternating current passes through the two diodes of the full bridge rectifier for either positive or negative portion of AC cycle in the PFC converter 50 . The diode is inefficient and will result in the high conduction loss.

So there is a need to solve the above problems.

It is an object of the present disclosure to provide a bridgeless PFC (power factor correction) converter and the method thereof.

In accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present disclosure, a bridgeless PFC converter, comprising: a first input terminal and a second input terminal configured to receive an input AC signal; an output terminal configured to provide an output signal; an inductor set comprising N inductors, wherein each inductor has a first terminal and a second terminal, and the first terminal of each inductor is coupled to the first input terminal; an output stage comprising (N+1) switching circuits coupled between the output terminal and a ground node, wherein a first switching circuit comprises a first switch and a second switch, and wherein the first switch and the second switch are coupled in series, and the conjunction of the switches in the first switching circuit is coupled to the second input terminal, and wherein each of the remaining switching circuits respectively comprises a bottom switch and a top switch, and wherein each conjunction of the switches in the remaining switching circuits is respectively coupled to the second terminal of the respective N inductors; and an output capacitor coupled between the output terminal and the ground node; wherein: N is a natural number, and wherein N≧1.

In accomplishing the above and other objects, there has been provided, in accordance with another embodiment of the present disclosure, a bridgeless PFC (power factor correction) converter, comprising: a first input terminal and a second input terminal configured to receive an input AC signal; an output terminal configured to provide an output signal to a load; an inductor having a first terminal and a second terminal, wherein the first terminal is coupled to the first input terminal; an output stage comprising a first switching circuit and a second switching circuit coupled between the output terminal and a ground node, wherein the first switching circuit comprises a first switch and a second switch, and wherein the conjunction of the first switch and the second switch is coupled to the second input terminal, and the second switching circuit comprises a bottom switch and a top switch, and wherein the conjunction of the bottom switch and the top switch is coupled to the second terminal of the inductor; and an output capacitor coupled between the output terminal and the ground node.

Furthermore, there has been provided, in accordance with an embodiment of the present disclosure, a method of control a bridgeless PFC converter, wherein the bridgeless PFC converter comprises a first input terminal and a second input terminal configured to receive an input AC signal; an output terminal configured to provide an output signal; an inductor set comprising N inductors, wherein each inductor has a first terminal and a second terminal, and the first terminal of each inductor is coupled to the first input terminal; an output stage comprising (N+1) switching circuits coupled between the output terminal and a ground node, wherein a first switching circuit comprises a first switch and a second switch, and wherein the first switch and the second switch are series coupled, and the conjunction of the switches in the first switching circuit is coupled to the second input terminal, and wherein each of the remaining switching circuits respectively comprises a bottom switch and a top switch, and wherein each conjunction of the switches in the remaining switching circuits are respectively coupled to the second terminal of the respective N inductors; an output capacitor coupled between the output terminal and the ground node; and wherein: N is a natural number and N≧1; the method comprising: during when the input AC signal is positive, keeping the first switch ON, keeping the second switch OFF, and turning ON and OFF the top switches and the bottom switches alternatively; and during when the input AC signal is negative, keeping the first switch OFF, keeping the second switch ON, and turning ON and OFF the top switches and the bottom switches alternatively.

FIG. 1 schematically shows a prior art PFC converter 50 .

FIG. 2 schematically shows a bridgeless PFC converter 100 in accordance with an embodiment of the present disclosure.

FIG. 3 shows the waveforms of the current i L flowing through the inductor L, the control signal of the switches S 1 , S 3 , S 4 and the drain-source voltage of the switch S 3 .

FIG. 4 shows the state of the bridgeless PFC converter 100 in subinterval t 0 ˜t 1 of FIG. 3 .

FIG. 5 shows the state of the bridgeless PFC converter 100 in subinterval t 1 ˜t 2 of FIG. 3 .

FIG. 6 shows the state of the bridgeless PFC converter 100 in subinterval t 2 ˜t 3 of FIG. 3 .

FIG. 7 shows the state of the bridgeless PFC converter 100 in subinterval t 3 ˜t 4 of FIG. 3 .

FIG. 8 shows the state of the bridgeless PFC converter 100 in subinterval t 4 ˜t 5 of FIG. 3 .

FIG. 9 shows the waveforms of the current i L flowing through the inductor L, the control signal of the switches S 2 , S 3 , S 4 and the drain-source voltage of the switch S 4 .

FIG. 10 shows the state of the bridgeless PFC converter 100 in subinterval t 0 ˜t 1 of FIG. 9 .

FIG. 11 shows the state of the bridgeless PFC converter 100 in subinterval t 1 ˜t 2 of FIG. 9 .

FIG. 12 shows the state of the bridgeless PFC converter 100 in subinterval t 2 ˜t 3 of FIG. 9 .

FIG. 13 shows the state of the bridgeless PFC converter 100 in subinterval t 3 ˜t 4 of FIG. 9 .

FIG. 14 shows the state of the bridgeless PFC converter 100 in subinterval t 4 ˜t 5 of FIG. 9 .

FIG. 15 shows the waveforms of the input AC signal Vin, the current i L flowing through the inductor L, the control signal of the switches S 1 ˜S 4 .

FIG. 16 schematically shows a bridgeless PFC converter 200 in accordance with an embodiment of the present disclosure.

FIG. 17 schematically shows a bridgeless PFC converter 300 in accordance with an embodiment of the present disclosure.

The use of the same reference label in different drawings indicates the same of like components.

In the present disclosure, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

FIG. 2 schematically shows a bridgeless PFC converter 100 in accordance with an embodiment of the present disclosure. The bridgeless PFC converter 100 comprises: a first input terminal (A) and a second input terminal (B) configured to receive an input AC signal; an output terminal (OUT) configured to provide an output signal Vo to a load R; an inductor L having a first terminal and a second terminal, wherein the first terminal is coupled to the first input terminal (A); an output stage comprising a first switching circuit 101 and a second switching circuit 102 coupled between the output terminal (OUT) and a ground node, wherein the first switching circuit 101 comprises a first switch S 1 and a second switch S 2 , and wherein the conjunction of the first switch S 1 and the second switch S 2 is coupled to the second input terminal (B), and the second switching circuit 102 comprises a bottom switch S 3 and a top switch S 4 , and wherein the conjunction of the bottom switch S 3 and the top switch S 4 is coupled to the second terminal of the inductor L; and an output capacitor Co coupled between the output terminal (OUT) and the ground node.

In one embodiment, the first switch S 1 and the second switch S 2 in the first switching circuit 101 work with low frequency and are alternatively turned ON for half of the AC cycle. The bottom switch S 3 and the top switch S 4 in the second switching circuit 102 work with high frequency. In one embodiment, the first and second switches work with the same frequency with the input AC signal; and the top switch and the bottom switch in the second switching circuit work with the same frequency of the PFC converter.

Persons of ordinary skill in the art should know that the switches S 1 ˜S 4 comprise semiconductor switches, for example, N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), P-type MOSFET or other semiconductor devices. In one embodiment, the switches in the switching circuits comprise N-type MOSFET. The MOSFET may have a body-diode parallel coupled with it as shown in FIG. 2 . Persons of ordinary skill in the art should know that the body-diode is the parasitic diode of the switch. An extra diode could be coupled with the switch if necessary.

In one embodiment, the switches in the switching circuits are turned ON by a logical high control signal, and are turned OFF by a logical low control signal.

Below we will explain separately first the operation from the positive input AC signal and then the operation from the negative input AC signal.

FIG. 3 shows the waveforms of signals in FIG. 2 . The operation from the positive input AC signal is described with respect to FIGS. 2 and 3 . In FIG. 3 , i L is a current flowing through the inductor L; G S1 , G S3 and G S4 are respective control signals of the first switch S 1 , the bottom switch S 3 and the top switch S 4 ; and V dsS3 is the drain-source voltage of the bottom switch S 3 .

At the beginning, when the voltage at the first terminal A is higher than the voltage at the second terminal B, the first switch S 1 is turned ON and the second switch S 2 is turned OFF. The states of the first switch S 1 and the second switch S 2 maintain until the voltage at the first terminal A goes lower than the voltage at the second terminal B. The bottom switch S 3 is turned ON after the top switch S 4 is turned OFF. The current i L flowing through the inductor L positively increases. When the current i L reaches a peak limit i limit , the bottom switch S 3 is turned OFF and the top switch S 4 is turned ON, then the current i L flowing through the inductor L positively decreases. When the current i L crosses zero from positive to negative, after a first delay time T DELAY1 , the top switch S 4 is turned OFF and the bottom switch S 3 is turned ON again, and the operation repeats.

In one embodiment, the bottom switch S 3 and the top switch S 4 are turned ON and OFF alternatively. There is a first dead time T D1 between the OFF of the bottom switch S 3 and the ON of the top switch S 4 , and there is a second dead time T D2 between the OFF of the top switch S 4 and the ON of the bottom switch S 3 . The switching circuits are coupled between input AC signal and the ground node. Persons of ordinary skill in the art should know that the dead times are added to avoid the large current from power to ground in case that the switches in each switching circuit are both ON in a instant.

The operation from the positive input AC signal is described in detailed with respect to FIGS. 4 to 8 .

FIG. 4 shows the state of the bridgeless PFC converter 100 in subinterval t 0 ˜t 1 . In FIG. 4 , the top switch S 4 is turned OFF. The bottom switch S 3 is still in the OFF state because of the second dead time T D2 . The body-diode of the bottom switch S 3 conducts. The input AC current i ac is flowing in the direction shown in FIG. 4 . The current i L flowing through the inductor L increases. The drain-source voltage V dsS4 of the top switch S 4 is a reverse biased voltage of the body-diode which is approximately equal to zero.

FIG. 5 shows the state of the bridgeless PFC converter 100 in subinterval t 1 ˜t 2 . As shown in FIG. 3 , at time t 1 , the second dead time T D2 ends. The bottom switch S 3 is turned ON. The top switch S 4 keeps OFF. The input AC current i ac is flowing in the direction shown in FIG. 5 . The current i L flowing through the inductor L increases. The drain-source voltage V asS3 of the bottom switch S 3 is approximately equal to zero at time t 1 as described above, so the bottom switch S 3 is turned ON with zero drain-source voltage. The zero-voltage-switching (ZVS) is realized.

FIG. 6 shows the state of the bridgeless PFC converter 100 in subinterval t 2 ˜t 3 . As shown in FIG. 3 , the current i L flowing through the inductor L reaches the peak limit l limit at time t 2 . Then the bottom switch S 3 is turned OFF. The top switch S 4 is still OFF because of the first dead time T D1 . The body-diode of the top switch S 4 conducts. The input AC current i ac is flowing in the direction shown in FIG. 6 . The current i L flowing through the inductor L positively decreases. The drain-source voltage V dsS4 is the reverse biased voltage of the body-diode of the top switch S 4 , and the drain-source voltage V dsS4 of the top switch S 4 is approximately equal to zero.

FIG. 7 shows the state of the bridgeless PFC converter 100 in subinterval t 3 ˜t 4 . As shown in FIG. 3 , the first dead time T D1 ends at time t 3 . The top switch S 4 is turned ON. The bottom switch S 3 is turned OFF. The input AC current i ac is flowing in the direction shown in FIG. 7 . The current i L flowing through the inductor L decreases. The drain-source voltage V dsS4 of the top switch S 4 is approximately equal to zero at time t 3 as described above, so the top switch S 4 is turned ON with zero drain-source voltage. The zero-voltage switching (ZVS) is realized.

FIG. 8 shows the state of the bridgeless PFC converter 100 in subinterval t 4 ˜t 5 . As shown in FIG. 3 , the current i L flowing through the inductor L crosses zero at time t 4 . The bottom switch S 3 keeps OFF. The top switch S 4 keeps ON for a first delay time T DELAY1 . The input AC current i ac is flowing in the direction shown in FIG. 8 . The current i L flowing through the inductor L negatively increases.

At time t 5 , the first delay time T DELAY1 ends. The top switch S 4 is turned OFF. The bottom switch S 3 is still OFF because of the second dead time T D2 . The first switch S 1 keeps ON and the second switch S 2 keeps OFF. The body-diode of the bottom switch S 3 conducts. The current i L flowing through the inductor L negatively decreases. The input AC current i ac is flowing in the direction shown in FIG. 4 . The operation of the bridgeless PFC converter 100 in time t 5 is similar to the operation in time t 0 .

In FIG. 3 , the time periods of the subinterval t 2 ˜t 3 and the subinterval t 4 ˜t 6 are extended for clearly illustration purpose. Persons of ordinary skill in the art should know that the subinterval t 2 ˜t 3 represents the first dead time T D1 , and the subinterval t 4 ˜t 6 represents the first delay time T DELAy1 and the second dead time T D2 . In real application, the subinterval t 2 ˜t 3 and the subinterval t 4 ˜t 6 are much shorter than the subinterval t 1 ˜t 2 and the subinterval t 3 ˜t 4 .

FIG. 9 shows the waveforms of signals in FIG. 2 . The operation from the negative input AC signal is described with respect to FIGS. 2 and 9 . In FIG. 9 , i L is current flowing through the inductor L; G S2 , G S3 and G S4 are the respective control signals of the second switch S 2 , the bottom switch S 3 and the top switch S 4 ; and V dsS4 is the drain-source voltage of the top switch S 4 .

At the beginning of the negative portion of the input AC signal, when the voltage at the first terminal (A) is lower than the voltage at the second terminal (B), the first switch S 1 is turned OFF and the second switch S 2 is turned ON. The states of the first switch S 1 and the second switch S 2 maintain until the voltage at the first terminal (A) is higher than the voltage at the second terminal (B). The top switch S 4 is turned ON after the bottom switch S 3 is turned OFF. The current i L flowing through the inductor L negatively increases. When the current i L reaches the peak limit l limit , the top switch S 4 is turned OFF and the bottom switch S 3 is turned ON, then the current i L flowing through the inductor L negatively decreases. When the current i L crosses zero from negative to positive, after a second delay time T DELAY2 , the bottom switch S 3 is turned OFF and the top switch S 4 is turned ON, then the operation repeats.

In one embodiment, the bottom switch S 3 and the top switch S 4 are turned ON and OFF alternatively. There is a third dead time T D3 between the OFF of the top switch S 4 and the ON of the bottom switch S 3 , and there is a fourth dead time T D4 between the OFF of the bottom switch S 3 and the ON of the top switch S 4 .

The operation from the negative input AC signal is described detailed in respect to FIGS. 10 to 14 .

FIG. 10 shows the state of the bridgeless PFC converter 100 in subinterval t 0 ˜t 1 of FIG. 9 . As shown in FIG. 10 , the bottom switch S 3 is turned OFF. The top switch S 4 is in the OFF state because of the fourth dead time T D4 . The body-diode of the top switch S 4 conducts. The input AC current i ac is flowing in the direction shown in FIG. 10 . The current i L flowing through the inductor L positively decreases. The drain-source voltage V dsS4 is the reverse biased voltage of the body-diode which is approximately equal to zero.

FIG. 11 shows the state of the bridgeless PFC converter 100 in subinterval t 1 ˜t 2 of FIG. 9 . As shown in FIG. 9 , at time t 1 , the fourth dead time T D4 ends. The top switch S 4 is turned ON. The bottom switch S 3 keeps OFF. The input AC current i ac is flowing in the direction shown in FIG. 11 . The current i L flowing through the inductor L negatively increases. The drain-source voltage V dsS4 of the top switch S 4 is approximately equal to zero at time t 1 as described before, so the top switch S 4 is turned ON with zero drain-source voltage. The zero-voltage-switching (ZVS) is realized.

FIG. 12 shows the state of the bridgeless PFC converter 100 in subinterval t 2 ˜t 3 of FIG. 9 . As shown in FIG. 9 , the current i L flowing through the inductor L reaches the peak limit l limit at time t 2 . Then the top switch S 4 is turned OFF. The bottom switch S 3 is still OFF because of the third dead time T D3 . The body-diode of the top switch S 3 conducts. The input AC current i ac is flowing in the direction shown in FIG. 12 . The current i L flowing through the inductor L negatively decreases. The drain-source voltage V dsS3 is the reverse biased voltage of the body-diode which is approximately equal to zero.

FIG. 13 shows the state of the bridgeless PFC converter 100 in subinterval t 3 ˜t 4 of FIG. 9 . As shown in FIG. 9 , the third dead time T D3 ends at time t 3 . The bottom switch S 3 is turned ON. The top switch S 4 is OFF. The second switch S 2 keeps ON and the first switch S 1 keeps OFF. The input AC current i ac is flowing in the direction shown in FIG. 13 . The current i L flowing through the inductor L negatively decreases. The drain-source voltage V dsS3 of the bottom switch S 3 is approximately equal to zero at time t 3 as described before, so the bottom switch S 3 is turned ON with zero drain-source voltage. The zero-voltage-switching (ZVS) is realized.

FIG. 14 shows the state of the bridgeless PFC converter 100 in subinterval t 4 ˜t 5 of FIG. 9 . As shown in FIG. 9 , at time t 4 , the current i L flowing through the inductor L crosses zero. The bottom switch S 3 keeps OFF. The top switch S 4 keeps ON for a second delay time T DELAY2 because of the propagation delay of the system. The input AC current i ac is flowing in the direction shown in FIG. 14 . The current i L flowing through the inductor L positively increases.

At time t 5 , the propagation delay T DELAY2 ends. The bottom switch S 3 is turned OFF. The top switch S 4 is still OFF because of the fourth dead time T D4 . The second switch S 2 keeps ON and the first switch S 1 keeps OFF. The body-diode of the top switch S 4 conducts. The current i L flowing through the inductor L positively decreases. The input AC current i ac is flowing in the direction shown in FIG. 10 . The operation of the bridgeless PFC converter 100 in time t 5 is similar to the operation in time t 0 .

In FIG. 9 , the time periods of the subinterval t 2 ˜t 3 and the subinterval t 4 ˜t 6 are extended for clearly illustration purpose. Persons of ordinary skill in the art should know that the subinterval t 2 ˜t 3 represents the third dead time T D3 , the subinterval t 4 ˜t 6 represents the second delay time T DELAY2 and the fourth dead time T D4 , and in real application, the subinterval t 2 ˜t 3 and the subinterval t 4 ˜t 6 are much shorter than the time period t 1 ˜t 2 and the time period t 3 ˜t 4 .

As seen from the above description, there are only two switches conducting at the same time. Such that the conduction loss is saved and the efficiency is improved.

FIG. 15 shows the waveforms of the input AC signal Vin, the current i L flowing through the inductor L, the control signal of the switches S 1 ˜S 4 . The peak current limit l limit is a sinusoidal waveform which is similar to the input AC signal Vin despite their magnitude. When the input AC signal crosses zero, the first switch S 1 and the second switch S 2 are both turned OFF to avoid that the voltage across the capacitor C decreases sharply because of the unexpected ON of the first switch S 1 and the second switch S 2 . Thus when the input AC signal crosses zero from positive to negative, a fifth dead time T D5 is inserted between the OFF of the first switch S 1 and the ON of the second switch S 2 . When the input AC signal crosses zero from negative to positive, a sixth dead time T D6 is inserted between the OFF of the second switch S 2 and the ON of the first switch S 1 . Meanwhile, the bottom switch S 3 and the top switch S 4 are turned OFF too in the dead times T D5 and T D6 . In one embodiment, the fifth dead time T D5 is equal to the sixth dead time T D6 .

Persons of ordinary skill in the art should know that the delay times are caused by propagation delay of the system. The value of every delay time is determined by the real application of the circuit.

FIG. 16 schematically shows a bridgeless PFC converter 200 in accordance with an embodiment of the present disclosure. The bridgeless PFC converter 200 comprises: a first input terminal (A) and a second input terminal (B) configured to receive an input AC signal; an output terminal configured to provide an output signal Vo; a first inductor L 1 and a second inductor L 2 , wherein each inductor L 1 has a first terminal and a second terminal, and the first terminal of each inductor is coupled to the first input terminal (A); an output stage comprising three switching circuits coupled between the output terminal and a ground node, wherein a first switching circuit 201 comprises a first switch S 1 and a second switch S 2 coupled in series, and the conjunction of the switches in the first switching circuit is coupled to the second input terminal (B), the second switching circuit 202 comprises a bottom switch S 3 and a top switch S 4 coupled in series, the conjunction of the switches is coupled to the second terminal of the first inductor L 1 , and the third switching circuit 203 comprises a bottom switch S 5 and a top switch S 6 coupled in series, the conjunction of the switches is coupled to the second terminal of the second inductor L 2 ; and an output capacitor Co coupled between the output terminal and the ground node. In one embodiment, the bridgeless PFC converter further comprises a load R parallel coupled to the capacitor Co.

The first switch S 1 and the second switch S 2 in the first switching circuit 201 work with low frequency and are alternatively turned ON for half AC cycle. The bottom switches S 3 and S 5 , and the top switches S 4 and S 6 in the other switching circuits work with high frequency. In one embodiment, the first and second switches work with the same frequency of the input AC signal; and the top switches and the bottom switches in the other switching circuits work with the same frequency of the PFC converter.

Persons of ordinary skill in the art should know that the switches S 1 ˜S 6 comprise semiconductor switches, for example, N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), P-type MOSFET or other semiconductor devices. In one embodiment, the switches in the switching circuits comprise N-type MOSFET. The MOSFET may have a body-diode parallel coupled with it as shown in FIG. 16 . Persons of ordinary skill in the art should know that the body-diode may be the parasitic diode of the switch. An extra diode could be coupled with the switch if necessary.

In one embodiment, the switches in the switching circuits are turned ON by logical high control signals, and are turned OFF by logical low control signals.

The operation from the positive input AC signal is described below.

At the beginning, when the voltage at the first terminal (A) is higher than the voltage at the second terminal (B), the first switch S 1 is turned ON and the second switch S 2 is turned OFF. The bottom switch S 3 is turned ON after the top switch S 4 is turned OFF. The current i L1 flowing through the inductor L positively increases. When the current i L1 reaches a peak limit, the bottom switch S 3 is turned OFF and the top switch S 4 is turned ON. The current i L1 flowing through the first inductor L 1 positively decreases. When the current i L1 crosses zero from positive to negative, after a first delay time T DELAY1 , the top switch S 4 is turned OFF and the bottom switch S 3 is turned ON, and the operation repeats. The top switch S 6 and the bottom switch S 5 operates similarly to the operation of the top switch S 4 and the bottom switch S 3 in the mean time. The bottom switch S 5 is turned ON after the top switch S 6 is turned OFF. The current i L2 flowing through the second inductor L 2 positively increases. When the current i L2 reaches a peak limit, the bottom switch S 5 is turned OFF and the top switch S 6 is turned ON, and the current i L2 flowing through the inductor L 2 positively decreases. A third delay time T DELAY3 later after the current i L2 crosses zero from positive to negative, the top switch S 6 is turned OFF and the bottom switch S 5 is turned ON, and the operation repeats.

The operation from the negative input AC signal is described below.

At the beginning, when the voltage at the first terminal A is lower than the voltage at the second terminal B, the second switch S 2 is turned ON and the first switch S 1 is turned OFF. The top switch S 4 is turned ON after the bottom switch S 3 is turned OFF. The current i L1 flowing through the inductor L 1 negatively increases. When the current i L1 reaches a peak limit, the top switch S 4 is turned OFF and the bottom switch S 3 is turned ON, and the current i L1 flowing through the first inductor L 1 negatively decreases. When the current i L crosses zero (from negative to positive), after a second delay time T DELAY2 , the bottom switch S 3 is turned OFF and the top switch S 4 is turned ON, then the operation repeats. The top switch S 6 and the bottom switch S 5 operates similarly to the operation of the top switch S 4 and the bottom switch S 3 in the mean time. The top switch S 6 is turned ON after the bottom switch S 5 is turned OFF. The current i L2 flowing through the second inductor L 2 negatively increases. When the current i L2 reaches a peak limit, the top switch S 6 is turned OFF and the bottom switch S 5 is turned ON, and the current i L2 flowing through the inductor L 2 negatively decreases. When the current i L2 crosses zero (from negative to positive), after a fourth delay time T DELAY4 , the bottom switch S 5 is turned OFF and the top switch S 6 is turned ON, then the operation repeats.

In one embodiment, the third dead time T D3 is equal to the fourth dead time T D4 .

Persons of ordinary skill in the art should know that above relationships between the dead times are for illustration purpose. The value of the dead times could be set differently in accordance with the actual condition of the system.

The operation of the bridgeless converter 200 is similar to the operation of the bridgeless converter 100 , and is not described here for brevity.

FIG. 17 schematically shows a bridgeless PFC converter 300 in accordance with an embodiment of the present disclosure. The structure of the bridgeless PFC converter 300 is similar to the structure of the bridgeless PFC converters 100 and 200 . The bridgeless PFC converter 300 comprises: a first input terminal (A) and a second input terminal (B) configured to receive an input AC signal; an output terminal configured to provide an output signal; an inductor set comprising N inductors, wherein each inductor has a first terminal and a second terminal, and the first terminal of each inductor is coupled to the first input terminal (A); an output stage comprising (N+1) switching circuits coupled between the output terminal and a ground node, wherein a first switching circuit 301 comprises a first switch S 1 and a second switch S 2 , and wherein the first switch S 1 and the second switch S 2 are coupled in series, and the conjunction of the switches in the first switching circuit 301 is coupled to the second input terminal (B), and wherein each of the rest N switching circuit respectively comprises a bottom switch and a top switch, and wherein the conjunctions of the switches in the rest N switching circuits are respectively coupled to the second terminal of the N inductors; and an output capacitor Co coupled between the output terminal and the ground node; wherein: N is a nature number, and wherein N≧1.

The operation of the bridgeless PFC converter 300 is similar to the operations of the bridgeless PFC converters 100 and 200 , and is not described here for brevity.

An effective technique for bridgeless PFC control has been disclosed. While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure.