Switching power source

This application claims priority to Provisional Application Ser. No. 61/418,185 filed on Nov. 30, 2010 and claims the benefit of Japanese Patent Application No. 2010-265959, filed Nov. 30, 2010, all of which are incorporated herein by reference in their entirety.

1. Field

Embodiments of the present invention relate to a switching power source.

2. Related Background Art

In some switching power sources, a first N channel MOS transistor and a second N channel MOS transistor are provided between a positive electrode and a negative electrode of a DC voltage source. In such a switching power source, the first N channel transistor and the second N channel transistor are alternately placed in conducting state by controlling gate voltages that are applied to the first N channel transistor and the second N channel transistor, respectively.

In such a switching power source, the gate voltage is applied to the gate terminal of the second N channel transistor with reference to the voltage of the terminal that is connected to the negative electrode. The gate voltage is applied to the gate terminal of the first N channel transistor with reference to the voltage at a midpoint between the first N channel transistor and the second N channel transistor.

However, the midpoint is connected to neither the positive electrode nor the negative electrode of the DC voltage source. Therefore, the voltage at the midpoint fluctuates. In conventional switching power sources, accordingly, the gate voltage is applied to the gate terminal through a photocoupler or a transformer, for instance as disclosed in Tamotsu Inaba, “Pawa MOS FET katsuyo no kiso to jissai (Fundamentals and practice of power MOS-FET use)”, 6th edition, CQ Publishing. Co., Ltd., Feb. 1, 2010, page 136.

The above-described conventional switching power source may exhibit limitations in high-speed driving. For instance, high-speed driving of the switching power source may be limited on account of photocoupler delay.

In the present technical field, therefore, a switching power source is required that is capable of high-speed driving.

A switching power source according to one aspect of the present invention includes a first transistor and a second transistor. The first transistor is connected to a positive electrode of a DC voltage source. The second transistor is connected between the first transistor and a negative electrode of a DC voltage source. The first transistor and the second transistor are alternately placed in conducting state. A gate signal is applied to a gate terminal of the first transistor with reference to a voltage of a terminal of the first transistor that is connected to the positive electrode. A gate signal is applied to a gate terminal of the second transistor with reference to a voltage of a terminal of the second transistor that is connected to the negative electrode. The first transistor and the second transistor are configured with wide bandgap semiconductors of mutually different materials, respectively.

In the switching power source, a gate voltage is applied to a gate terminal of the first transistor that is connected to the positive electrode of the DC voltage source, with reference to the voltage of a terminal connected to the positive electrode. Therefore, a stable reference gate voltage can be applied to the first transistor without a photocoupler or transformer. Accordingly, the switching power source is capable of high-speed operation. In addition, using in the second transistor a wide bandgap semiconductor different from commonly used semiconductors allows realizing a first transistor that can be driven with reference to the voltage of the terminal connected to the positive electrode in a switching power source where high-speed operation is required.

In one embodiment, the first transistor may be a P channel MOS transistor, and the second transistor may be an N channel MOS transistor. In one embodiment, the wide bandgap semiconductor that configures the first transistor may comprise diamond. The structure of the transistors is not limited to that of a MOS transistor (MOSFET), and may be that of a junction type transistor (JFET). The transistors are not limited to being vertical type or horizontal type transistors.

As described above, a switching power source that is capable of high-speed driving is provided.

FIG. 1 is a circuit diagram of a switching power source according to one embodiment; and

FIG. 2 is a circuit diagram of a switching power source according to another embodiment.

Various embodiments of the present invention are explained in detail with reference to accompanying drawings. In the drawings, identical or equivalent portions are denoted with the same reference symbol.

FIG. 1 is a circuit diagram of a switching power source according to one embodiment. A switching power source 10 illustrated in FIG. 1 includes a first transistor Tr 1 and a second transistor Tr 2 . In one embodiment, the switching power source 10 may further includes a capacitor C 10 , an inductor L 10 and a capacitor C 12 .

The transistor Tr 1 is connected to a positive electrode of a DC voltage source 14 . The transistor Tr 2 is connected between the transistor Tr 1 and a negative electrode of the DC voltage source 14 . The capacitor C 10 is connected in parallel to the DC voltage source 14 , as illustrated in FIG. 1 . One end of the inductor L 10 is connected to a midpoint N 10 between the transistor Tr 1 and the transistor Tr 2 . One end of the capacitor C 12 is connected to the other end of the inductor L 10 . The other end of the capacitor C 12 is connected to the negative electrode of the DC voltage source 14 . To the switching power source 10 , a load L is connected in parallel to the capacitor C 12 .

The configuration of the switching power source 10 is explained in more detail below. As illustrated in FIG. 1 , a first terminal of the transistor Tr 2 is connected to the midpoint N 10 , and a second terminal of the transistor Tr 2 is connected to the negative electrode of the DC voltage source 14 . The transistor Tr 2 is controlled by a gate signal from a gate signal generator G 2 . The gate signal generator G 2 applies, to the transistor Tr 2 , a gate signal with reference to the voltage of the second terminal connected to the negative electrode of the DC voltage source 14 .

In one embodiment, the transistor Tr 2 may be an N channel junction type transistor or MOS transistor. In this case, the first terminal of the transistor Tr 2 is a drain terminal, and the second terminal is a source terminal. More specifically, the transistor Tr 2 may be a vertical type or horizontal type N channel junction type transistor or MOS transistor. The wide bandgap semiconductor that configures an N channel transistor includes, for example, SiC or GaN.

The first terminal of the transistor Tr 1 is connected to the positive electrode of the DC voltage source 14 , and the second terminal of the transistor Tr 1 is connected to the midpoint N 10 . The transistor Tr 1 is controlled by a gate signal from a gate signal generator G 1 . The gate signal generator G 1 applies, to the transistor Tr 1 , a gate signal with reference to the voltage of the first terminal connected to the positive electrode of the DC voltage source 14 .

In the switching power source 10 , the transistor Tr 1 is made up of a wide bandgap semiconductor that is different from that of the transistor Tr 2 . In one embodiment, the transistor Tr 1 may be a P channel junction type transistor or MOS transistor. In this case, the first terminal of the transistor Tr 1 is a drain terminal, and the second terminal is a source terminal. The wide bandgap semiconductor that configures a P channel transistor includes diamond and cBN (cubic boron nitride). The transistors may each be of vertical type or horizontal type.

In the switching power source 10 , the transistor Tr 1 and the transistor Tr 2 are alternately placed in conducting state based on respective gate signals from the gate signal generator G 1 and the gate signal generator G 2 . As a result, substantially DC voltage is generated in the capacitor C 12 , and DC power is applied to the load L.

In the switching power source 10 having such a configuration, a gate voltage based on the voltage of the terminal connected to the positive electrode is applied to the gate terminal of the first transistor Tr 1 that is connected to the positive electrode of the DC voltage source 14 . Therefore, a stable reference gate voltage can be applied to the first transistor Tr 1 without a photocoupler or transformer. Accordingly, the switching power source 10 is capable of high-speed operation.

In addition, utilizing a wide bandgap semiconductor that is different from a semiconductor material commonly used in the second transistor Tr 2 , a first transistor can be realized that can be driven with reference to the voltage coupled to the positive electrode. More specifically, a conventional P channel MOS transistor or junction type transistor made up of Si semiconductor is not appropriate for switching power sources where high-speed operation is required, due to its characteristic of a small rated drain current, i.e. the characteristic of a small ampacity. In contrast, using a wide bandgap semiconductor, such as diamond or cBN, that is different from that of the second transistor Tr 2 , allows realizing a first transistor Tr 1 that can be driven with reference to the voltage of the terminal connected to the positive electrode in the switching power source 10 where high-speed operation is required.

A switching power source according to another embodiment is explained next. FIG. 2 is a circuit diagram of a switching power source according to another embodiment. A switching power source 20 illustrated in FIG. 2 further includes a third transistor Tr 3 and a fourth transistor Tr 4 , in addition to the first transistor Tr 1 and the second transistor Tr 2 .

The switching power source 20 may include a capacitor C 20 that is similar to the capacitor C 10 of the switching power source 10 . The capacitor C 20 is connected in parallel to the DC voltage source 24 .

The transistor Tr 1 is connected to a positive electrode of a DC voltage source 24 . The transistor Tr 2 is connected between the transistor Tr 1 and a negative electrode of the DC voltage source 24 . The transistor Tr 2 is configured with a wide gap semiconductor different from the semiconductor that configures the transistor Tr 1 . In one embodiment, the transistor Tr 1 may be a horizontal type P channel junction type transistor, and the transistor Tr 2 may be a horizontal type N channel junction type transistor. The N channel junction type transistor can be configured with a semiconductor material such as SiC or GaN. The horizontal type P channel junction type transistor can be configured with a semiconductor material such as diamond or cBN.

The gate signal source G 1 applies a gate signal to the transistor Tr 1 with reference to the voltage of the terminal of the transistor Tr 1 that is connected to the positive electrode of the DC voltage source 24 . The gate signal source G 2 applies a gate signal to the transistor Tr 2 with reference to the voltage of the terminal of the transistor Tr 2 that is connected to the negative electrode of the DC voltage source 24 .

The transistor Tr 3 is provided in parallel to the transistor Tr 1 , and is connected to a positive electrode of a DC voltage source 24 . The transistor Tr 4 is provided in parallel to the transistor Tr 2 , and is connected between the transistor Tr 3 and a negative electrode of the DC voltage source 24 .

The transistor Tr 3 is configured with a wide gap semiconductor different from the semiconductor that configures the transistor Tr 4 . In one embodiment, the transistor Tr 3 may be a vertical type P channel MOS transistor, and the transistor Tr 4 may be a vertical type or horizontal type N channel junction type transistor or MOS transistor. The N channel transistor can be configured with a semiconductor material such as SiC or GaN. The P channel MOS transistor can be configured with a semiconductor material such as diamond or cBN.

More specifically, the first terminal (for instance, drain terminal) of the transistor Tr 3 is connected to the positive electrode of the DC voltage source 24 . The second terminal (for instance, source terminal) of the transistor Tr 3 is connected to a midpoint N 22 between the transistor Tr 3 and the transistor Tr 4 . A gate signal from a gate signal generator G 3 is applied to the gate terminal of the transistor Tr 3 with reference to the voltage of the first terminal of the transistor Tr 3 that is connected to the positive electrode of the DC voltage source 24 .

A first terminal (for instance, drain terminal) of the transistor Tr 4 is connected to the midpoint N 22 , and a second terminal (for instance, source terminal) of the transistor Tr 4 is connected to the negative electrode of the DC voltage source 24 . A gate signal from a gate signal generator G 4 is applied to the gate terminal of the transistor Tr 4 with reference to the voltage of the second terminal of the transistor Tr 4 that is connected to the negative electrode of the DC voltage source 24 .

A load L 2 (in the present example, an inductor) is connected between the midpoint N 22 and a midpoint N 20 between the transistor Tr 1 and the transistor Tr 2 of the switching power source 20 . In the switching power source 20 , gate signals from the gate signal generators G 1 to G 4 are applied such that the transistor Tr 2 and the transistor Tr 3 are placed in non-conducting state at a period where the transistor Tr 1 and the transistor Tr 4 are placed in conducting state. Conversely, gate signals from the gate signal generators G 1 to G 4 are applied such that the transistor Tr 1 and the transistor Tr 4 are placed in non-conducting state at a period where the transistor Tr 2 and the transistor Tr 3 are placed in conducting state. As a result, AC voltage is applied to the load L 2 .

In the switching power source 20 as well, gate signals are applied to the transistor Tr 1 and the transistor Tr 3 that are connected to the positive electrode of the DC voltage source 24 with reference to the voltages of the terminals that are connected to the positive electrode. Therefore, stable reference gate voltages can be applied to the transistor Tr 1 and the transistor Tr 3 without a photocoupler or transformer. Accordingly, the switching power source 20 is capable of high-speed operation.

In addition, using a wide bandgap semiconductor, such as diamond or cBN, that is different from that of the transistor Tr 2 and the transistor Tr 4 , allows realizing a transistor Tr 1 and a transistor Tr 3 that can be driven with reference to the voltages of the terminals connected to the positive electrode in the switching power source 20 where high-speed operation is required.