Semiconductor switch device and method of manufacturing semiconductor switch device

The present application is a of continuation International Application No. PCT/JP2010/058173 filed May 14, 2010, which claims priority to Japanese Patent Application No. 2009-120720 filed May 19, 2009, the entire contents of each of these applications being incorporated herein by reference in their entirety.

The present invention relates to a semiconductor switch device in which a switch circuit, etc. are constituted by using semiconductor elements, such as an FET (Field Effect Transistor), and to a method of manufacturing the semiconductor switch device.

Transition from the second-generation cellular phone system to the third-generation cellular phone system is now in progress. With such system transition, an integrated circuit fabricated by integrating a logic circuit, an amplification circuit, etc. with the switch circuit is employed in front-end portions of the cellular phones in increasing number.

In that type of integrated circuit, it is demanded to improve not only characteristics of the switch circuit alone, but also characteristics of the entire integrated circuit, such as an insertion loss and isolation. Therefore, some integrated circuit is constituted as a semiconductor switch device in which a depletion-type FET (hereinafter referred to as a “D-type FET”) and an enhancement-type FET (hereinafter referred to as an “E-type FET”) are formed on a single semiconductor substrate in a mixed way. For example, see Japanese Unexamined Patent Application Publication No. 2005-203642 (PTL 1). The D-type FET has a normally-on characteristic that a threshold voltage is negative when a drain current starts to flow, and it is featured in having a smaller insertion loss than the E-type FET. The D-type FET is used in many switch circuits. The E-type FET has a normally-off characteristic that a threshold voltage is positive when a drain current starts to flow, and it is used in many amplification circuits and many logic circuits.

The present disclosure provides a semiconductor switch device having an improved distortion characteristic, and a method of manufacturing the semiconductor switch device.

In one aspect, a semiconductor switch device includes a plurality of semiconductor elements, e.g., an E-type FET and a D-type FET, formed on a semiconductor substrate and constituting a switch circuit and a connection circuit, e.g., a logic circuit, connected to the switch circuit. Each of the semiconductor elements includes recess, a gate electrode portion including a gate electrode, a drain electrode portion including a drain electrode, and a source electrode portion including a source electrode. The gate electrode forming portion is arranged between the drain electrode portion and the source electrode portion. The switch circuit is constituted by at least one of the semiconductor elements in which the gate electrode has a rectangular external shape in section. The connection circuit includes at least one of the semiconductor elements in which the gate electrode has an external shape other than being rectangular in section.

In a more specific embodiment, the recess may have a multi-stepped shape including a first recess portion and a second recess portion deeper than the first recess portion, the second recess portion having a recess width smaller than a recess width of the first recess portion.

In another more specific embodiment, a ratio of the recess width of the second recess portion to the recess width of the first recess portion is larger in the semiconductor element including the rectangular gate than in the semiconductor element including the V-shaped gate and the T-shaped gate.

In another aspect of the disclosure, a semiconductor switch device includes a plurality of semiconductor elements formed on a single semiconductor substrate with provision of recesses for the semiconductor elements. The plurality of semiconductor elements are used to constitute a switch circuit and a connection circuit connected to the switch circuit. Each of the semiconductor elements comprises a gate electrode forming portion, a drain electrode forming portion, and a source electrode forming portion including respectively a gate electrode, a drain electrode, and a source electrode. The gate electrode forming portion is arranged between the drain electrode forming portion and the source electrode forming portion. The recess has a multi-stepped shape including a first recess portion and a second recess portion deeper than the first recess portion, the second recess portion having a recess width smaller than a recess width of the first recess portion. A ratio of the recess width of the second recess portion to the recess width of the first recess portion is larger in the semiconductor element constituting the switch circuit than in the semiconductor element constituting the connection circuit.

In a more specific embodiment, the recess width of the second recess is larger in the semiconductor element including the gate electrode having the rectangular sectional shape than in the semiconductor element including the gate electrode having the sectional shape other than being rectangular.

In another more specific embodiment, an amplification circuit provided with the semiconductor element including a gate having a shape other than rectangular can be formed on the semiconductor substrate.

In another aspect of the disclosure, a manufacturing method includes forming rectangular gate after forming the gate electrode having a sectional shape other than rectangular.

FIG. 1 is a schematic sectional view of a semiconductor switch device according to a first exemplary embodiment.

FIG. 2 represents characteristic graphs of the semiconductor switch device illustrated in FIG. 1 .

FIG. 3 represents schematic circuit diagrams of the semiconductor switch device illustrated in FIG. 1 .

FIG. 4 represents sectional views illustrating states in successive steps of a manufacturing process for the semiconductor switch device illustrated in FIG. 1 .

FIG. 5 is a schematic sectional view of a semiconductor switch device according to a second exemplary embodiment.

FIG. 6 represents schematic circuit diagrams of the semiconductor switch device illustrated in FIG. 5 .

FIG. 7 is a schematic sectional view of a semiconductor switch device according to a third exemplary embodiment.

FIG. 8 is a schematic sectional view of a semiconductor switch device according to a fourth exemplary embodiment.

The inventors recognized that a third-generation cellular phone system faces a serious problem in that intermodulation distortion enters a reception path and causes a reception error in addition to harmonic distortion (signal distortion), which has so far been a problem in the second-generation cellular phone system. The intermodulation distortion is generated by mixing of jamming waves and transmitted waves, which exist in air. Thus, in the third-generation cellular phone system, the distortion characteristic that has not been taken into consideration as a problem in the second-generation cellular phone system is an important characteristic, and improvement of the distortion characteristic with reduction of both the harmonic distortion and the intermodulation distortion is demanded.

The inventors of this application have found that linearity of a capacitance characteristic in the FET constituting a switch circuit greatly affects the distortion characteristic, and the present disclosure addresses that finding.

A semiconductor switch device according to a first exemplary embodiment will now be described in connection with FIG. 1 , which depicts an example in which an FET is formed as a semiconductor element. It is to be noted that embodiments also can be applied to the case using an HEMT (high Electron Mobility Transistor) as one type of FET.

FIG. 1 is a schematic sectional view of the semiconductor switch device 1 . The semiconductor switch device 1 includes a plurality of semiconductor elements including at least two types of semiconductor elements E 1 and D 1 . FIG. 1 illustrates an exemplary construction in which the semiconductor element E 1 and the semiconductor element D 1 are formed side by side.

The semiconductor switch device 1 includes a semiconductor substrate 2 , gate electrodes 4 A and 4 B, source electrodes 5 A and 5 B, and drain electrodes 6 A and 6 B. The semiconductor substrate 2 includes a GaAs layer 2 A as a semiconductor layer, a channel layer 2 B epitaxially grown on the GaAs layer 2 A, and a contact layer 2 C epitaxially grown on the channel layer 2 B.

The semiconductor substrate 2 includes a groove 3 C that is formed by partly removing the contact layer 2 C, the channel layer 2 B, and the GaAs layer 2 A. The groove 3 C delimits a region where one semiconductor element is formed, and it makes the GaAs layer 2 A exposed to the outside.

The semiconductor substrate 2 includes recesses 3 A and 3 B, which are formed by partly removing the contact layer 2 C, in the regions where the semiconductor elements are formed, respectively. The recesses 3 A and 3 B make the channel layer 2 B exposed to the outside.

The source electrodes 5 A and 5 B and the drain electrodes 6 A and 6 B are formed on the contact layer 2 C at positions corresponding to respective ridges aside on both sides of the recesses 3 A and 3 B, respectively. The source electrodes 5 A and 5 B and respective portions of the contact layer 2 C just thereunder constitute source electrode forming portions in the present disclosure. The drain electrodes 6 A and 6 B and respective portions of the channel layer 2 B just thereunder constitute drain electrode forming portions in the present disclosure.

The gate electrodes 4 A and 4 B are formed on bottom surfaces of the recesses 3 A and 3 B. The gate electrode 4 A is formed in a state partly buried in the channel layer 2 B, and the gate electrode 4 B is formed on the channel layer 2 B. Each of portions of the gate electrodes 4 A and 4 B, which project respectively from the bottom surface of the recesses 3 A and 3 B, constitutes a gate electrode forming portion in the present disclosure.

The semiconductor element E 1 is an E-type FET and is made up of the semiconductor substrate 2 , the gate electrode 4 A, the source electrode 5 A, and the drain electrode 6 A. The gate electrode 4 A is a V-shaped gate formed to have a V-shape in section (hereinafter referred to as a “V-shaped gate 4 A”). The recess 3 A is formed in the region of the semiconductor substrate 2 where the semiconductor element E 1 is formed. The recess 3 A has two steps in sectional shape, which are constituted by a first recess portion formed by processing the contact layer 2 C and a second recess portion formed by processing the channel layer 2 B. A recess width L 1 of the first recess portion is larger than a recess width L 2 of the second recess portion.

The semiconductor element D 1 is a D-type FET and is made up of the semiconductor substrate 2 , the gate electrode 4 B, the source electrode 5 B, and the drain electrode 6 B. The gate electrode 4 B is a rectangular gate formed to have a rectangular shape in section (hereinafter referred to as a “rectangular gate 4 B”). The recess 3 B is formed in the region of the semiconductor substrate 2 where the semiconductor element D 1 is formed. The recess 3 B has two steps in sectional shape, which are constituted by a first recess portion formed by processing the contact layer 2 C and a second recess portion formed by processing the channel layer 2 B. A recess width L 1 ′ of the first recess portion is larger than a recess width L 2 ′ of the second recess portion.

In the semiconductor element D 1 of this embodiment, because the rectangular gate 4 B is employed, its surface area can be reduced. Comparing with the case employing a V-shaped gate or a T-shaped gate, therefore, a stray capacitance component generated between the semiconductor substrate 2 and each of the source electrode 5 B and the drain electrode 6 B can be reduced. Further, the recess width L 2 ′ for the semiconductor element D 1 is set larger than the recess width L 2 for the semiconductor element E 1 such that a potential gradient in the channel layer 2 B is moderated and linearity of a capacitance characteristic is improved. On the other hand, in the semiconductor element E 1 , a decrease of an amplification rate and an increase of an impedance component are suppressed by employing the V-shaped gate.

The capacitance characteristic of a semiconductor element is now described in connection with, by way of example, the D-type FET.

FIG. 2A is a graph plotting the relationship between a source-drain capacitance Coff and a gate-source voltage Vgs in an off-state of the D-type FET. The graph comparatively plots the case employing a rectangular gate as the D-type FET and the case employing a V-shaped gate as the D-type FET. Further, the gate-source voltage Vgs is represented in terms of the so-called inverse voltage.

As seen from the graph of FIG. 2A , the capacitance Coff in the case employing the rectangular gate is always smaller than the capacitance Coff in the case employing the V-shaped gate, and the stray capacitance component between the gate electrode and each of the drain electrode and the source electrode can be suppressed.

Also, from the graph of FIG. 2A , it can be confirmed that the rectangular gate provides a smaller slope of change in the capacitance Coff than the V-shaped gate in a region where the voltage Vgs is larger than a pinch-off voltage of about 0.8 V. Thus, it can be confirmed that, by employing the rectangular gate and increasing the recess width of the first recess portion, bias dependency of the capacitance Coff can be moderated and the linearity can be improved.

FIG. 2B is a graph plotting the relationship between the source-drain capacitance Coff and L 2 ′/L 1 ′, i.e., a ratio of the recess width of the second recess portion to the recess width of the first recess portion in the two-stepped recess for the rectangular gate. FIG. 2B comparatively represents data while the gate-source voltage Vgs is kept at the same condition.

As seen from the graph of FIG. 2B , the capacitance Coff decreases as the recess width ratio L 2 ′/L 1 ′ increases. Thus, it is understood that the capacitance Coff can be reduced by increasing the recess width of the second recess portion.

While the above description has been made on data obtained at different recess width ratios in the rectangular gate, the confirmed relationship is held regardless of the gate shape. It is therefore preferable to set the recess width ratio in a semiconductor element in which the capacitance Coff is to be reduced, such as a semiconductor element constituting a switch circuit, to be larger than the recess width ratio in another semiconductor element in which the necessity of reducing the capacitance Coff is relatively low.

With the arrangement described above, the linearity of the capacitance characteristic in the semiconductor element constituting the switch circuit can be improved. Further, with the a ratio of the recess width of the second recess portion to the recess width of the first recess portion is larger in one of the semiconductor elements constituting the switch circuit than in one of the semiconductor elements constituting a connection (e.g., logic) circuit, the increase of resistance in the channel region of the semiconductor element can be suppressed in the connection circuit while the distortion characteristic of the semiconductor element can be reliably improved in the switch circuit.

One example of circuit configuration of the semiconductor switch device 1 will be described below.

FIG. 3A is a schematic circuit diagram showing an exemplary configuration of the semiconductor switch device 1 . The semiconductor switch device 1 includes a switch circuit SW and a logic circuit LOGIC.

FIG. 3B is a schematic circuit diagram showing an exemplary configuration of the switch circuit SW. The switch circuit SW is constituted by a plurality of semiconductor elements D 1 , and it has input/output ports PORT 1 and PORT 2 and an antenna port ANT. In the switch circuit SW, each semiconductor element D 1 is turned on or off in accordance with a control voltage input to a control terminal, whereby connection of the input/output port PORT 1 or PORT 2 to the antenna port ANT is selected.

Here, it is supposed that all semiconductor elements constituting the switch circuit SW are the semiconductor elements D 1 including the rectangular gates 4 B. Thus, the linearity is improved in the capacitance characteristic of each semiconductor element D 1 , and the switch circuit SW has a very good distortion characteristic.

FIG. 3C is a schematic circuit diagram showing an exemplary configuration of the logic circuit LOGIC. The logic circuit LOGIC is constituted by the semiconductor element D 1 and the semiconductor element E 1 . The logic circuit LOGIC outputs a voltage of a logic level to the control terminal of the switch circuit SW in accordance with a control voltage Vct 1 that is input to an input port the logic circuit LOGIC.

In the illustrated logic circuit LOGIC, since the semiconductor element E 1 including the V-shaped gate is employed, the decrease of the amplification rate and the increase of the impedance component can be suppressed in amounts corresponding to the use of the semiconductor element E 1 in comparison with the case where all the gate electrode forming portions of the semiconductor elements E 1 are formed to be rectangular in section.

An exemplary process for manufacturing the semiconductor switch device 1 will now be described with reference to FIGS. 4A to 4G .

FIG. 4A is a sectional view illustrating a state during a region dividing step in the manufacturing process.

In this step, the groove 3 C is formed at each of positions partitioning a plurality of semiconductor elements in the semiconductor substrate 2 . More specifically, the semiconductor substrate 2 having a flat plate shape and including the GaAs layer 2 A, the channel layer 2 B, and the contact layer 2 C is first prepared. Then, the groove 3 C is formed by etching, for example, with a depth extending from the contact layer 2 C up to the GaAs layer 2 A. After completion of the region dividing step, the manufacturing process advances to a next ohmic electrode forming step.

FIG. 4B is a sectional view illustrating a state during the ohmic electrode forming step in the manufacturing process.

In this step, ohmic electrodes serving as the drain electrodes 6 A and 6 B and the source electrode 5 A and 5 B are formed in the regions individually delimited by the groove 3 C. The ohmic electrodes are each formed by metal vapor deposition. After completion of the ohmic electrode forming step, the manufacturing process advances to a next common etching step.

FIG. 4C is a sectional view illustrating a state during the common etching step in the manufacturing process.

In this step, respective first recess portions 13 A and 13 B of the recesses 3 A and 3 B are formed. More specifically, a resist film is first formed by photolithography. Next, the contact layer 2 C is partly removed by wet etching or dry etching. Thereafter, the resist film is removed. After completion of the common etching step, the manufacturing process advances to a next E-type FET etching step.

FIG. 4D is a sectional view illustrating a state during the E-type FET etching step in the manufacturing process.

In this step, the second recess portion 13 C of the recess 3 A is formed. More specifically, a resist film 11 A is first formed on the semiconductor substrate 2 by photolithography. A resist window having a taper in match with the shape of a lower surface of the V-shaped gate 4 A is formed in the resist film 11 A. Further, a resist film 11 B is formed over the resist film 11 A by photolithography. A resist window having an opening in match with the shape of the V-shaped gate 4 A, as viewed from above, is formed in the resist film 11 B. Then, the channel layer 2 B is partly removed by, e.g., wet etching or dry etching. After completion of the E-type FET etching step, the manufacturing process advances to a next E-type FET gate electrode forming step.

FIG. 4E is a sectional view illustrating a state during the E-type FET gate electrode forming step in the manufacturing process.

In this step, the V-shaped gate 4 A is formed. More specifically, metal vapor deposition is first carried out by utilizing the resist films 11 A and 11 B, which have been formed in the preceding step. Thereafter, the resist films 11 A and 11 B are removed. Thus, a process of forming the resist films is curtailed by utilizing the resist films, which have been employed in the preceding step, to form the V-shaped gate 4 A in this E-type FET gate electrode forming step as well. After completion of the E-type FET gate electrode forming step, the manufacturing process advances to a next D-type FET etching step.

FIG. 4F is a sectional view illustrating a state during the D-type FET etching step in the manufacturing process.

In this step, the second recess portion 13 D of the recess 3 B is formed. More specifically, a resist film 11 C is first formed on the semiconductor substrate 2 by photolithography. A resist window having an opening in match with the shape of the rectangular gate 4 B, as viewed from above, is formed in the resist film 11 C. Then, the channel layer 2 B is partly removed by, e.g., wet etching or dry etching. After completion of the D-type FET etching step, the manufacturing process advances to a next D-type FET gate electrode forming step.

FIG. 4G is a sectional view illustrating a state during the D-type FET gate electrode forming step in the manufacturing process.

In this step, the rectangular gate 4 B is formed. More specifically, metal vapor deposition is first carried out by utilizing the resist film 11 C, which has been formed in the preceding step. Thereafter, the resist film 11 C is removed. Thus, a process of forming the resist film is curtailed by utilizing the resist film, which has been employed in the preceding step, to form the rectangular gate 4 B in this D-type FET gate electrode forming step as well.

The semiconductor switch device 1 is manufactured by the above-described manufacturing process. With this embodiment, since the rectangular gate 4 B is formed after forming a non-rectangular gate, e.g., a V-shaped or T-shaped gate, that requires a relatively long and/or complicated manufacturing process, an influence of the steps of forming the semiconductor element in a later stage upon the semiconductor element formed in an earlier stage can be suppressed even when the different types of semiconductor elements are formed in sequence. Additionally, a risk of damaging the rectangular gate due to, e.g., heat generated in the manufacturing process of the V-shaped gate and/or the T-shaped gate is increased. The possible damage can be suppressed by forming the rectangular gate, which is relatively simple in the manufacturing process, in a later stage.

In the arrangement described above, a stray capacitance component is reduced in the gate electrode having the rectangular sectional shape (hereinafter referred to as a “rectangular gate”) as compared with a gate electrode having a V-shape or T-shape in section (hereinafter referred to as a “V-shaped or T-shaped gate”). The stray capacitance component remains after turning-off of a switch circuit and causes leakage of a high-frequency signal, thus degrading a distortion characteristic of the switch circuit. Further, the rectangular gate enables the recess to be formed in a larger width than the V-shaped gate and the T-shaped gate, for example. By forming the recess in a larger width, when the switch circuit is turned off, potential gradients between the gate electrode and the source electrode and between the gate electrode and the drain electrode can be moderated and linearity of the capacitance characteristic in the D-type FET can be improved. As a result, the distortion characteristic of the switch circuit can be improved.

There is a risk that the larger recess width may increase resistance in a channel region. In the third-generation cellular phone system to which embodiments of the present disclosure can be applied, however, it is more important to improve the distortion characteristic than to reduce the resistance in the channel region. In the present disclosure, therefore, the rectangular gate enabling the recess width to be more easily increased is employed in the switch circuit in which increasing the recess width is effective in improving the distortion characteristic. On the other hand, in the connection circuit in which the effect of an increase of the recess width upon the distortion characteristic is less important, the V-shaped gate or the T-shaped gate is formed to suppress an increase of resistance in the channel region of the E-type FET. Herein, the term “recess” implies a groove formed between the drain electrode forming portion and the source electrode forming portion and having a recessed sectional shape. The term “recess width” implies a width of the groove.

A semiconductor switch device 21 according to a second exemplary embodiment will now be described with reference to FIG. 5 . In the following, the same components as those in the first exemplary embodiment are denoted by the same symbols, and description of those components is given above.

In embodiments in which the recess has a multi-stepped shape including a first recess portion and a second recess portion deeper than the first recess portion, the second recess portion having a recess width smaller than a recess width of the first recess portion, the stray capacitance component generated in the recess can be further reduced, and the linearity of the capacitance characteristic in the semiconductor element can be improved.

In embodiments in which a ratio of the recess width of the second recess portion to the recess width of the first recess portion is larger in the semiconductor element including the rectangular gate than in the semiconductor element including a gate shape other than rectangular (e.g., a V-shaped gate or a T-shaped gate), the increase of resistance in the channel region of the semiconductor element can be suppressed in the connection circuit while the distortion characteristic of the semiconductor element can be reliably improved in the switch circuit.

FIG. 5 is a schematic sectional view of the semiconductor switch device 21 . The semiconductor switch device 21 includes a plurality of semiconductor elements including at least three types of semiconductor elements E 1 , D 1 and D 2 .

The semiconductor element D 2 is a D-type FET and is made up of a semiconductor substrate 22 , a gate electrode 24 , a source electrode 25 , and a drain electrode 26 . The gate electrode 24 is a V-shaped gate formed to have a V-shape in section (hereinafter referred to as a “V-shaped gate 24 ”). By partly removing the contact layer 2 C, a recess 23 is formed in a region of the semiconductor substrate 22 where the semiconductor element D 2 is formed. The recess 23 has two steps in sectional shape and has a recess width in the same size as that for the semiconductor element E 1 . The source electrode 25 and the drain electrode 26 are formed on the contact layer on both sides of the recess 23 .

Since the V-shaped gate 24 is employed in the semiconductor element D 2 of this embodiment, the recess width L 2 is reduced in comparison with the case employing the rectangular gate. As a result, the decrease of the amplification rate and the increase of the impedance component can be suppressed in the semiconductor element D 2 .

One example of circuit configuration of the semiconductor switch device 1 will now be described.

FIG. 6A is a schematic circuit diagram showing an exemplary configuration of the semiconductor switch device 21 . The semiconductor switch device 21 includes a switch circuit SW, a logic circuit LOGIC, a power amplifier PA, and a low-noise amplifier LNA.

FIG. 6B is a schematic circuit diagram showing an exemplary configuration of the switch circuit SW. The switch circuit SW is constituted by a plurality of semiconductor elements D 1 .

Here, it is supposed that all semiconductor elements constituting the switch circuit SW are the semiconductor elements D 1 including the rectangular gates 4 B. Thus, the linearity is improved in the capacitance characteristic of each semiconductor element D 1 , and the switch circuit SW has a very good distortion characteristic.

FIG. 6C is a schematic circuit diagram showing an exemplary configuration of the logic circuit LOGIC. The logic circuit LOGIC is constituted by the semiconductor element D 2 and the semiconductor element E 1 . The logic circuit LOGIC outputs a voltage of a logic level to a control terminal of the switch circuit SW in accordance with a control voltage Vct 1 that is input to an input port of the logic circuit LOGIC.

In this embodiment, since the logic circuit LOGIC is constituted by the semiconductor elements E 1 and D 2 each including the V-shaped gate, the decrease of the amplification rate and the increase of the impedance component can be suppressed corresponding to the use of the semiconductor elements E 1 and D 2 .

FIG. 6D is a schematic circuit diagram showing an exemplary configuration of the power amplifier PA and the low-noise amplifier LNA. Each of the power amplifier PA and the low-noise amplifier LNA is constituted by the semiconductor element D 2 . Accordingly, the decrease of the amplification rate and the increase of the impedance component can be suppressed corresponding to the use of the semiconductor element D 2 .

A semiconductor switch device 31 according to a third exemplary embodiment will now be described with reference to FIG. 7 . In the following, the same components as those in the first and second embodiments are denoted by the same symbols, and description of those components is given above.

FIG. 7 is a schematic sectional view of the semiconductor switch device 31 . The semiconductor switch device 31 includes a plurality of semiconductor elements including at least three types of semiconductor elements E 2 , D 1 and D 3 .

The semiconductor element D 3 is a D-type FET, and it includes a gate electrode 34 A. The semiconductor element E 2 is an E-type FET, and it includes a gate electrode 34 B. The gate electrodes 34 A and 34 B are each a T-shaped gate formed to have a T-shape in section.

Even when the T-shaped gate 24 is employed instead of the V-shaped gate as in this embodiment, the decrease of the amplification rate and the increase of the impedance component in the semiconductor element can be suppressed by minimizing the recess width for the T-shaped gate as in the case employing the V-shaped gate.

A semiconductor switch device 41 according to a fourth exemplary embodiment will now be described with reference to FIG. 8 . In the following, the same components as those in the first to third embodiments are denoted by the same symbols, and description of those components is given above.

FIG. 8 is a schematic sectional view of the semiconductor switch device 41 . The semiconductor switch device 41 includes a plurality of semiconductor elements including at least three types of semiconductor elements E 2 , D 4 and D 3 .

The semiconductor element D 4 is a D-type FET including a rectangular gate, and it includes a semiconductor substrate 42 in which a recess 43 is formed. The recess 43 is formed such that its recess width has the same size as that for each of the semiconductor element D 3 and the semiconductor element E 2 . Such a structure of the semiconductor element D 4 is employed in the semiconductor element constituting the switch circuit SW.

Even when the recess width is set to be the same for all the semiconductor elements as in this embodiment, the distortion characteristic of the switch circuit can be improved by employing the T-shaped gate, the V-shaped gate, and the rectangular gate in a combined manner.

In embodiments including an amplification circuit with a semiconductor element including the V-shaped gate or the T-shaped gate in the semiconductor substrate, the amplification circuit can be formed in an integrated state on the semiconductor substrate, whereby a degree of integration in the circuit configuration can be increased and some steps in a manufacturing process can be performed in common.

Embodiments according to the present disclosure can improve the linearity of the capacitance characteristic in the semiconductor element while suppressing a decrease of an amplification rate and an increase of an impedance component. It is hence possible to improve the distortion characteristic and to suppress, e.g., the occurrence of a reception error in the third-generation cellular phone system.

While exemplary embodiments have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure.