Switching controller with valley-lock switching and limited maximum frequency for quasi-resonant power converters

This application claims the benefit of U.S. Provisional Application No. 61/450,642, filed on Mar. 9, 2011, the contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention generally relates to power converters; more specifically, the present invention relates to quasi-resonant power converters.

2. Description of the Related Art

To achieve higher efficiency and reduce power loss of a power converter under high switching frequency, quasi-resonant (QR) technique is widely applied. However, one drawback of the QR power converter is lower efficiency under light-load condition. The switching frequency of QR power converter is varied in response to an input voltage and an output load of the QR power converter. Its switching frequency is normally increased when the output load is decreased. Acoustic noise might be generated during the valley switching operation, which becomes a main issue to be resolved.

The operative description of QR power converter can be found in the prior art:

“Switching Control Circuit Having a Valley Voltage Detector to Achieve Soft Switching for a Resonant Power Converter”, U.S. Pat. No. 7,426,120.

The present invention provides a controller for a power converter. The controller comprises a PWM circuit, a detection circuit, a signal generator, an oscillation circuit, a valley-lock circuit, a timing circuit and a burst circuit. The PWM circuit generates a switching signal coupled to switch a transformer of the power converter. A feedback signal is coupled to control and disable the switching signal. The detection circuit is coupled to the transformer via a resistor for generating a valley signal in response to a waveform obtained from the transformer. The signal generator is coupled to receive the feedback signal and the valley signal for generating an enabling signal. The oscillation circuit generates a maximum frequency signal. The maximum frequency signal associates with the enabling signal to generate a turning-on signal. The turning-on signal is coupled to enable the switching signal. The feedback signal is correlated to an output load of the power converter. A maximum frequency of the turning-on signal is limited.

The valley-lock circuit and the timing circuit are coupled to receive the valley signal for providing a hysteresis characteristic for the enabling signal. The burst circuit is coupled to receive the feedback signal for generating a burst signal to disable the switching signal. The burst circuit generates the burst signal in response to a hysteresis-threshold signal. An off time of the switching signal is increased in response to a decrement of the feedback signal.

The present invention also provides a method for controlling a quasi-resonant (QR) power converter. The method comprises generating a switching signal coupled to switch a transformer of the QR power converter; generating a reset signal in response to a feedback signal; generating a valley signal in response to a waveform obtained from the transformer during an off time of the switching signal; generating a maximum frequency signal; generating an enabling signal in response to the feedback signal and the valley signal; and generating a turning-on signal in response to the enabling signal and the maximum frequency signal. The reset signal is coupled to disable the switching signal. The turning-on signal is coupled to enable the switching signal. The feedback signal is correlated to an output load of the QR power converter. The valley signal is generated via a resistor coupled to the transformer. The method further comprises providing a hysteresis characteristic for the enabling signal by a timing circuit. The timing circuit provides the hysteresis characteristic in response to the valley signal. The timing circuit provides the hysteresis characteristic by programming a threshold or a time constant of the timing circuit. The method further comprises generating an overflow signal in response to the valley signal. The turning-on signal is generated in response to the feedback signal when the overflow signal is generated without being synchronized by the valley signal. The method further comprises generating a burst signal in response to the feedback signal. The burst signal is coupled to disable the switching signal. The burst signal is generated in response to the feedback signal and a hysteresis-threshold signal. The off time of the switching signal is increased in response to a decrement of the feedback signal.

The present invention also provides a method for switching a power converter. The method comprises generating a switching signal coupled to switch a transformer of the power converter; generating a reset signal in response to a feedback signal; generating a valley signal in response to a waveform obtained from the transformer during an off time of the switching signal; generating a turning-on signal in response to the feedback signal and the valley signal; providing a hysteresis characteristic for the turning-on signal. The reset signal is coupled to disable the switching signal. The turning-on signal is coupled to enable the switching signal. The feedback signal is correlated to an output load of the power converter. The hysteresis characteristic is provided by a timing circuit in response to the valley signal. The method further comprises generating a timing signal to generate the turning-on signal. A period of the timing signal is increased in response to a decrement of the feedback signal. The valley signal is generated via a resistor coupled to the transformer. The method further comprises generating an overflow signal in response to the valley signal. The overflow signal is coupled to disable a valley switching operation of the power converter. The turning-on signal is generated in response to the feedback signal when the overflow signal is generated without being synchronized by the valley signal.

It is therefore an object of the present invention to provide a controller for a quasi-resonant power converter that can limit the maximum switching frequency and achieve valley switching operation under both heavy-load and light-load conditions. Therefore, high efficiency of the quasi-resonant power converter can be achieved over full-range load conditions.

It is also another object of the present invention to provide a controller for the quasi-resonant power converter with valley-lock function, which is beneficial to reduce the acoustic noise of the transformer during a valley number of the valley switching operation is changing.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a quasi-resonant (QR) power converter;

FIG. 2A shows an embodiment of a controller of the quasi-resonant power converter according to the present invention;

FIG. 2B shows a flowchart of a method for controlling the quasi-resonant power converter according to the present invention;

FIG. 3 shows an embodiment of a burst circuit of the controller according to the present invention;

FIG. 4 shows an embodiment of a waveform detector of the controller according to the present invention;

FIG. 5A shows an embodiment of a signal generator of the controller according to the present invention;

FIG. 5B shows another embodiment of the signal generator of the controller according to the present invention;

FIG. 6 shows an embodiment of an oscillation circuit of the signal generator according to the present invention;

FIG. 7 shows a schematic of a voltage-to-current converter of the signal generator according to the present invention;

FIG. 8 shows waveforms of a switching signal and a reflected voltage of a transformer;

FIG. 9 shows key waveforms of the quasi-resonant power converter operated under various load condition;

FIG. 10A shows key waveforms as the quasi-resonant power converter is operated at quasi-resonant and achieve valley switching operation under heavy load condition;

FIG. 10B shows key waveforms as the quasi-resonant power converter is operated at quasi-resonant and achieve extended valley switching operation under light load condition;

FIG. 11 shows an embodiment of a valley-lock circuit of the signal generator in FIG. 5A ;

FIG. 12A shows the waveforms of a valley signal and a controlling signal when an output load decreases;

FIG. 12B shows the waveforms of a valley signal and a controlling signal when the output load increases;

FIG. 13 shows an embodiment of a valley-lock circuit of the signal generator in FIG. 5B ; and

FIG. 14 shows another embodiment of the controller of the quasi-resonant power converter according to the present invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows a quasi-resonant power converter. A transformer 10 has an auxiliary winding N A , a primary winding N P and a secondary winding N S . The primary winding N P is coupled to an input voltage V IN . The secondary winding N S generates an output voltage V O via a rectifier 40 and a capacitor 45 . In order to regulate the output voltage V O , a controller 50 generates a switching signal S PWM to switch the transformer 10 via a power transistor 20 . A feedback signal V FB is correlated to the output V O of the power converter. The feedback signal V FB is coupled to the controller 50 to generate the switching signal S PWM which is utilized to regulate the output voltage V O of the power converter. A reflected voltage V AUX obtained across the auxiliary winding N A can be expressed as:

where T A and T S are respectively the winding turns of the auxiliary winding N A and the secondary winding N S of the transformer 10 .

A voltage divider is formed by resistors 31 and 32 . The voltage divider divides the reflected voltage V AUX into a detection voltage V S which is supplied to a detection terminal VS of the controller 50 . The detection voltage V S can be shown as:

where R 31 and R 32 are respectively the resistance of resistors 31 and 32 .

The detection voltage V S is also correlated to a demagnetizing time T S of the transformer 10 and the voltage V DS (the drain-to-source voltage) of the power transistor 20 . Therefore, the switching signal S PWM is generated in response to the detection voltage V S to achieve valley switching operation for the power transistor 20 .

FIG. 2A shows an embodiment of the controller 50 of the quasi-resonant power converter according to the present invention. The controller in this embodiment is denoted as 50 a . The controller 50 a comprises a burst circuit 100 , a waveform detector 200 , a signal generator 300 and a PWM circuit 60 . The PWM circuit 60 comprises a flip-flop 80 , an AND gate 85 , an inverter 65 , an AND gate 76 and a comparator 75 . The controller 50 a generates a switching signal S PWM coupled to switch the transformer 10 . The burst circuit 100 receives the feedback signal V FB to generate a burst signal S BT for disabling the switching signal S PWM when the level of the feedback signal V FB is lower than a hysteresis-threshold signal V T . The signal generator 300 generates a ramp signal RMP coupled to the comparator 75 . The ramp signal RMP associates with the feedback signal V FB generate a reset signal RST at the output of the AND gate 76 . The reset signal RST is coupled to disable the switching signal S PWM . The waveform detector 200 , which is a detection circuit, is coupled to the transformer 10 via the detection terminal VS of the controller 50 a for generating a valley signal S V and a discharging-time signal S T in response to the waveform obtained from the transformer 10 . The aforementioned waveform is correlated to the reflected voltage V AUX , which is also correlated to the detection voltage V S . The signal generator 300 is coupled to receive the feedback signal V FB , the valley signal S V and the discharging-time signal S T for generating a pulse signal (turning-on signal) PLS. The pulse signal PLS is coupled to enable the switching signal S PWM by clocking the flip-flop 80 . An output of the flip-flip 80 is connected to an input of the AND gate 85 for generating the switching signal S PWM . Another input of the AND gate 85 receives the pulse signal PLS via the inverter 65 to limit the maximum duty of the switching signal S PWM .

FIG. 2B shows a flowchart of a method for controlling the quasi-resonant power converter according to the present invention. The method comprises the steps of generating a switching signal to switch a transformer of a power converter; generating a reset signal in response to a feedback signal to disable the switching signal; generating a valley signal in response to the valleys of a waveform obtained from the transformer during an off time of the switching signal; generating a turning-on signal to enable the switching signal; and providing a hysteresis characteristic for the turning-on signal.

FIG. 3 shows an embodiment of the burst circuit 100 of the controller 50 a according to the present invention. The burst circuit 100 comprises a comparator 110 and a hysteresis circuit. A positive terminal of the comparator 110 receives the feedback signal V FB . A negative terminal of the comparator 110 receives the hysteresis-threshold signal V T which is provided by the hysteresis circuit. The hysteresis circuit comprises an inverter 115 and switches 120 and 125 . As the burst signal S BT is enabled, the switch 120 will be turned on and the switch 125 will be turned off. The hysteresis-threshold signal V T will equal to a reference voltage V TA which is coupled to the switch 120 . As the burst signal S BT is disabled, the switch 125 will be turned on via the inverter 115 and the switch 120 will be turned off. The hysteresis-threshold signal V T will equal to a reference voltage V TB which is coupled to the switch 125 . The level of the reference voltage V TA is lower than that of the reference voltage V TB . The reference voltages V TA and V TB provide the hysteresis-threshold signal V T a hysteresis characteristic for generating the burst signal S BT by comparing the feedback signal V FB with the hysteresis-threshold signal V T .

FIG. 4 shows an embodiment of the waveform detector 200 of the controller 50 a according to the present invention. The waveform detector 200 comprises a voltage clamping circuit, a current detection circuit and a signal generator. The voltage clamping circuit comprises a current source 210 , a resistor 213 , a transistor 215 and a transistor 220 . The current source 210 is connected between a supply voltage V CC and a gate of the transistor 220 . The resistor 213 is connected between the gate of the transistor 220 and a drain of the transistor 215 . A gate and the drain of the transistor 215 are connected together. A source of the transistor 215 is connected to a ground reference. A source of the transistor 220 is connected to the detection terminal VS. The detection terminal VS is coupled to the transformer 10 via the voltage divider to receive the detection voltage V S . The voltage clamping circuit clamps a minimum magnitude (V S(MIN) ) of the detection voltage V S . A turn-on threshold voltage of the transistor 215 is chosen to be correlated to that of the transistor 220 . A current of the current source 210 and the resistance of the resistor 213 determine the minimum magnitude (V S(MIN) ) of the detection voltage V S at the detection terminal VS. The minimum magnitude (V S(MIN) ) of the detection voltage V S can be expressed as:

V S ⁡ ( MIN ) = - ( V i ⁢ ⁢ n × N a N p × R 32 R 31 + R 32 ) ( 3 )

where V in , is the input voltage of the quasi-resonant power converter.

The current detection circuit comprises transistors 231 , 232 and a resistor 240 . The transistors 231 and 232 form a current mirror. An input of the current mirror is connected to a drain of the transistor 220 . The resistor 240 is connected to an output of the current mirror. The current detection circuit generates a current signal V 240 across the resistor 240 in response to a current sourced to the detection terminal VS. The signal generator comprises comparators 250 , 260 , an inverter 251 and AND gates 270 , 280 . A positive terminal of the comparator 250 receives the current signal V 240 . A negative terminal of the comparator 250 is supplied with a threshold voltage V T2 . A negative terminal of the comparator 260 is connected to the detection terminal VS. A positive terminal of the comparator 260 is supplied with a threshold voltage V T1 . A first input of the AND gate 270 and a first input of the AND gate 280 are supplied with a reversed switching signal /S PWM from an output of the inverter 251 . A second input of the AND gate 270 and a second input of the AND gate 280 are respectively connected to an output of the comparator 250 and an output of the comparator 260 . An output of the AND gate 270 generates the valley signal S v in response to this current signal V 240 . When the current signal V 240 is higher than the threshold signal V T2 and the switching signal S PWM is being disabled, the valley signal S V will be enabled. When the detection voltage V S at the detection terminal VS is lower than the threshold voltage V T1 and the switching signal S PWM is being disabled, the discharging-time signal S T will be enabled. The discharging-time signal S T indicating a demagnetized time of the transformer 10 is utilized to achieve the quasi-resonant switching for the power converter.

FIG. 5A shows an embodiment of the signal generator 300 a of the controller 50 according to the present invention. The signal generator 300 a comprises a timing circuit, a valley-lock circuit 500 a , an enabling circuit and an oscillation circuit 330 . The timing circuit comprises a voltage-to-current converter 312 , a current source 313 , an inverter 315 , a transistor 316 and a capacitor 320 . The voltage-to-current converter 312 receives the feedback signal V FB to generate a current I FB . A current I 313 provided by the current source 313 is summed up with the current I FB to generate a charging current I X . The capacitor 320 is connected between an output of the voltage-to-current converter 312 and the ground reference. The transistor 316 is connected in parallel with the capacitor 320 . The discharging-time signal S T is coupled to discharge the capacitor 320 via the inverter 315 and the transistor 316 . A magnitude of the charging current I X to the capacitor 320 is equal to the sum of the current I 313 and the current I FB . The current I 313 ensures a minimum magnitude for the charging current I X . The charging current I X charges the capacitor 320 to generate a timing signal V TM across the capacitor 320 . The charging current I X to the capacitor 320 is thus decreased in response to a decrement of the feedback signal V FB . Therefore, a charging period of the timing signal V TM increases in response to the decrement of the feedback signal V FB . The enabling circuit comprises comparators 321 , 322 , an AND gate 325 and an OR gate 326 . The comparator 321 compares the timing signal V TM with a threshold voltage V TX for enabling a controlling signal S X when the timing signal V TM is higher than the threshold voltage V TX . The threshold voltage V TX determines a trip-point voltage of the timing signal V TM . A first valley signal S K is further generated by the valley-lock circuit 500 a . The comparator 322 enables a time-out signal S MT at its output when the timing signal V TM is higher than a threshold voltage V TY . The threshold voltage V TY is higher than the threshold voltage V TX . The time-out signal S MT is further coupled to generate an enabling signal S ENB via an input of the OR gate 326 . The controlling signal S X and the first valley signal S K are supplied to inputs of the AND gate 325 . An output of the AND gate 325 is connected to another input of the OR gate 326 . An output of the OR gate 326 generates the enabling signal S ENB . The valley-lock circuit 500 a receives a reference voltage V REF , the valley signal S V , the discharging-time signal S T and the enabling signal S ENB to generate the controlling signal S X and the first valley signal S K .

A period starting as the discharging-time signal S T is enabled and ending as the controlling signal S X is enabled is defined as an enabling delay time. The feedback signal V FB decreases in response to a decrement of the output load. The enabling delay time increases in response to the decrement of the feedback signal V FB . The off-time of the switching signal S PWM is therefore increased in response to the decrement of the feedback signal V FB . The oscillation circuit 330 receives the enabling signal S ENB for generating the pulse signal PLS and the ramp signal RMP.

FIG. 5B shows an embodiment of a signal generator 300 b of the controller 50 according to the present invention. Different to the embodiment in FIG. 5A , the signal generator 300 b has a valley-lock circuit 500 b generating the threshold voltage V TX and the first valley signal S K not only in response to the reference voltage V REF , the valley signal S V , the discharging-time signal S T and the enabling signal S ENB but also in response to a sinking current I K coupled to the output of the voltage-to-current converter 312 .

FIG. 6 shows an embodiment of the oscillation circuit 330 of the signal generator 300 according to the present invention. The oscillation circuit 330 comprises a saw-tooth generator and a control circuit. The saw-tooth generator comprises current sources 350 , 355 , 359 , a capacitor 340 and switches 351 , 354 , 358 . The current source 350 is connected between the supply voltage V CC and a first terminal of the switch 351 . A second terminal of the switch 351 is connected to a first terminal of the switch 354 . The current source 355 is connected between a second terminal of the switch 354 and the ground reference. The switch 358 and the current source 359 are connected in series between the second terminal of the switch 354 and the ground reference. The capacitor 340 is connected between the second terminal of the switch 351 and the ground reference. The current source 350 is utilized to charge the capacitor 340 via the switch 351 . The current source 355 is utilized to discharge the capacitor 340 via the switch 354 . The ramp signal RMP is therefore generated across the capacitor 340 . The switch 351 is controlled by a charging signal S C . The switch 354 is controlled by a discharging signal S DM . The switch 358 is controlled by a fast-discharging signal S FD . The ramp signal RMP is thus generated across the capacitor 340 . The control circuit comprises comparators 361 , 362 , 363 , NAND gates 365 , 366 , AND gates 367 , 370 , inverters 375 , 376 and an OR gate 371 . The ramp signal RMP is supplied to a negative terminal of the comparator 361 , a positive terminal of the comparator 362 and a positive terminal of the comparator 363 . A positive terminal of the comparator 361 receives a threshold voltage V H . A negative terminal of the comparator 362 receives a threshold voltage V L . A negative terminal of the comparator 363 receives a threshold voltage V M . The magnitude of the threshold voltage V H is greater than that of the threshold voltage V M . The magnitude of the threshold voltage V M is greater than that of the threshold voltage V L . NAND gates 365 and 366 form a latch circuit coupled to receive the output signals of the comparators 361 and 362 . The latch circuit outputs a discharging signal S D . The discharging signal S D , which is a maximum frequency signal, determines a maximum frequency of the switching signal S PWM . The discharging signal S D and an output signal of the comparator 363 are supplied to inputs of the AND gate 367 for generating the discharging signal S DM .

The inverter 375 receives the discharging signal S D to generate the charging signal S C . The inverter 376 receives the charging signal S C to generate the pulse signal PLS. The pulse signal PLS is enabled during a discharging period of the capacitor 340 . The discharging signal S D is further supplied to an input of the AND gate 370 to generate the fast-discharging signal S FD . The fast-discharging signal S FD and the enabling signal S ENB are supplied to inputs of the OR gate 371 . An output of the OR gate 371 is connected to another input of the AND gate 370 . Therefore, the enabling signal S ENB will trigger the fast-discharging signal S FD once the discharging signal S D is enabled. The fast-discharging signal S FD can be disabled only when the discharging signal S D is disabled. Since the current of the current source 359 is much higher than that of the current source 355 , the capacitor 340 will be immediately discharged when the fast-discharging signal S FD is enabled. During the discharging period of the capacitor 340 , the ramp signal RMP is held at the level of the threshold voltage V M until the enable signal S ENB activates the fast-discharging signal S FD . Once the ramp signal RMP is lower than the threshold voltage V L , the discharging signal S D will be disabled. The valley signal S V (the first valley signal S K ) and the enable signal S ENB are thus able to trigger the pulse signal PLS once the discharging signal S D is enabled. Therefore, the current of the current source 350 , the capacitance of the capacitor 340 and the threshold voltages V H , V M , V L determine a maximum frequency of the discharging signal S D , which also determines the maximum frequency of the switching signal S PWM .

FIG. 7 shows a schematic of the voltage-to-current converter 312 of the signal generator 300 according to the present invention. The voltage-to-current converter 312 comprises current sources 430 , 435 , an operational amplifier 410 , transistors 411 , 421 , 422 and a resistor 412 . An input terminal V is connected to a positive terminal of the operational amplifier 410 . An output terminal of the operational amplifier 410 is coupled to drive the transistor 411 . A negative terminal of the operational amplifier 410 is connected to a source of the transistor 411 . The resistor 412 is connected between the source of the transistor 411 and the ground reference. The current source 435 is connected between the supply voltage V CC and a drain of the transistor 411 . A current I 411 flowing through the transistor 411 will flow through the resistor 412 . Once the current I 411 is higher than a current I 435 sourced from the current source 435 , a current I 421 , which equals to the difference of the current I 411 and the current I 435 ) will flow via an input of the current mirror developed by transistors 421 and 422 . A current generated at a terminal I, which is also an output of the current mirror, will be in proportion to the current I 421 . A maximum current generated from the terminal I will be limited by the current source 430 . The transistor 422 generates an output current to the output terminal I, which is corrected to an input voltage received at the input terminal V.

FIG. 8 shows waveforms of the switching signal S PWM and the reflected voltage V AUX of the transformer 10 . The period T S represents the demagnetizing time of the transformer 10 , which is correlated to the discharging-time signal S T . To achieve quasi-resonant operation, the switching signal S PWM could be enabled at time point P 1 , P 2 , or P 5 , depending on the load conditions. As the load is heavier, the switching signal S PWM could be enabled earlier, such as at the time point P 1 or P 2 . As the load is lighter, the switching signal S PWM could be enabled later, such as at the time point P 3 , P 4 , or P 5 .

FIG. 9 shows key waveforms of the quasi-resonant power converter operated under various load condition. In a shown burst period T BST , the quasi-resonant power converter is operated at burst mode. The burst mode indicates that the operation of the quasi-resonant power converter has entered ultra-light-load condition. Once the burst signal S BT is activated (disabled), the switching signal S PWM will be disabled. That is, when the switching signal S PWM is not disabled by the burst signal S BT , the switching signal S PWM could be enabled at time point P 1 or P 2 for reducing the switching loss of the transistor 20 , which increases the efficiency of the quasi-resonant power converter.

FIG. 10A shows key waveforms as the quasi-resonant power converter is operated at quasi-resonant and achieve valley switching operation under heavy load condition. The switching signal S PWM is enabled at the time point P 1 shown in FIG. 8 .

FIG. 10B shows key waveforms as the quasi-resonant power converter is operated at quasi-resonant and achieve extended valley switching operation under light load condition. The switching signal S PWM is, for example, enabled at the time point P 3 shown in FIG. 8 .

FIG. 11 shows an embodiment of a valley-lock circuit 500 a of the signal generator 300 a according to the present invention. The valley-lock circuit 500 a comprises a counter 610 , a register array 620 , an inverter 611 , an AND gate 621 , an OR gate 685 , a decoder 650 , a comparison circuit 680 and a threshold generator. A counter 610 counts a code M in response to the valley signal S V . The discharging-time signal S T is coupled to reset the counter 610 via the inverter 611 . The enabling signal S ENB and the discharging-time signal S T are supplied to inputs of the AND gate 621 to generate a shift signal to shift the code M from the counter 610 to the register array 620 . The register array 620 thus generates a code N in response to the code M. According to the code N provided by the register array 620 , the decoder 650 generates control signals X N ˜X 0 . The reference voltage V REF is provided to a voltage divider developed by resistors 710 , 719 , 720 , and 721 . The voltage divider is coupled to switches 750 ˜ 759 . The control signals X N ˜X 0 are coupled to control the switches 750 ˜ 759 for programming the threshold voltage V TX . The magnitude of the threshold voltage V TX is increased in response to the increment of the code N. The hysteresis characteristic of the enabling signal S ENB and the controlling signal S X is thus provided by programming the trip-point voltage of the timing signal V TM .

The variation of the code N also represents the variation of the output load. As the output load reduces, the value of the code N will increase, and vice versa. The enabling delay time is thus increased slightly in response to the increment of the code N. This therefore provides a hysteresis for the valley switching operation. This hysteresis will lock the valley switching operation at the valley number N for a while until the feedback signal V FB from the feedback loop changes. This valley-lock function is beneficial to reduce the acoustic noise of the transformer 10 during the valley number of the valley switching operation is changing.

Furthermore, the register array 620 is coupled to a comparator 680 to generate an overflow signal S H when the value of the code N is larger than a value of a threshold code N T . The overflow signal S H and the valley signal S V are connected to inputs of the OR gate 685 to generate the first valley signal S K . Therefore, the state of the first valley signal S K is the same as that of the valley signal S V when the value of the code N is lower than that of the threshold code N T . The valley signal S K becomes logic-high when the value of the code N is greater than that of the threshold code N T .

During an ultra-light load condition, the value of the code N will be greater than the threshold code N T . This will make the overflow signal S H become logic-high and therefore make the first valley signal S K become logic-high via the OR gate 685 . After the overflow signal S H is enabled (logic-high), the turning-on of the switching signal S PWM will no longer be synchronized with the valley signal S V and the switching frequency of the switching signal S PWM will be linearly decreased in response to a decrement of the feedback signal V FB .

FIG. 12A shows the waveforms of the valley signal S V and the controlling signal S X . When the output load decreases, the valley number n, which is correlated to the code N, is increased, for example, from 3 to 4 ([S X (n−1)]→[S X (n)]). A hysteresis period T HYS will be automatically generated for the next switching cycle ([S X (n+1)].

FIG. 12B shows the waveforms of the valley signal S V and the first-enable signal S X . When the output load increases, the valley number n, which is correlated to the code N, is decreased, for example, from 4 to 3 ([S X (n−1)]→[S X (n)]). The hysteresis period T HYS will be generated for the next switching cycle ([S X (n+1)].

FIG. 13 shows another embodiment of a valley-lock circuit 500 b of the signal generator 300 b according to the present invention. The valley-lock circuit 500 b comprises a counter 610 , a register array 620 , an inverter 611 , an AND gate 621 , an OR gate 685 , a decoder 650 , a comparison circuit 680 and a programmable current sink. The threshold voltage V TX in this embodiment is a fixed value which equal to the reference voltage V REF . Current sources 810 ˜ 819 are coupled to the switches 850 ˜ 859 to form the programmable current sink. The control signals X N ˜X 0 are coupled to control the switches 850 ˜ 859 for drawing the sinking current I K . The sinking current I K is coupled to modulate the charging current I X (See FIG. 5B ). The magnitude of the charging current I X decreases in response to the increment of the code N. The charging current I X to the capacitor 320 is thus decreased in response to the increment of the code N which also represents the valley number n of the reflected voltage V AUX . Therefore, the charging time of the timing signal V TM will increase in response to the increment of the valley number of the reflected voltage V AUX . The hysteresis characteristic of the enable signal S ENB and the controlling signal S X is generated by modulating a time constant of the timing circuit.

FIG. 14 shows another embodiment of the controller 50 of the quasi-resonant power converter according to the present invention. The controller in this embodiment is denoted as 50 b . Different to the controller 50 a shown in FIG. 2A , the burst circuit 100 and the AND gate 76 are not included. The flip-flop 80 is reset by the output of the comparator 75 directly.