Delay generator

The present invention relates to a delay generator. More particularly, it relates to a process-insensitive current-controlled delay generator with threshold voltage compensation.

Sampled-data systems incorporating data conversion and switched-capacitor filters are indispensable in state-of-art IC design, and are crucial for applications such as telecommunication, consumer electronics and medical imaging. In such discrete-time systems, the clock generator is extremely important, and the accuracy of the clock signal is determinant in the overall design since it often affects the overall resolution. However, the variation of the clock pulse width exists inevitably and is normally associated with process or temperature variations in the delay paths. Usually, large design margins should be adopted in the transistor implementation to overcome such process variations. Unfortunately, this would imply extra power consumption with the subsequent degradation of system performance.

Therefore, process-insensitive delay generators are highly demanded and effective solutions have been proposed either off-chip or on-chip.

Traditionally, the delay generator is implemented by the inverter-chain, also referred to as g m /C circuit that accumulates the time delay of the inverters and provides the time delay for the system. Although its architecture is quite simple, it suffers from a significant process variation sensitivity that can lead to a significant ±15% variation in time delay.

An alternative solution, the current-controlled delay generator was previously proposed to achieve higher process-insensitivity with the utilization of less process-sensitive circuit elements. FIG. 1 a schematically illustrates a simplified delay generator which contains basically a current source, a capacitor, switches, and output buffers; and FIG. 1 b illustrates input and output waveforms of the delay generator of FIG. 1 a . The top-plate of the capacitor C is firstly charged to the voltage supply VDD and Φ out remains at HIGH level. Then, the capacitor C is linearly discharged by a constant current I b which is controlled by the current source, and thus a delay t d is generated.

To calculate the delay t d , firstly refer to the following equation:

Under a linear situation, dt≈Δt and dV C ≈ΔV C ,

thus when i=I b ; we obtain

where ΔV C is equal to VDD−V th (V th is the threshold voltage of the inverter connected to Vc).

The current I b is provided by the current source and its accuracy is mainly related to the precision of the current mirror and the reference current. This is usually accurate and the current mirror is relatively easy to design with good matching. Therefore, the current will not be significantly affected by process variations. Besides, a MOS-capacitor is adopted to ensure less sensitivity to process variations, when compared with other type of implementations of the capacitors. Normally, the MOS-capacitance varies around ±5% with process.

However, the delay generator of FIG. 1 a is still sensitive to process variations, mainly because of threshold voltage variation of the inverter connected to the capacitor. When V C decreases, the inverter will be triggered to generate the delay t d until V C passes its threshold voltage V th that depends on the robustness of the N/PMOS transistors and is highly process-sensitive.

In view of the above, it is an object of the present invention to provide an advanced current-controlled delay generator using process-insensitive components such as current mirrors and MOS-capacitors, thereby avoiding the complexity of a delay-locked loop (DLL). By applying the threshold voltage compensation, the delay generator of the present invention reduces the deviation induced by the internal inverter buffer, and thus becomes more robust to process variations than prior art.

According to an aspect of the present invention, a delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.

According to the above aspect of the present invention, the total delay is determined by the current and the first capacitance.

According to the above aspect of the present invention, the first delay portion further comprises two switches that will be tamed on by opposite input clocks.

According to the above aspect of the present invention, the second delay portion further comprises two switches that will be turned on by opposite input clocks.

These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.

FIG. 1 a shows a simplified diagram of a delay generator according to prior art.

FIG. 1 b illustrates input and output waveforms of the delay generator of FIG. 1 a.

FIG. 2 shows a block diagram of a delay generator according to the present invention.

FIG. 3 illustrates input and output waveforms of the delay generator according to the present invention.

FIG. 4 shows the circuit implementation of the delay generator according to the present invention.

FIG. 5 a shows the characteristic waveforms for a first delay portion of the delay generator according to the present invention.

FIG. 5 b shows the characteristic waveforms for a second delay portion of the delay generator according to the present invention.

FIGS. 6 a and 6 b show characteristic waveforms of the delay generator according to the present invention in a typical case and two extreme cases.

A preferred embodiment for a delay generator according to the invention is described with reference to the drawings as follows.

Refer firstly to FIG. 2 , which illustrates an embodiment of a current-controlled delay generator 200 according to the invention. In this embodiment, the delay generator 200 comprises a current source 210 , a first delay portion 220 and a second delay portion 230 . The current source 210 provides a current I b to both the first delay portion 220 and the second delay portion 230 . An input clock Φ in in is fed into the first delay portion 220 and an output clock Φ middle having a delay t d1 with respect to the clock Φ in is generated. Next, the clock Φ middle is fed into the second delay portion 230 and an output clock Φ out having a delay t d2 with respect to the clock Φ middle is generated. As a result, the total delay t dtotal generated by the delay generator 200 is obtained as t d1 +t d2 . A schematic diagram showing the total delay t dtotal =t d1 +t d2 is shown in FIG. 3 . The total delay t dtotal generated by the delay generator 200 is insensitive to the process variation because the process variation incurred when t d1 is generated and the process variation incurred when t d2 is generated will be compensated by each other. A further detail for achieving the compensation effect of the process variation according to the present invention is described as follows.

The circuit of FIG. 4 represents a preferred embodiment of the delay generator 200 . As shown in the figure, the delay generator 200 is comprised of the first delay portion 220 and the second delay portion 230 . Although, in FIG. 4 , the current source 210 is shown as included in the first delay portion 220 , the current I b is also provided to the second delay portion 230 through the bias point Vbn.

The operation of the first delay portion 220 can be divided into two phases. At the first phase, the clock Φ in is going from LOW to HIGH, the switch S 1 is open (turned off) and the switch S 2 is closed (turned on). Accordingly, a transient current will charge a capacitor C 1 until the top-plate voltage V C1 of the capacitor C 1 reaches VDD. Next, at the second phase, the clock Φ in is going from HIGH to LOW, the switch S 1 is closed (turned on) and the switch S 2 is open (turned off). Because V C1 has been charged to VDD, the voltage V tr1 (which is obtained from V C1 after two inverters) will be VDD, too. Thus, M 3 connects and a discharging current begins to flow. The current mirror comprised of M 1 and M 2 renders the discharging current equal to I b . The charge stored on the top plate of the capacitor C 1 flows to the ground through S 1 , M 3 and M 2 , and thus the voltage V C1 starts dropping. When V C1 reaches the threshold voltage V th (triggering point) of the inverter, V tr1 becomes digital ‘0’ and thus shuts off M 3 . At this moment, the discharging current stops flowing from C 1 and V C1 remains the same. The above discharging operation generates a delay t d1 , and thus the clack Φ middle is output, as clearly illustrated in FIG. 5 a . Subsequently, the operation returns to the first phase, V C1 will be charged to VDD again and V tr also goes to VDD by rapid pull-up of the inverter.

As shown in FIG. 5 a , V C1 is dropping linearly. Accordingly, by referring to the above-mentioned equation (2), t d1 can be expressed as:

Similarly, the operation of the second delay portion 230 can be divided into two phases. For the second delay portion 230 , the clock Φ middle is inverted and used as an input clock. At the first phase, the clock Φ middle is going from HIGH to LOW, the switch S 3 is open (turned off) and the switch S 4 is closed (turned on). Accordingly, C 2 , which has a capacitance as the same as that of C 1 , will be discharged through the switch S 4 and reset to ground. Next, at the second phase, the clock Φ middle is going from LOW to HIGH, the switch S 3 is closed (turned on) and the switch S 4 is open (turned off). Accordingly, C 2 is charged by a constant current from a p-type current mirror comprised of M 6 and M 7 , and the voltage V C2 starts raising from 0 (ground). When V C2 reaches the threshold voltage V th (triggering point) of the inverter, V tr2 becomes digital ‘0’ and thus shuts off M 8 . At this moment, the charging current stops flowing to C 2 and V C2 remains the same. The above charging operation generates a delay t d2 , and thus the clock Φ out is output, as clearly illustrated in FIG. 5 b.

As shown in FIG. 5 b , V C2 is raising linearly. Again, by referring to the above-mentioned equation (2), t td2 can be expressed as:

As mentioned above, the total delay t dtotal generated by the delay generator 200 is obtained by summation of t d1 and t d2 , that is, t d1 +t d2 . From equations (3) and (4), we obtain:

As C 1 =C 2 , it leads to,

Since C 1 , VDD and I b are all preset values, t dtotal will be a constant. In other words, the total delay t dtotal is not affected by the threshold voltage V th , which is highly process-sensitive.

To further explain the threshold voltage compensation applied by the present invention, refer now to FIGS. 6 a and 6 b , wherein characteristic waveforms of the delay generator according to the present invention are illustrated in a typical case (‘tt’) and two extreme cases (‘fs’: fast NMOS and slow PMOS, ‘sf’: slow NMOS and fast PMOS). The two extreme cases are provided as examples of process corners which will produce most significant drifts in the threshold voltage V th . As shown in the figures, waveforms similar to those of FIG. 5 a and 5 b can be observed for the typical case (process corner ‘tt’). For the ‘fs’ process corner, a shorter t d1,fs and a longer t d2,fs can be observed For the ‘sf’ process corner, a longer t d1,sf and a shorter t d2,sf can be observed. However, both the summation of t d1,fs and t d2,fs and the summation of t d1,sf and t d2,sf will lead to the same total delay t dtotal as that of the typical process corner ‘tt’. In other words, the shorter t d1,fs is “compensated” by the longer t d2,fs , and the longer t d1,sf is “compensated” by the shorter t d2,sf . This is not difficult to derive because, according to the above equation (6), the same total delay t dtotal will be obtained for either the ‘fs’ process corner or the ‘sf’ process corner.

While the present invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. Therefore, it is intended that the invention will include all embodiments falling within the scope of the appended claims.