Semiconductor package and electronic component package

This patent application is based on and claims priority pursuant to 35 U.S.C. §119 to Japanese Patent Application No. 2010-246693, filed on Nov. 2, 2010, in the Japan Patent Office, the entire disclosure of which is hereby incorporated by reference herein.

1. Technical Field

The present disclosure relates to a semiconductor package and an electronic component package, and more particularly to a semiconductor package in which an IC chip mounting a driver transistor is mounted on leads by flip chip bonding and sealed with resin, and an electronic component package incorporating the semiconductor package.

2. Description of the Background Art

Conventionally, in semiconductor packages in which integrated circuit (IC) chips are sealed with resin, a wire-bonding technique is used to electrically connect pads of the IC chip and leads of the semiconductor packages.

Alternatively, there is also a flip chip bonding technique in which the IC chip is mounted in a device by using projecting solder terminals called bumps arranged in a grid array. Since the flip chip bonding technique can reduce the mounting area of the IC chip compared to the wire-bonding technique, the external dimensions of the semiconductor package can be downsized when the semiconductor package is assembled with the flip chip bonding.

There are ICs that have large mounting areas, such as voltage regulator ICs mounting a driver transistor and ICs mounting a power transistor. Herein, the term “large-area transistor” means, for example, a transistor constituting an analog circuit (e.g., a reference voltage generator, a differential amplification circuit, or a buffer circuit) and a transistor whose layout area of the transistor is greater than that of transistor used to configure a digital circuit. In a semiconductor package as proposed in JP-2005-228811-A, for example, an IC chip mounting a power transistor is mounted on a wire substrate (wiring patterns) using flip chip bonding.

However, the IC chip installing large-area transistors such as a driver transistor or a power transistor generate heat caused by the transistors, which is a problem.

In an effort to counteract this problem, in a configuration in which the pads of the IC chip and the leads of the semiconductor package are electrically connected by wire bonding as proposed in JP-2006-196922-A and JP-2006-332708-A, because the IC chip is mounted on a die pad, heat radiation can be improved by exposing the die pad outside an encapsulating resin.

By contrast, in the semiconductor package assembled with flip chip bonding, the IC chip is mounted on the leads in a state in which a pad formation face of the IC chip faces the package leads. Therefore, in order to improve heat radiation, in a semiconductor package like that proposed in JP-2005-228811-A, the IC chip is not sealed with resin but with a heat releasing member formed of metal material connected to a back face of the IC chip.

However, sealing the semiconductor package using metal material is more complicated than resin sealing, and consequently the cost manufacturing a metal material-sealed semiconductor package is higher than that for a resin-sealed semiconductor package.

In one aspect of this disclosure, there is a provided a semiconductor package assembled with flip chip bonding and sealed with resin, including an IC chip and at least four leads. The IC chip includes an element arrangement region, a pad array, and a driver transistor. The pad array has at least four pads including a voltage input pad to supply an input voltage and a voltage output pad to which an output voltage is supplied. The voltage input pad and the voltage output pad are disposed at edges of the pad array. The driver transistor is disposed between the voltage input pad and the voltage output pad to receive the input voltage from the voltage input pad and output the output voltage to the voltage output pad, and the driver transistor is disposed in contact with an edge of the element arrangement region. The at least four leads on which the IC chip is mounted by the flip chip bonding are disposed corresponding to the pads in the pad array and are formed in a lead array. The leads include a voltage input lead electrically connected to the voltage input pad and a voltage output lead electrically connected to the voltage output pad. The voltage input lead and the voltage output lead are disposed at edges of the lead array.

In another aspect of this disclosure, there is a provided an electronic component package including a printed circuit board having at least four wiring patterns and a semiconductor package mounted on the printed circuit board by flip chip bonding and sealed with resin. The semiconductor package includes the above-described IC chip and the above-described at least four leads.

The aforementioned and other features, aspects and advantages of the present disclosure would be better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a plan view illustrating a semiconductor package in an electronic component package according to a first embodiment of the present disclosure;

FIG. 2 is a cross-sectional diagram of the semiconductor package in the electronic component package along a line A-A′ shown in FIG. 1 ;

FIG. 3 is a top view illustrating an external outline of an encapsulating resin and leads in the semiconductor package in FIG. 1 ;

FIG. 4 is a bottom view illustrating the external outline of the encapsulating resin and the leads in the semiconductor package shown in FIG. 3 ;

FIG. 5 is a plan view illustrating an external outline of an IC chip mounted in the semiconductor package, pads and an element arrangement region of the IC chip;

FIG. 6 is a plan view illustrating a printed circuit board in the electronic component package shown in FIG. 1 ;

FIG. 7 is a block diagram illustrating a voltage regulator formed in the IC chip shown in FIG. 5 ;

FIG. 8 is a plan view illustrating a semiconductor package in an electronic component package according to a second embodiment;

FIG. 9 is a cross-sectional diagram of the semiconductor package in the electronic component package along a line B-B′ shown in FIG. 8 ;

FIG. 10 is a plan view illustrating a semiconductor package in an electronic component package according to a third embodiment;

FIG. 11 is a plan view illustrating a semiconductor package in an electronic component package according to a forth embodiment; and

FIG. 12 is a cross-sectional diagram of the semiconductor package in the electronic component package along a line C-C′ shown in FIG. 11 .

In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner and achieve a similar result.

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, particularly to FIGS. 1 through 12 , electronic component packages including semiconductor packages according to illustrative embodiments are described.

First Embodiment

A semiconductor package 1 mounted on an electronic component package 100 according to a first embodiment is described below with reference to FIGS. 1 through 7 .

FIG. 1 is a plan view illustrating the semiconductor package 1 and the electronic component package 100 according to the first embodiment. In FIG. 1 , only an external outline of an encapsulating resin 7 of the semiconductor package 1 is represented, an integrated circuit (IC) chip is represented by a broken line, and figures of bumps and solder are omitted. FIG. 2 is a cross-sectional diagram of the semiconductor package 1 in the electronic component package 100 along a line A-A′ shown in FIG. 1 . FIG. 3 is a top view illustrating the external outline of the encapsulating resin 7 and leads 1 a , 1 b , 1 c , and 1 d in the semiconductor package 1 . FIG. 4 is a bottom view illustrating the external outline of the encapsulating resin 7 and the leads 1 a , 1 b , 1 c , and 1 d in the semiconductor package 1 . FIG. 5 is a plan view illustrating an external outline of an IC chip 3 mounted in the semiconductor package 1 , pads 3 a , 3 b , 3 c , and 3 d , and an element arrangement region (element formation region) 3 e of the IC chip 3 . FIG. 6 is a plan view (bottom view) illustrating a printed circuit board 9 in the electronic component package 100 shown in FIG. 1 .

As illustrated in FIG. 1 , in the semiconductor package 1 , the IC chip 3 is mounted on a lead frame (lead array) including four electrically separated leads 1 a , 1 b , 1 c , and 1 d via respective bumps 5 by flip chip bonding. The bumps 5 are formed of, for example, solder.

As illustrated in FIG. 5 , the IC chip 3 is, for example, a power supply IC installing a voltage regulator, and the IC chip 3 includes the four pads 3 a , 3 b , 3 c , and 3 d and the element arrangement region 3 e including a driver transistor 3 f and an analog circuit forming region 3 g. The pad 3 a functions as a voltage input pad to supply an input voltage to the driver transistor 3 f and supply a power supply voltage to an analog circuit formed in the analog circuit forming region 3 g . The pad 3 b functions as a voltage output pad to which an output voltage from the driver transistor 3 f is supplied. The pad 3 c functions as a ground pad that is connected to a ground voltage. The pad 3 d functions as an enable-terminal pad to supply an enable signal to the analog circuit formed in the analog circuit forming region 3 g.

The driver transistor 3 f is disposed between the voltage input pad 3 a and the voltage output pad 3 b and is positioned in contact with an outer edge of the element arrangement region 3 e . In this embodiment, the four pads 3 a , 3 b , 3 c , and 3 d are arranged in an array of two columns and two rows. The respective pads 3 a , 3 b , 3 c , and 3 d are arranged at edges the pad array.

In the semiconductor package 1 , the pad 3 a is connected to the lead 1 a via the bump 5 , the pad 3 b is connected to the lead 1 b via the bump 5 , the pad 3 c is connected to the lead 1 c via the bump 5 , and the pad 3 d is connected to the lead 1 d via the bump 5 . In this embodiment, since the leads 1 a , 1 b , 1 c , and 1 d are arranged in an array of two columns and two rows, the respective leads 1 a , 1 b , 1 c , and 1 d are arranged at edges of the lead array.

The leads 1 a , 1 b , 1 c , and 1 d , the IC chip 3 , and the bumps 5 are sealed with the encapsulating resin 7 . The leads 1 a , 1 b , 1 c , and 1 d have steps in a backside face (“exposure face”) opposite an IC chip mounting face that faces the IC chip 3 , such that the leads 1 a , 1 b, 1 c , and 1 d are partially exposed outside the backside face (second face) of the encapsulating resin 7 . The area of the leads 1 a , 1 b , 1 c , and 1 d in the IC chip mounting face (first face) is larger than the area of those leads in the exposure face (second face) in which the leads 1 a , 1 b , 1 c , and 1 d are exposed from the encapsulating resin 7 , that is, the first face has a surface area larger than the second face. In addition, lateral faces of the leads 1 a , 1 b , 1 c , and 1 d are partially exposed at lateral faces of the encapsulating resin 7 .

As illustrated in FIG. 2 , the electronic component package 100 is formed by mounting the semiconductor package 1 on the printed circuit board 9 . The printed circuit board 9 includes an insulative substrate 11 and wiring patterns 13 a , 13 b , 13 c , and 13 d formed on a surface of the insulative substrate 11 . With reference to FIGS. 1 , 2 , and 6 , upper ends of the wiring patterns 13 a , 13 b , 13 c , and 13 d are disposed at positions corresponding to the exposure faces of the leads 1 a , 1 b , 1 c , and 1 d of the semiconductor package 1 . The lead (voltage input lead) 1 a is connected to the wiring pattern (voltage input wiring pattern) 13 a via solder 15 , the lead (voltage output lead) 1 b is connected to the wiring pattern (voltage output wiring pattern) 13 b via the solder 15 , the lead 1 c is connected to the wiring pattern 13 c via the solder 15 , and the lead 1 d is connected to the wiring pattern 13 d via the solder 15 . The voltage input wiring pattern 13 a connected to the voltage input lead 1 a and the voltage output wiring pattern 13 b connected to the voltage output lead 1 b have line widths that are wider than line widths of the wiring patterns 13 c and 13 d.

FIG. 7 is a block diagram illustrating the voltage regulator formed in the IC chip 3 as a power supply IC. More specifically, the power supply IC (IC chip 3 ) includes a voltage regulator 17 to reliably supply a power supply voltage to a load. The voltage regulator 17 includes the voltage input pad 3 a to which a direct voltage V DD from, for example a battery, is supplied, the voltage output pad 3 b , connected to the load, to which a voltage output V OUT is supplied to the load, the ground pad 3 c that is connected to a ground voltage GND, and the enable-terminal pad 3 d to which an enable signal CE is input. The voltage regulator 17 further includes a reference voltage generator 19 , a differential amplification circuit 21 , the driver transistor 3 f constituted by a positive channel metal oxide semiconductor (P-ch MOS) transistor, and a feedback resistance circuit 23 to generate a feedback voltage to a voltage supplied to the load. The circuits 19 , 21 , and 23 are formed on the analog circuit forming region 3 g shown in FIG. 5 .

The driver transistor 3 f is disposed between the voltage input pad 3 a and the voltage output pad 3 b . The reference voltage generator 19 and the differential amplification circuit 21 are connected between the voltage input pad 3 a and the ground pad 3 c . The feedback resistance circuit 23 includes resistors R 1 and R 2 that are connected in series between the voltage output pad 3 b and the ground pad 3 c . The enable-terminal pad 3 d is connected to the reference voltage generator 19 and the differential amplification circuit 21 . The enable-terminal pad 3 d is also connected to the ground pad 3 c via a resistor 25 . The resistor 25 is formed on the analog circuit forming region 3 g shown in FIG. 5 .

An output terminal of the differential amplification circuit 21 is connected to a gate terminal of the driver transistor 3 f . A reference voltage V REF generated in the reference voltage generator 19 is input to an inverting input terminal (−) of the differential amplification circuit 21 . A feed back voltage V FB generated in the feedback resistance circuit 23 is input to a non-inverting input terminal (+) of the differential amplification circuit 21 . The differential amplification circuit 21 controls an output of the driver transistor 3 f so that the feedback voltage V FB is identical to the reference voltage V REF .

In the present embodiment, since the voltage input lead 1 a and the voltage output lead 1 b are arranged at the edges of the lead array, in the printed circuit board 9 on which the semiconductor package 1 is mounted, the line widths of the voltage input wiring pattern 13 a that is connected to the voltage input lead 1 a and the voltage output wiring pattern 13 b that is connected to the voltage output lead 1 b can be wider than those of other wiring patterns 13 c and 13 d.

Since the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b have the line widths that are wider than those of other wiring patterns 13 c and 13 d on the printed circuit board 9 , a heat generated in the driver transistor 3 f can be effectively released via the voltage input pad 3 a and the voltage output pad 3 b , and the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b , compared to a configuration in which the line widths of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b are equal to or narrower than those of the wiring patterns 13 c and 13 d . Thus, heat radiation in the semiconductor package 1 in which the IC chip 3 including the driver transistor 3 is mounted on the leads 1 a , 1 b , 1 c , and 1 d using the flip chip bonding and is sealed with the resin can be improved.

Further, since the line widths of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b are wider than those of other wiring patterns 13 c and 13 d on the printed circuit board 9 , wiring resistance of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b can be minimized, which minimizes voltage drop caused by wiring resistances of the wiring patterns 13 a and 13 b.

Further, in the semiconductor package 1 , since the driver transistor 3 f of the IC chip 3 is disposed in contact with an outer edge of the element arrangement region 3 e , the heat generated in the driver transistor 3 f can be more easily transmitted to the lateral faces of the encapsulating resin 7 of the semiconductor package 1 , compared to a configuration in which the driver transistor of the IC chip is disposed not contacting the outer edge of the element arrangement region. Thus, heat radiation in the lateral faces of the encapsulating resin 7 can be improved in the semiconductor package 1 .

Second Embodiment

Next, a semiconductor package 1 - 1 of a second embodiment is described below with reference to FIGS. 8 and 9 . FIG. 8 is a plan view illustrating the semiconductor package 1 - 1 in an electronic component package 100 - 1 according to the second embodiment. In FIG. 8 , a driver transistor formed in an IC chip 3 - 1 is represented by alternate long and short broken lines, and figures of the bumps and the solder are omitted. FIG. 9 is a cross-sectional diagram of the semiconductor package 1 - 1 in the electronic component package 100 - 1 along a line B-B′ shown in FIG. 8 . Components in electronic component package 100 - 1 operating similarly to the components in the electronic component package 100 in FIGS. 1 through 7 are represented by identical numerals in FIGS. 8 and 9 .

In the semiconductor package 1 - 1 , the IC chip 3 - 1 are mounted on nine electrically separated leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n via the bump 5 . The leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n , collectively referred to as leads 27 , are formed by electrotyping and do not include a so-called “suspender lead”. Thus, the leads 27 can be formed so that film thicknesses of the leads are thinner than those of the leads in the lead frame that is formed by processing sheet metal. In the leads 27 formed by electrotyping, areas of the leads 27 in the IC chip mounting face (first face) are almost identical to areas of those in the exposure face (second face)(opposite to the IC chip mounting face) as illustrated in FIG. 9 . The IC chip 3 - 1 includes nine pads 3 a , 3 b , 3 h , 3 i , 3 j , 3 k , 3 l , 3 m , and 3 n and the driver transistor 3 f formed in the element arrangement region (figure is omitted). The pad 3 a functions as a voltage input pad to supply an input voltage to the driver transistor 3 f . The pad 3 b functions as a voltage output pad to which an output voltage from the driver transistor 3 f is supplied.

The driver transistor 3 f is disposed between the voltage input pad 3 a and the voltage output pad 3 b and is disposed in contact with an outer edge of the element arrangement region (not shown). In the present embodiment, the nine pads 3 a , 3 b , 3 h , 3 i , 3 j , 3 k , 3 l , 3 m , and 3 n are arranged in an array of three columns and three rows. Excluding the pad 3 j , the pads 3 a, 3 b , 3 h , 3 i , 3 k , 3 l , 3 m , and 3 n are arranged at edges of a pad array.

In the semiconductor package 1 - 1 , the nine pads 3 a , 3 b , 3 h , 3 i , 3 j , 3 k , 3 l , 3 m and 3 n are connected to the corresponding leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n via the bump 5 . In the present embodiment, the nine leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m, and 27 n are arranged in an array of three columns and three rows. Therefore, excluding the lead 27 j , the leads 27 a , 27 b , 27 h , 27 i , 27 k , 27 l , 27 m , and 27 n are arranged at edges of a lead array.

The leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n , the IC chip 3 - 1 , and bump 5 are sealed with encapsulating resin 7 - 1 . The lead potions 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l, 27 m , and 27 n are exposed outside a backside face of the encapsulating resin 7 - 1 positioned opposite to the IC chip mounting face.

As illustrated in FIG. 9 , the semiconductor package 1 - 1 is mounted on a printed circuit board 9 - 1 , which forms the electronic component package 100 - 1 . The printed circuit board 9 - 1 includes the insulative substrate 11 and wiring patterns 13 a , 13 b , 13 h , 13 i , 13 j , 13 k, 13 l , 13 m , and 13 n.

Upper ends of the wiring patterns 13 a , 13 b , 13 h , 13 i , 13 j , 13 k , 13 l , 13 m , and 13 n are disposed at positions corresponding to the leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n . The leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n are connected to the corresponding wiring patterns 13 a , 13 b , 13 h , 13 i , 13 j , 13 k , 13 l , 13 m , and 13 n via the solder 15 .

The line widths of the voltage input wiring pattern 13 a that is connected to the voltage input lead 1 a and the voltage output wiring pattern 13 b that is connected to the voltage output lead 1 b can be wider than those of other wiring patterns 13 h , 13 i , 13 j , 13 k , 13 l , 13 m , and 13 n . The wiring pattern 13 j connected to the lead 27 j formed at a center position in the lead array of the semiconductor package 1 - 1 is guided to the outside of a mounting region of the semiconductor package 1 - 1 through a gap between the wiring patterns 13 m and 13 n , and therefore a line width of the wiring pattern 13 j is narrower than those of other wiring patterns 13 h , 13 i , 13 k , 13 l , 13 m , and 13 n.

In the present embodiment, since the voltage input lead 27 a and the voltage output lead 27 b are provided at the edges of the lead array, in the printed circuit board 9 - 1 on which the semiconductor package 1 - 1 is mounted, the line widths of the voltage input wiring pattern 13 a that is connected to the voltage input lead 27 a and the voltage output wiring pattern 13 b that is connected to the voltage output lead 27 b can be wider than those of other wiring patterns 13 h , 13 i , 13 j , 13 k , 13 l , 13 m , and 13 n.

As a comparative example, it is assumed that the driver transistor 3 f is disposed between the pads 3 j and 3 b , the pad 3 j functions as a voltage input pad, and the pad 27 j functions as a voltage input pad in the IC chip 3 - 1 . Since the wiring pattern 13 j connected to the lead 27 j is guided to the outside of the mounting region of the semiconductor package 1 - 1 through a gap between the wiring patterns 13 m and 13 n , the line width of the wiring pattern 13 j cannot be wider. That is, if the lead pad 27 j provided at the center position in the lead array of the semiconductor package 1 - 1 functions as the voltage input pad or the voltage output pad, the line width of the voltage input wiring pattern or the voltage output wiring pattern cannot be wider than those of other wiring patterns. By contrast, the IC chip 3 - 1 of the present embodiment can overcome this problem.

Since the line widths of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b are wider than those of other wiring patterns 13 h , 13 i , 13 j , 13 k , 13 l , 13 m, and 13 n on the printed circuit board 9 - 1 , a heat generated in the driver transistor 3 f can be effectively released via the voltage input pad 3 a and the voltage output pad 3 b , the voltage input lead 27 a and the voltage output lead 27 b , and the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b , compared to a configuration in which the line widths of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b are equal to or narrower than those of the wiring patterns 13 h , 13 i , 13 j , 13 k , 13 l , 13 m , and 13 n . Thus, the heat radiation in the semiconductor package 1 - 1 in which the IC chip 3 - 1 including the driver transistor 3 f is mounted on the leads 27 a , 27 b , 27 h , 27 i , 27 j , 27 k , 27 l , 27 m , and 27 n by the flip chip bonding and is sealed with the resin can be improved.

Further, since the line widths of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b are wider than other wiring patterns 13 h , 13 i , 13 j , 13 k , 13 l , 13 m, and 13 n on the printed circuit board 9 - 1 , wiring resistance of the voltage input wiring pattern 13 a and the voltage output wiring pattern 13 b can be minimized, which minimizes voltage drop caused by wiring resistance of the wiring patterns 13 a and 13 b.

Further, in the semiconductor package 1 - 1 , since the driver transistor 3 f of the IC chip 3 - 1 is disposed in contact with the outer edge of the element arrangement region, the heat generated in the driver transistor 3 f can be more easily transmitted to lateral faces of the encapsulating resin 7 - 1 of the semiconductor package 1 - 1 , compared to the configuration in which the driver transistor 3 f of the IC chip is disposed not contacting the outer edge of the element arrangement region. Thus, heat radiation in the lateral faces of the encapsulating resin 7 - 1 can be improved in the semiconductor package 1 - 1 .

Third Embodiment

Next, a semiconductor package 1 - 2 according to a third embodiment is described below with reference to FIG. 10 . FIG. 10 is a plan view illustrating the semiconductor package 1 - 2 in an electronic component package 100 - 2 according to the third embodiment. Components in the electronic component package 100 - 2 operating similarly to the components in the electronic component package 100 - 1 in FIGS. 8 and 9 are represented by identical numerals in FIG. 10 . In the present embodiment, an IC chip 3 - 2 further includes a driver transistor 3 o in addition to components included in the IC chip 3 - 1 shown in FIGS. 8 and 9 .

The driver transistor 3 o is disposed between the voltage input pad 3 a and the pad 3 h and is disposed in contact with an outer edge of the element arrangement region. The pad 3 h functions as a voltage output pad to which an output voltage from the driver transistor 3 o is supplied. The voltage input pad 3 a is shared between the driver transistors 3 f and 3 o.

In a printed circuit board 9 - 2 , a line width of a wiring pattern 13 h - 2 connected to the voltage output pad 3 h is equal to that of the wiring pattern 13 b and is wider than those of the wiring patterns 13 i , 13 j , 13 k , 13 l , 13 m , and 13 n.

The configuration of the third embodiment can achieve effects similar to those of the electronic component package 100 - 1 described above with reference to FIGS. 8 and 9 . In addition, since the driver transistors 3 f and 3 o use the voltage input pad 3 a and the voltage input lead 27 in common, the IC chip 3 - 2 and the semiconductor package 1 - 2 can be more compact than a configuration in which the voltage input pad and the voltage input lead are provided respectively for two adjacent driver transistors 3 f and 3 o . In the printed circuit board 9 - 2 on which the semiconductor package 1 - 2 is mounted, although two wiring patterns are required if the voltage input pads and the voltage input leads are provided for the two adjacent driver transistors 3 f and 3 o , respectively, in the present embodiment, since the voltage input pad 3 a and the voltage input lead 27 are shared between the two adjacent driver transistors 3 f and 3 o , only a single voltage input wiring pattern is provided. Thus, the space for the wiring pattern for two voltage input wiring patterns can be eliminated and used instead for a wiring region. The voltage input wiring pattern 13 a can be made wider, thereby improving heat radiation.

Fourth Embodiment

Next, a semiconductor package 1 - 3 according to a fourth embodiment is described below. FIG. 11 is a plan view illustrating the semiconductor package 1 - 3 in an electronic component package 100 - 3 according to the forth embodiment. FIG. 12 is a cross-sectional diagram of the semiconductor package 1 - 3 in the electronic component package 100 - 3 along a line C-C′ shown in FIG. 11 . Components in electronic component package 100 - 3 operating similarly to the components in the electronic component package 100 in FIGS. 1 through 6 are represented by identical numerals in FIGS. 11 and 12 .

A horizontal size of an IC chip 3 - 3 according to the present embodiment is smaller than that of the IC chip 3 according to the first embodiment shown in FIGS. 1 through 6 , and an array pitch of the pads 3 a - 3 , 3 b - 3 , 3 c - 3 , and 3 d - 3 is smaller than that of the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 in the exposure face.

However, even if the horizontal size of the IC chip and the pitch of the array of the pads can be downsized so as to increase the number of IC chips cut from single wafer, the array pitch of the exposure face of the leads cannot be downsized due to layout limitations of the wiring pattern in the printed circuit board on which the semiconductor package is mounted.

In order to solve this problem, each of the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 includes the first face on which the IC chip is mounted and the second face (exposure) opposite the first face, the first face has a surface area larger than the second face, that is, the first face has a surface area larger than the second face. The leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 in the IC chip mounting face are laid out so as to correspond the pads 3 a - 1 , 3 b - 2 , 3 c - 3 , and 3 d - 3 , such that the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 in the IC chip mounting face are partially positioned beneath the pads 3 a - 3 , 3 b - 3 , 3 c - 3 , and 3 d - 3 , so that the IC chip 3 - 3 can be mounted on the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 using the flip chip bonding.

In the present embodiment, the pads 3 a - 3 , 3 b - 3 , 3 c - 3 , and 3 d - 3 are connected to the IC chip mounting face of the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 via the bump 5 , where layout positions of the pads 3 a - 3 , 3 b - 3 , 3 c - 3 , and 3 d - 3 are entirely different from the layout positions of the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 in the exposure face (second face). However, one, two, or three of the four pads 3 a - 3 , 3 b - 3 , 3 c - 3 , and 3 d - 3 may be connected to the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 , where the layout positions of the pads 3 a - 3 , 3 b - 3 , 3 c - 3 , and 3 d - 3 are different from that of the leads 1 a - 3 , 1 b - 3 , 1 c - 3 , and 1 d - 3 in the exposure face (second face), and the other pad(s) may be connected to the leads where the pad(s) is superimposed on the layout position(s) of the lead(s) in the exposure faces (second face) when viewed from above.

Herein, although the semiconductor package having the four leads and the pads is described in the present embodiment, a configuration of a semiconductor package in which five or greater leads and pads are provided is similar to that of the semiconductor package 1 - 3 . In this configuration, the semiconductor package includes at least one pad that is connected to the corresponding lead so that layout position of the pad is different from a layout position of the exposure face (second face) of the corresponding lead.

It is to be noted that the configuration of the present specification is not limited to that shown in FIGS. 1 through 12 . The number, shape, arrangement, and circuit configuration of the electronic device are not limited to the above-described embodiments, and various modifications and improvements in the material and shape of the developer regulator are possible without departing from the spirit and scope of the present invention.

For example, in the first embodiment shown in FIGS. 1 through 7 , the areas of the leads 1 a , 1 b , 1 c , and 1 d in the IC chip mounting face are greater than that in the exposure face. However, the configuration of the present specification is not limited to this embodiment, and the areas of the leads 1 a , 1 b , 1 c , and 1 d in the chip mounting face are equal to those in the exposure face. In addition, the leads formed by the electrotyping as described with reference to FIGS. 8 and 9 can be used in the semiconductor package 1 and 1 - 3 of the first and fourth embodiments shown in FIGS. 1 through 7 and 11 and 12 . The lead formed by processing the metal plate as described with reference to FIGS. 1 through 7 can be used in the semiconductor package 1 - 1 and 1 - 2 in the second and third embodiments shown in FIGS. 8 through 10 .

In the above-described embodiments, although the power supply IC including the voltage regulator is described as the IC chip installed in the semiconductor package, the IC chip in the present disclosure is not limited to this IC. The IC chip installed in the semiconductor package in the present specification can be adapted to an IC having any function including a driver transistor.

In addition, although the semiconductor package adapts a leadless type package, the semiconductor package of the present disclosure can be adapted to a semiconductor package in which leads are projected from an encapsulating resin.

Numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein.