Power supply unit

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-224925, filed on Oct. 4, 2010, the entire contents of which are incorporated herein by reference.

The present disclosure relates to a power supply unit mounted in a host device for supplying power to a client device connected to the host device through a cable.

FIG. 5 is a block diagram showing an exemplary power supply unit 100 of the related art. The power supply unit 101 is mounted in a host device 100 implemented according to the Universal Serial Bus (USB) standard, and supplies power to a client device 300 by using a cable 200 interposed therebetween. In addition to the power supply unit 101 , the host device 100 includes a protective switch 103 configured to connect/disconnect a power supply line from the host device 100 to the client device 300 , and a microcomputer 102 configured to control an ON/OFF operation of the protective switch 103 .

This type of power supply unit is disclosed in, for example, Japanese Patent Laid-Open Publication No. 1-110-225105.

In the power supply unit 101 according to the related art, in order to maintain an output voltage Vo 1 (which is an output voltage obtained from an upper stream side, i.e., power supply unit 101 side of the protective switch 103 ) output from the power supply unit 101 , at a predetermined target value, a voltage feedback control operation is performed. However, in the voltage feedback control operation, neither an output voltage Vo 1 ′ (which is an output voltage obtained from a lower stream side, i.e., cable 200 side of the protective switch 103 ) output from the host device 100 nor an output voltage Vo 2 eventually supplied to the client device 300 is considered.

Thus, in the power supply unit 101 according to the related art, when an output current Io supplied to the client device 300 from the host device 100 is increased, a voltage drop (Io×Ron) generated from an ON resistor Ron of the protective switch 103 and a voltage drop (Io×Rim) generated from a wiring resistor Rim of the cable 200 are increased. In addition, the output voltage Vo 2 (Vo 1 −Io×(Ron+Rim)) finally supplied to the client device 300 falls below a lower limit value of a USB standard range (see FIG. 6 ).

In light of the foregoing problems discovered by the inventors of the present application, the present disclosure provides some embodiments of a power supply unit capable of maintaining an output voltage finally supplied to a client device from a host device, within a predetermined standard range, without depending on the amount of an output current supplied from the host device to the client device.

According to one embodiment of the present disclosure, a power supply unit, which is mounted in a host device for supplying power to a client device through a cable interposed therebetween, includes an output unit configured to generate a first output voltage from an input voltage. The power supply unit also includes a controller configured to perform voltage feedback control on the output unit such that the first output voltage is maintained at a predetermined target value. Further, in the power supply unit, a first correction unit is provided to correct the voltage feedback control at the controller such that the first output voltage is increased as a second output voltage finally supplied to the client device gets lower, and a second correction unit configured to correct the voltage feedback control at the controller such that the first output voltage is increased as an output current supplied from the host device to the client device gets larger.

FIG. 1 is a block diagram showing an exemplary configuration of a power supply unit according to one embodiment of the present disclosure.

FIG. 2 is an IV correlation diagram showing a relationship between an output current Io and output voltages Vo 1 and Vo 2 .

FIG. 3 is a block diagram showing a first exemplary configuration of a first correction unit ADJ 1 and a second correction unit ADJ 2 .

FIG. 4 is a block diagram showing a second exemplary configuration of the first correction unit ADJ 1 and the second correction unit ADJ 2 .

FIG. 5 is a block diagram showing a related art example of a power supply unit.

FIG. 6 is an IV correlation diagram showing a relationship between an output current Io and output voltages Vo 1 to Vo 2 of the power supply unit shown in FIG. 5 .

FIG. 1 is a block diagram showing an exemplary configuration of a power supply unit according to one embodiment of the present disclosure. In this exemplary configuration, a power supply unit 1 is mounted in a host device 10 and supplies power to a client device 30 by using a cable 20 interposed therebetween. The host device 10 , the cable 20 , and the client device 30 are all implemented and coupled in series according to the Universal Serial Bus (USB) standard. Also, the host device 10 includes a microcomputer 2 which controls the overall operations of the host device 10 , in addition to the power supply device 1 .

The power supply unit 1 includes an N channel type metal oxide semiconductor (MOS) field effect transistor N 1 , a diode D 1 , an inductor L 1 , a condenser C 1 , resistors R 1 to R 4 , a sense resistor Rs, a switching controller CTRL, a first correction unit ADJ 1 , a second correction unit ADJ 2 , an error detection unit DET, and a filter unit FLT.

A drain of the transistor N 1 is connected to an application terminal of an input voltage Vi. A source of the transistor N 1 is connected to a cathode of the diode D 1 and a first terminal of the inductor L 1 . A gate of the transistor N 1 is connected to the switching controller CTRL. An anode of the diode D 1 is connected to a ground terminal. A second terminal of the inductor L 1 is connected to an application terminal of a first output voltage Vo 1 through the sense resistor Rs interposed therebetween. A first terminal of the condenser C 1 is connected to the application terminal of the first output voltage Vo 1 . A second terminal of the condenser C 1 is connected to the ground terminal. A first terminal of the resistor R 1 is connected to the application terminal of the first output voltage Vo 1 . A second terminal of the resistor R 1 is connected to a first terminal of the resistor R 2 . A second terminal of the resistor R 2 is connected to the ground terminal. A connection node of the resistor R 1 and the resistor R 2 is connected to the switching controller CTRL, as an application terminal of a first feedback voltage Vfb 1 . A first terminal of the resistor R 3 is connected to an application terminal of a second output voltage Vo 2 . A second terminal of the resistor R 3 is connected to a first terminal of the resistor R 4 . A second terminal of the resistor R 4 is connected to the ground terminal. A connection node of the resistor R 3 and the resistor R 4 is connected to the first correction unit ADJ 1 , as an application terminal of a second feedback voltage Vfb 2 , through the filter unit FLT interposed therebetween. Both ends of the sensor resistor Rs are connected to the second correction unit ADJ 2 .

Also, an output unit for stepping down the input voltage Vi to generate the first output voltage Vo 1 is formed by the transistor N 1 , the diode D 1 , the inductor L 1 , and the condenser C 1 . In other words, the output unit of the power supply unit 1 includes the output transistor N 1 connected between the application terminal of the input voltage Vi and the output terminal of the first output voltage Vo 1 , and drives the output transistor N 1 based on an instruction from the switching controller CTRL to step down the input voltage Vi to thereby generate the output voltage Vo 1 . However, the configuration of the output unit is not limited thereto and, for example, a P channel type MOS field effect transistor may be used as the output transistor, or a synchronous rectifying transistor may be used instead of the diode D 1 .

The switching controller CTRL performs a voltage feedback control on the output unit (N 1 , D 1 , L 1 , C 1 ) such that the first output voltage Vo 1 is consistent with a predetermined target value. More specifically, the switching controller CTRL monitors the first feedback voltage Vfb 1 (which is a divided voltage of the first output voltage Vo 1 ) drawn from the connection node of the resistor R 1 and the resistor R 2 , and generates a gate signal of the transistor N 1 to increase an ON duty (Ton/T, namely, the ratio of ON period Ton of the transistor N 1 to a predetermined switching driving period T) of the transistor N 1 when the first output voltage Vo 1 is lower than the predetermined target value, and decrease the ON duty of the transistor N 1 as the first output voltage Vo 1 approaches the predetermined target value.

As used herein, the first output voltage Vo 1 indicates an output voltage which is obtained from an upper stream side of the cable 20 (the connector 21 side close to the host device 10 ) and output from the power supply unit 1 . Meanwhile, the second output voltage Vo 2 indicates an output voltage which is obtained from a lower stream side of the cable 20 (the connector 23 side close to the client device 30 ) and finally supplied to the client device 30 .

Since a cable main body 22 includes the wiring resistor Rim, the second output voltage Vo 2 has a lower voltage value, by a voltage drop corresponding to the product of the output current Io supplied to the client device 30 from the host device 10 and the wiring resistor Rim of the cable main body 22 , than the output voltage Vo 1 (Vo 2 =Vo 1 −Io×Rim).

Thus, the power supply unit 1 according to the present embodiment includes the first correction unit ADJ 1 and the second correction unit ADJ 2 configured to correct the voltage feedback control at the switching controller CTRL, so as to supplement the voltage drop.

The first correction unit ADJ 1 monitors the second feedback voltage Vfb 2 (which is a divided voltage of the second output voltage Vo 2 ) which is drawn from the connection node of the resistor R 3 and the resistor R 4 and input through the filter unit FLT, and corrects the voltage feedback control at the switching controller CTRL such that the first output voltage Vo 1 is increased as the second output voltage Vo 2 finally supplied to the client device 30 becomes lower.

Also, the second correction unit ADJ 2 monitors a voltage Vs across the sensor resistor Rs and corrects the voltage feedback control at the switching controller CTRL such that the first output voltage Vo 1 is increased as the output current Io supplied to the client device 30 from the host device 10 gets higher.

In this manner, the power supply unit 1 including the first correction unit ADJ 1 and the second correction unit ADJ 2 can appropriately supplement the voltage drop (Io×Rim) generated from the wiring resistor Rim of the cable 20 , so that the second output voltage Vo 2 finally supplied to the client device 30 can be maintained to be within a predetermined USB standard range, without depending on the amount of the output current Io supplied from the host device 10 to the client device 30 (see FIG. 2 ).

In the configuration in which only the voltage feedback control is performed based on the second output voltage Vo 2 , tolerance to responsiveness or noise with respect to a load change is insufficient. Also, in the configuration in which only the current feedback control is performed based on the output current Io, the second output voltage Vo 2 is not considered, similar to the power supply unit of the related art in FIG. 5 . Thus, in order to realize high responsiveness with respect to the load change and maintain the second output voltage Vo 2 reliably within the USB standard range, it may be preferred in some embodiments to employ a configuration in which the voltage feedback control based on the first output voltage Vo 1 is performed along a central axis and then corrections are independently performed on the voltage feedback control based on the respective monitoring results of the second output voltage Vo 2 and the output current Io.

In addition, the power supply unit 1 according to the present embodiment further includes the filter unit FLT configured to remove a noise component from the second feedback voltage Vfb 2 and output the same to the first correction unit ADJ 1 . With such a configuration, even when a noise component overlaps with the second output voltage Vo 2 (and the second feedback voltage Vfb 2 generated by dividing the second output voltage Vo 2 ) returned to the host device 10 from the client device 30 through the cable 20 interposed therebetween, the noise component can be appropriately removed, so correction precision at the first correction unit ADJ 1 can be enhanced.

Further, the power supply unit 1 according to the present embodiment may include the error detection unit DET configured to detect an error (overvoltage, reduced voltage, overcurrent, high temperature, or the like) of the power supply unit 1 , generate an error detection signal, and output the generated error detection signal outside of the power supply unit 1 (to microcomputer 2 in FIG. 1 ). With such a configuration, when the power supply unit 1 has a certain error, corresponding information can be provided to the microcomputer 2 .

Also, in the power supply unit 1 according to the present embodiment, the switching controller CTRL is configured to forcibly turn off the output transistor N 1 when an error protection signal is received from outside of the power supply unit 1 (from microcomputer 2 in FIG. 1 ). With such a configuration, the protective switch 103 which was required in the related art example of FIG. 5 can be eliminated, and thus, the voltage drop (Io×Ron) generated in the ON resistor Ron of the protective switch 103 can be resolved.

Furthermore, in the power supply unit 1 according to the present embodiment, the error detection unit DET is configured to output the error detection signal also to the switching controller CTRL, and the switching controller CTRL is configured to forcibly turn off the output transistor N 1 even when the error detection signal is received from the error detection unit DET. With such a configuration, when the power supply unit 1 has a certain error, the operation of the power supply unit 1 can be quickly stopped without having to wait for an instruction from the microcomputer 2 .

<First Configuration Example of First Correction Unit and Second Correction Unit>

FIG. 3 is a block diagram showing a first exemplary configuration of the first correction unit ADJ 1 and the second correction unit ADJ 2 . In the first exemplary configuration, both the first correction unit ADJ 1 and the second correction unit ADJ 2 are included in the switching controller CTRL.

The switching controller CTRL includes an error amplifier ERR, a reference voltage generation unit E 1 , a pulse width modulation signal generation unit PWM, a driver DRV, an operational amplifier AMP, and an adder ADD. A non-inverting input terminal (+) of the error amplifier ERR is connected to an application terminal (a positive electrode terminal of the reference voltage generation unit E 1 ) of a reference voltage Vref. A first inverting input terminal (−) of the error amplifier ERR is connected to an application terminal of the first feedback voltage Vfb 1 . A second inverting input terminal (−) of the error amplifier ERR is connected to an application terminal of the second feedback voltage Vfb 2 . An output terminal of the error amplifier ERR is connected to a first input terminal of the adder ADD. A non-inverting input terminal (+) of the operational amplifier AMP is connected to a high potential terminal (one end at the inductor L 1 side) of the sense resistor Rs. An inverting input terminal (−) of the operational amplifier AMP is connected to a low potential terminal (the other end at the condenser C 1 side) of the sensor resistor Rs. An output terminal of the operational amplifier AMP is connected to a second input terminal of the adder ADD. An output terminal of the adder ADD is connected to the pulse width modulation signal generation unit PWM.

The error amplifier ERR amplifies a difference between a lower value of the first and second feedback voltages Vfb 1 and Vbf 2 , and the reference voltage Vref to generate an error signal S 1 . In other words, the first correction unit ADJ 1 is configured with the error amplifier ERR, and the second feedback voltage Vfb 2 , instead of the first feedback voltage Vfb 1 , is input to an amplification terminal of the error amplifier ERR when the second feedback voltage Vfb 2 is lower than the first feedback voltage Vfb 1 . With such a configuration, when the second output voltage Vo 2 is lower than the first output voltage Vo 1 , a greater error signal S 1 is generated to make the second output voltage Vo 2 consistent with the reference voltage Vref, so the first output voltage Vo 1 can be raised and the voltage drop (Io×Rim) generated from the wiring resistor Rim of the cable 20 can be appropriately supplemented.

The operational amplifier AMP amplifies the voltage Vs (which is a voltage dependent on the output current Io) across the sensor resistor Rs to generate a correction signal S 2 , and outputs the correction signal S 2 to the adder ADD. The adder ADD adds the correction signal S 2 and the error signal S 1 to generate an added signal S 3 , and outputs the added signal S 3 to the pulse width modulation signal generation unit PWM. Namely, the second correction unit ADJ 2 is formed by the operational amplifier AMP and the adder ADD, and serves to increase the error signal S 1 as the output current Io is increased. With such a configuration, since the added signal S 3 (=S 1 +S 2 ) input to the pulse width modulation signal generation unit PWM is increased as the output current Io is increased, the first output voltage Vo 1 can be increased. And the voltage drop (Io×Rim) generated from the wiring resistor Rim of the cable 20 can be appropriately supplemented.

The pulse width modulation signal generation unit PWM compares the added signal S 3 and a predetermined slope signal to generate a pulse width modulation signal S 4 , and then outputs the pulse width modulation signal S 4 to the driver DRV. Meanwhile, as the added signal S 3 (=S 1 +S 2 ) gets larger, a high level period Ton occupied in the switching driving period T of the pulse width modulation signal S 4 , i.e., ON duty (Ton/T) of the transistor N 1 , is increased.

The driver DRV generates a gate signal S 5 of the transistor N 1 based on the pulse width modulation signal S 4 , and drives an ON/OFF operation of the transistor N 1 .

In this manner, in the switching controller CTRL of the present exemplary configuration, a control signal generation unit is formed by the pulse width modulation signal generation unit PWM and the driver DRV to generate a gate signal S 5 of the transistor N 1 such that the error signal S 1 is reduced.

<Second Configuration Example of First Correction Unit and Second Correction Unit>

FIG. 4 is a block diagram showing a second exemplary configuration of the first correction unit ADJ 1 and the second correction unit ADJ 2 . Also, in the second exemplary configuration, the first correction unit ADJ 1 and the second correction unit ADJ 2 are included in the switching controller CTRL.

The switching controller CTRL includes the error amplifier ERR, the reference voltage generation unit E 1 , the pulse width modulation signal generation unit PWM, the driver DRV, and the operational amplifier AMP. Compared with the foregoing first exemplary configuration, the adder ADD is excluded.

The non-inverting input terminal (+) of the error amplifier ERR is connected to the application terminal (a positive electrode terminal of the reference voltage generation unit E 1 ) of the reference voltage Vref. An inverting input terminal (−) of the error amplifier ERR is connected to the application terminal of the first feedback voltage Vfb 1 . An output terminal (−) of the error amplifier ERR is connected to the pulse width modulation signal generation unit PWM. The non-inverting input terminal (+) of the operational amplifier AMP is connected to the high potential terminal (one end at the inductor L 1 side) of the sense resistor Rs. The inverting input terminal (−) of the operational amplifier AMP is connected to the low potential terminal (the other end at the condenser C 1 side) of the sensor resistor Rs. A voltage control terminal of the reference voltage generation unit E 1 is connected to the application terminal of the second feedback voltage Vfb 2 and the output terminal of the operational amplifier AMP.

The error amplifier ERR amplifies a difference between the first feedback voltage Vfb 1 and the reference voltage Vref to generate an error signal S 1 . The pulse width modulation signal generation unit PWM compares the error signal S 1 and a predetermined slope signal to generate a pulse width modulation signal S 4 and outputs the pulse width modulation signal S 4 to the driver DRV. Meanwhile, as the magnitude of the error signal S 1 becomes larger, the high level period Ton occupied in the switching driving period T of the pulse width modulation signal S 4 , i.e., ON duty (Ton/T) of the transistor N 1 , is increased. The driver DRV generates a gate signal S 5 of the transistor N 1 based on the pulse width modulation signal S 4 , and drives an ON/OFF operation of the transistor N 1 .

The reference voltage generation unit E 1 operates to increase the reference voltage Vref as the second feedback voltage Vref 2 becomes lower. Namely, the first correction unit ADJ 1 is included in the switching controller CTRL as a function of the reference voltage generation unit E 1 . With such a configuration, as the second output voltage Vo 2 becomes lower, the reference voltage Vref is increased and the greater error signal S 1 is generated, such that the first output voltage Vo 1 can be raised up and the voltage drop (Io×Rim) generated from the wiring resistor Rim of the cable 20 can be appropriately supplemented.

The operational amplifier AMP amplifies the voltage Vs (which is a voltage depending on the output current Io) across the sensor resistor Rs to generate the correction signal S 2 , and outputs the correction signal S 2 to the reference voltage generation unit E 1 . The reference voltage generation unit E 1 operates to increase the reference voltage Vref as the correction signal S 2 becomes larger. Namely, the second correction unit ADJ 2 is formed by the operational amplifier AMP and the reference voltage generation unit E 1 and serves to increase the reference voltage Vref and the error signal S 1 as the output current Io becomes larger. With such a configuration, since the error signal S 1 input to the pulse width modulation signal generation unit PWM is increased as the output current Io becomes larger, the first output voltage Vo 1 can be increased and the voltage drop (Io×Rim) generated from the wiring resistor Rim of the cable 20 can be appropriately supplemented.

<Other Modifications>

In the above embodiments, the configurations which apply the present disclosure to the step-down power supply unit for generating a desired output voltage by stepping down an input voltage have been described by way of example, but the present disclosure is not limited thereto and can be widely applied to a step-up or step-up/step-down power supply unit.

Additionally, in the above embodiments, the configurations which apply the present disclosure to the switching regulator type power supply unit are described by way of example, but the present disclosure is not limited thereto and can be also widely applied to a series regulator type or charge pump type power supply unit.

Further, in the above embodiments, the configurations of monitoring the output current Io by using the sensor resistor Rs are described by way of example, but the present disclosure is not limited thereto and, for example, a configuration of monitoring a voltage drop in the transistor N 1 may be employed.

The power supply unit according to the present disclosure can be appropriately used as a power supply unit which is mounted in a host device based on, for example, a USB standard and supplies power to a client device through a cable interposed therebetween.

According to the embodiments of the present disclosure, a power supply unit capable of maintaining an output voltage finally supplied to a client device from a host device, within a predetermined standard range, without depending on the amount of an output current supplied from the host device to the client device, is provided.

Also, the configuration of the embodiments provided in the present disclosure may be variably modified, within a scope which does not depart from the main purport of the present disclosure, in addition to the foregoing embodiments. In other words, the embodiments are illustrative in every aspect and considered not to be limited, and it is to be understood that the technical scope of the present disclosure is not defined by the description of the embodiments but by the scope of claims and include every modification belonging to the meanings and scope equivalent to the scope of claims.