Apparatus for controlling bleed switch, power supply, and method for driving power supply

This application claims priority to and the benefit of Korean Patent Application No. 10-2011-0002378 filed in the Korean Intellectual Property Office on Jan. 10, 2011, the entire contents of which are incorporated herein by reference.

(a) Field of the Invention

The present invention relates to a power supply. In particular, the present invention relates to a power supply including a bleed switch for an LED lamp which is controlled by a TRIAC dimmer.

(b) Description of the Related Art

The TRIAC dimmer is widely used for controlling a current provided to a load. Referring to FIG. 1 and FIG. 2 , the TRIAC dimmer will be described.

FIG. 1 is a schematic diagram representing a prior circuit including a TRIAC dimmer, and FIG. 2 is a waveform diagram showing an operation of the TRIAC dimmer.

As shown in FIG. 1 , the TRIAC dimmer 10 is connected in series to an AC power source Vac and a load 20 . The TRIAC dimmer 10 includes a variable resistor R 1 , a resistor R 2 , a capacitor C 1 , a DIAC, and a TRIAC.

The AC power source Vac provides a voltage source with an AC waveform as shown in FIG. 2 (A). An RC network consisting of the variable resistor R 1 , the resistor R 2 , and the capacitor C 1 delays turn-on of the TRIAC until a voltage of the capacitor C 1 reaches a trigger voltage of the DIAC. From this, two terminals of the load 20 are provided with a voltage with a waveform as shown in FIG. 2 (B).

In the other hand, if resistance of the variable resistor R 1 increases, the delay of turn-on of the TRIAC also increases. That is, because on-time of the TRIAC reduces, an average power provided to the load 20 reduces.

In this way, when the TRIAC dimmer 10 is used, a power provided to the load 20 can be controlled by controlling a value of the variable resistor R 1 .

In particular, in a case that the load 20 corresponds to an AC-DC converter and an LED lamp, if on-time of the TRIAC is shorter than a certain time, flicker can be caused. A constant current is required to continuously flow to prevent this problem. This current is called a bleed current.

However, efficiency of the AC-DC converter worsens because of the continuous current.

Embodiments of the present invention provide a power supply having advantages of improving efficiency.

An embodiment of the present invention provides a device for controlling a bleed switch, including: a first controller for generating a first control signal having a first level in a first time duration and having a second level in a second time duration; and a second controller for generating a second control signal by using the first control signal and providing the second control signal to the bleed switch, wherein the bleed switch is turned off in the first time duration, and wherein the bleed switch is turned on in the second time duration.

Magnitude of a current of a power switch in the first time duration may be larger than magnitude of a current of the power switch in the second time duration.

The second control signal may have a third level in the first time duration, have a fourth level in a third time duration within the second time duration, and have a fifth level in a fourth time duration within the second time duration.

Magnitude of a current of the power switch in the third time duration may be larger than magnitude of a current of the power switch in the fourth time duration.

Magnitude of a current of the bleed switch in the fourth level may be smaller than magnitude of a current of the bleed switch in the fifth level.

The second controller may include a sampler for sampling a voltage corresponding to a current of the power switch to output a sampling signal; an inverter for inverting the sampling signal to generate an inverted signal; and a third controller for generating the second control signal by using the first control signal and the inverted signal.

The third controller may include a clock generator for generating a clock signal by using a control signal of the power switch; a tracker for generating a tracking signal, wherein the tracking signal has a third level when the first control signal has the first level and has a level of the sampling signal corresponding to an edge of the clock signal when the first control signal has the second level; and an amplifier for amplifying the tracking signal to generate the second control signal.

The sampling signal may have a level corresponding to a current of the power switch just before the power switch is turned off when a condition of the power switch corresponds to a turn-off.

The sampling signal may have a level corresponding to a current of the power switch when a condition of the power switch corresponds to a turn-on.

Another embodiment of the present invention provides a power supply, including: a TRIAC dimmer; and an AC-DC converter connected to the TRIAC dimmer, wherein the AC-DC converter includes a power switch; a bleed switch; and a bleed switch controller for turning off the bleed switch in a first time duration and turning on the bleed switch in a second time duration.

Magnitude of a current of the power switch in the first time duration may be larger than magnitude of a current of the power switch in the second time duration.

The bleed switch controller may control the bleed switch so that magnitude of a current of the bleed switch in a third time duration within the second time duration is smaller than magnitude of a current of the bleed switch in a fourth time duration within the second time duration.

Magnitude of a current of the power switch in the third time duration may be larger than magnitude of a current of the power switch in the fourth time duration.

Yet another embodiment of the present invention provides a method of driving a power supply of which consumption power is controlled by a TRIAC dimmer, wherein the power supply includes a bleed switch, the method including: generating a first control signal having a first level in a first time duration and having a second level in a second time duration; generating a second control signal by using the first control signal; and providing the second control signal to the bleed switch, wherein the bleed switch is turned off in the first time duration, and wherein the bleed switch is turned on in the second time duration.

Magnitude of a current of a power switch in the first time duration may be larger than magnitude of a current of the power switch in the second time duration.

The second control signal may have a third level in the first time duration, have a fourth level in a third time duration within the second time duration, and have a fifth level in a fourth time duration within the second time duration.

Magnitude of a current of the power switch in the third time duration may be larger than magnitude of a current of the power switch in the fourth time duration.

Magnitude of a current of the bleed switch in the fourth level may be smaller than magnitude of a current of the bleed switch in the fifth level.

generating the second control signal may include generating a sampling signal, wherein the sampling signal has a level corresponding to a current of the power switch just before the power switch is turned off when a condition of the power switch corresponds to a turn-off and has a level corresponding to a current of the power switch when a condition of the power switch corresponds to a turn-on; inverting the sampling signal to generate an inverted signal; generating a clock signal by using a control signal of the power switch; generating a tracking signal, wherein the tracking signal has a third level when the first control signal has the first level, and has a level of the sampling signal corresponding to an edge of the clock signal when the first control signal has the second level; and amplifying the tracking signal to generate the second control signal.

FIG. 1 is a schematic diagram representing a prior circuit including a TRIAC dimmer.

FIG. 2 is a waveform diagram showing an operation of the TRIAC dimmer.

FIG. 3 is a schematic diagram representing a circuit including an AC-DC converter according to an embodiment of the present invention.

FIG. 4 is a schematic diagram representing a bleed switch controller and a bleed switch circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram representing a bleed switch controller and a bleed switch circuit according to another embodiment of the present invention.

FIG. 6 is a schematic diagram representing a circuit of a digital controller according to an embodiment of the present invention.

FIG. 7 is a schematic diagram representing a circuit of an analog controller according to an embodiment of the present invention.

FIG. 8 is a waveform diagram showing an operation of a bleed switch controller according to an embodiment of the present invention.

In the following detailed description, only certain embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

Throughout this specification and the claims that follow, when it is described that an element is “connected” to another element, the element may be “directly connected” to the other element or “electrically connected” to the other element through a third element.

In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Next, referring to FIG. 3 to FIG. 8 , a power supply according to an embodiment of the present invention will be described.

FIG. 3 is a schematic diagram representing a circuit including an AC-DC converter according to an embodiment of the present invention.

As shown in FIG. 3 , the AC-DC converter 30 according to an embodiment of the present invention has an input terminal connected in series to the AC power source Vac and a TRIAC dimmer 10 , and an output terminal connected to a load RL.

The AC-DC converter 30 includes a bridge diode BD, an input capacitor C 2 , a bleed switch circuit 200 , a bleed switch controller 100 , a power switch T 1 , a resistor R 3 , a transformer TX, and a diode D 1 .

The bridge diode BD consists of four diodes, and has two input terminals that are connected to the AC power source Vac and the TRIAC dimmer 10 , respectively, and two output terminals outputting a rectified AC voltage V+.

The input capacitor C 2 is connected to the rectified AC voltage V+, stabilizes the rectified AC voltage V+, and reduces electromagnetic interference (EMI).

The bleed switch controller 100 generates a bleed switch control signal Vg by using a source voltage V 1 of the power switch T 1 .

The transformer TX includes a primary coil Co 1 and a secondary coil Co 2 . One terminal of the primary coil Co 1 is connected to one of two output terminals of the bridge diode BD, and the other terminal of the primary coil Co 1 is connected to a drain electrode of the power switch T 1 . One terminal of the secondary coil Co 2 is connected to an anode of the diode D 1 . One terminal of the load RL is connected to a cathode of the diode D 1 , and the other terminal of the load RL is connected to the other terminal of the secondary coil Co 2 .

A gate electrode of the power switch T 1 is provided with a power switch control signal Vout, and a source electrode of the power switch T 1 is connected to one terminal of the resistor R 3 .

Next, referring to FIG. 4 and FIG. 5 , a bleed switch controller 100 and a bleed switch circuit 200 according to an embodiment of the present invention will be described. In particularly, the bleed switch controller 100 as shown in FIG. 4 and FIG. 5 can be embodied by one integrated circuit, but it is unnecessary to limit the present invention like this.

FIG. 4 is a schematic diagram representing a bleed switch controller and a bleed switch circuit according to an embodiment of the present invention.

As shown in FIG. 4 , the bleed switch controller 100 includes a digital controller 120 and an analog controller 130 , and the bleed switch circuit 200 includes a resistor R 11 , a high voltage switch Ta, and a bleed resistor R BLEED .

The digital controller 120 generates a bleed switch on-off control signal Vd. The analog controller 130 with the source voltage V 1 of the power switch T 1 and the bleed switch on-off control signal Vd as inputs generates the bleed switch control signal Vg.

According to the embodiment of FIG. 4 , the high voltage switch Ta has a drain electrode connected to one terminal of the resistor R 11 , a gate electrode connected to the bleed switch control signal Vg, and a source electrode connected to one terminal of the bleed resistor R BLEED . The resistor R 11 has one terminal connected to the drain electrode of the high voltage switch Ta, and the other terminal connected to the rectified AC voltage V+.

FIG. 5 is a schematic diagram representing a bleed switch controller and a bleed switch circuit according to another embodiment of the present invention.

As shown in FIG. 5 , the bleed switch controller 100 includes a digital controller 120 , an analog controller 130 , a low voltage NMOS transistor Tb, and a bleed resistor R BLEED . In this case, to prevent the low voltage NMOS transistor Tb from being provided with a high voltage, a bleed switch circuit 200 having a high voltage switch Tc, a resistor R 21 , a resistor R 22 , a zener diode D 21 , and a capacitor C 21 is connected to the low voltage NMOS transistor Tb.

The digital controller 120 generates the bleed switch on-off control signal Vd. The analog controller 130 with the source voltage V 1 of the power switch T 1 and the bleed switch on-off control signal Vd as inputs generates the bleed switch control signal Vg.

The low voltage NMOS transistor Tb according to the embodiment of FIG. 5 has a drain electrode connected to a source electrode of the high voltage switch Tc, a gate electrode connected to the bleed switch control signal Vg, and a source electrode connected to one terminal of bleed resistor R BLEED . The high voltage switch Tc has a drain electrode connected to one terminal of the resistor R 21 , a gate electrode connected to one terminal of the capacitor C 21 , and the source electrode connected to the drain electrode of the low voltage NMOS transistor Tb. The resistor R 21 has one terminal connected to the source electrode of the high voltage switch Tc and the other terminal connected to the rectified AC voltage V+. The resistor R 22 has one terminal connected to one terminal of the capacitor C 21 and the other terminal connected to the rectified AC voltage V+. The capacitor C 21 has one terminal connected to the gate electrode of the high voltage switch Tc and the other terminal connected to ground. The zener diode D 21 has an anode connected to one terminal of capacitor 21 and a cathode connected to ground.

Next, referring to FIG. 6 , the bleed switch controller 100 according to an embodiment of the present invention will be described.

FIG. 6 is a schematic diagram representing a circuit of a digital controller according to an embodiment of the present invention.

The digital controller 120 generates the bleed switch on-off control signal Vd. For example, the bleed switch on-off control signal Vd can have two levels. If the bleed switch on-off control signal. Vd corresponds to one of two levels, the bleed switch circuit 200 is turned on. Otherwise, if the bleed switch on-off control signal Vd corresponds to the other one of two levels, the bleed switch circuit 200 can be turned off. In an embodiment of the present invention, if the bleed switch on-off control signal Vd corresponds to the high level, the bleed switch circuit 200 is turned off, which will be described below.

As shown in FIG. 6 , the digital controller 120 includes a transistor T 2 , a comparator U 1 a , a NOT gate U 1 b , an AND gate U 1 c , a counter U 1 d , a comparator U 1 e , a short pulse trigger U 1 f , a NOT gate U 1 g , an AND gate U 1 h , a latch U 1 i , and a NAND gate U 1 j.

The comparator U 1 a has a non-inverted terminal (+) connected to a reference voltage CS_REF, an inverted terminal (−) connected to a sampling signal Vs outputted by the analog controller 130 , and an output terminal. The NOT gate U 1 b has an input terminal connected to the power switch control signal Vout and an output terminal. The AND gate U 1 c has two input terminals and an output terminal. The two input terminals of the AND gate U 1 c are connected to the output terminal of the comparator U 1 a and the output terminal of the NOT gate U 1 b , respectively. The counter U 1 d has an input terminal connected to the output terminal of the AND gate U 1 c , a reset terminal connected to an output terminal of a NOT gate U 1 h , and an output terminal. The transistor T 2 has a drain electrode connected to the rectified AC voltage V+, a gate electrode connected to ground, and a source electrode. The comparator U 1 e has a non-inverted terminal (+) connected to the source electrode of the transistor T 2 , an inverted terminal (−) connected to a reference voltage V+_REF, and an output terminal. The short pulse trigger U 1 f has an input terminal connected to the output terminal of the comparator U 1 e and an output terminal. The NOT gate U 1 g has an input terminal connected to the output terminal of the short pulse trigger U 1 f and an output terminal. The AND gate U 1 h has two input terminals and an output terminal. The two input terminals of the AND gate U 1 h are connected to the output terminal of the counter U 1 d and the output terminal of NOT gate U 1 g , respectively. The latch U 1 i has a set terminal S connected to the output terminal of the AND gate U 1 h , a reset terminal R connected to the output terminal of the short pulse trigger U 1 f , and an output terminal Q. The NAND gate U 1 j has two input terminals and an output terminal. The two input terminal of the NAND gate U 1 j are connected to the output terminal Q of the latch U 1 i and the output terminal of the comparator U 1 e , respectively. The output terminal of the NAND gate U 1 j outputs the bleed switch on-off control signal Vd. An operation of the digital controller 120 will be described below.

FIG. 7 is a schematic diagram representing a circuit of an analog controller according to an embodiment of the present invention.

The analog controller 130 with the source voltage V 1 of the power switch T 1 and the bleed switch on-off control signal Vd as inputs generates the bleed switch control signal Vg.

As shown in FIG. 7 , the analog controller 130 according to an embodiment of the present invention includes a low-pass filter 131 a , an analog buffer 131 b , a sampler 132 , an inverting amplifier 133 , a tracker 134 , an amplifier 135 , and a tracking clock signal generator 136 .

The low-pass filter 131 a low-pass-filters the source voltage V 1 of the power switch T 1 to output a filtered signal Vcs. The low-pass filter 131 a can be used for remove a noise of the source voltage V 1 of the power switch T 1 . The low-pass filter 131 a according to an embodiment of the present invention includes a resistor R 4 and a capacitor C 3 . The resistor R 4 has one terminal connected to the source electrode of the power switch T 1 and the other terminal connected to one terminal of the capacitor C 3 . The capacitor C 3 has one terminal connected to the other terminal of the resistor R 4 and the other terminal connected to ground. The one terminal of the capacitor C 3 outputs the filtered signal Vcs.

The analog buffer 131 b can be used so that a change of impedance does not cause a change of the filtered signal Vcs. The analog buffer 131 b includes an operational (OP) amplifier U 4 . The OP amplifier U 4 has a non-inverted terminal (+) connected to the filtered signal Vcs, an inverted terminal (−) connected to the output terminal of the OP amplifier U 4 , and an output terminal outputting a buffered signal.

The sampler 132 samples an output voltage of the analog buffer 131 to generate the sampling signal Vs. The sampler 132 includes a transistor T 3 , a resistor R 6 , and a capacitor C 4 . The transistor T 3 has a drain electrode connected to the output terminal of the OP amplifier U 4 and a gate electrode connected to the power switch control signal Vout. The resistor R 6 has one terminal connected to a source electrode of the transistor T 3 and the other terminal connected to one terminal of the capacitor T 4 . The capacitor T 4 has one terminal outputting the sampling signal Vs and the other terminal connected to ground.

The inverting amplifier 133 inverts a phase of the sampling signal Vs to output an inverted sampling signal. The inverting amplifier 133 includes an OP amplifier U 5 , a transistor T 4 , a resistor Ra, and a resistor Rb. The OP amplifier U 5 has a non-inverted terminal (+) provided with the sampling signal Vs, an inverted terminal (−) connected to a source electrode of the transistor T 4 , and an output terminal connected to a gate electrode of the transistor T 4 . The transistor T 4 has a drain electrode connected to one terminal of the resistor Ra and outputting the inverted sampling signal, a gate electrode connected to the output terminal of the OP amplifier U 5 , and a source electrode connected to one terminal of the resistor Ra. The resistor Ra has one terminal connected to the drain electrode of the transistor T 4 and the other terminal connected to a voltage Vsource. The resistor Rb has one terminal connected to the source electrode of the transistor T 4 and the other terminal connected to ground.

The tracking clock signal generator 136 generates a tracking clock signal Vt_clk for tracking by using the power switch control signal Vout.

The tracker 134 with the tracking clock signal Vt_clk, the inverted sampling signal outputted by the inverting amplifier 133 , and the bleed switch on-off control signal Vd as inputs outputs a tracking signal Vt. The tracker 134 includes a transistor T 5 , a transistor T 6 , a resistor R 7 , and a capacitor C 5 . The transistor T 5 has a drain electrode connected to the drain electrode of the transistor T 4 , a gate electrode connected to the tracking clock signal Vt_clk, and a source electrode connected to one terminal of the resistor R 7 . The resistor R 7 has one terminal connected to the source electrode of the transistor T 5 , and the other terminal connected to one terminal of the capacitor C 5 and outputting the tracking signal Vt. The transistor T 6 has a drain electrode connected to one terminal of the capacitor C 5 , a gate electrode connected to the bleed switch on-off control signal Vd, and a source electrode connected to ground. The capacitor C 5 has one terminal connected to the drain electrode of the transistor T 6 and the other terminal connected to ground.

The amplifier 135 amplifies the tracking signal Vt to a suitable magnitude for the bleed switch circuit 200 to output the bleed switch control signal Vg. The amplifier 135 includes an OP amplifier U 6 , a resistor Rc, and a register Rd. The OP amplifier U 6 has a non-inverted terminal (+) connected to the tracking signal Vt, an inverted terminal (−) connected to both one terminal of the resistor Rd and one terminal of the resistor Rc, and an output terminal connected to the other terminal of the resistor Rd and outputting the bleed switch control signal Vg. The resistor Rc has one terminal connected to the inverted terminal (−) of the OP amplifier U 6 , and the other terminal connected to ground. The resistor Rd has one terminal connected to the inverted terminal (−) of the OP amplifier U 6 , and the other terminal connected to an output terminal of the OP amplifier U 6 .

Next, referring to FIG. 8 , an operation of the bleed switch controller 100 according to an embodiment of the present invention will be described.

FIG. 8 is a waveform diagram showing an operation of a bleed switch controller according to an embodiment of the present invention.

First, an operation of the analog controller 130 will be described.

The rectified AC voltage V+ has a waveform as shown in FIG. 8 because of the TRIAC dimmer 10 . If magnitude of the rectified AC voltage V+ reduces, an interval between on-time pulses of the power switch T 1 also reduces for conversion of a constant power.

Because the primary coil Co 1 of the transformer TX increases magnitude of a current in the resistor R 3 with a slope of V+/L during a turn-on time of the power switch T 1 , a waveform of the filtered signal Vcs corresponding to the source voltage V 1 of power switch T 1 is as shown in FIG. 8 . In particular, because magnitude of a voltage provided to the primary coil Co 1 is small in a duration when magnitude of the rectified AC voltage V+ is small, a peak value of the filtered signal Vcs is also small.

The analog buffer 131 b performs analog buffering of the filtered signal Vcs to output a buffered signal. In a case that the power switch control signal Vout has a high level, the transistor T 3 of the sampler 132 is turned on. Therefore, in a duration when the power switch control signal Vout has the high level, the sampling signal Vs is equal to the sum of the output signal of the analog buffer 131 b and a drain-source voltage Vds of the transistor T 3 . On the other hand, in a case that the power switch control signal Vout has a low level, the transistor T 3 is turned off, so a charged voltage of the capacitor C 4 is equal to magnitude of the sampling signal Vs. Therefore, in a duration when the power switch control signal Vout has the low level, the sampling signal Vs remains at the magnitude of the sampling signal Vs at a falling edge of the power switch control signal Vout.

Next, an operation of the digital controller 120 will be described.

The comparator U 1 a compares the sampling signal Vs with the reference voltage CS_REF to output a signal V 3 . Concretely, if the reference voltage CS_REF is larger than the sampling signal Vs, the comparator U 1 a according to an embodiment of the present invention outputs a high-level signal. Otherwise, the comparator U 1 a outputs a low-level signal.

The NOT gate U 1 b inverts the power switch control signal Vout to output a signal V 2 .

The AND gate U 1 c performs an AND operation with the output signal V 2 of the NOT gate U 1 b and the output signal V 3 of the comparator U 1 a as inputs, and outputs a signal V 4 as shown in FIG. 8 . The output signal V 4 of the AND gate U 1 c is a signal that is generated by detecting a condition where the sampling signal Vs is smaller than the reference voltage CS_REF while the power switch control signal Vout has the high level. The output signal V 4 is noise-filtered by the counter U 1 d and the latch U 1 i.

On the other hand, the comparator U 1 e compares the rectified AC signal V+ with the reference voltage V+_REF to output a signal V 5 . Concretely, if the reference voltage V+_REF is larger than the rectified AC signal V+, the comparator U 1 e outputs a low-level signal. Otherwise, the comparator U 1 e outputs a high-level signal. The output signal V 5 of the comparator U 1 e is used for turning off the bleed switch circuit 200 when the TRIAC is turned off.

If the TRIAC is triggered, the short pulse trigger U 1 f generates short pulses at a rising edges of the output signal V 5 of the comparator U 1 e to output a signal V 6 . The NOT gate U 1 g inverts the output signal V 6 of the short pulse trigger U 1 f to output a signal V 7 . The output signal V 6 of the short pulse trigger U 1 f and the output signal V 7 of the OT gate U 1 g are used for resetting the latch U 1 i and the counter U 1 d when the TRIAC is triggered, respectively.

The counter U 1 d outputs a low-level at every falling edge of output signal V 7 of the NOT gate U 1 g and inverts a phase at every rising edge of the output signal V 4 of the AND gate U 1 c to output a signal V 8 . The AND gate U 1 h performs an AND operation with the output signal V 8 of the counter U 1 d and the output signal V 7 of the NOT gate U 1 g to output a signal V 9 as shown in FIG. 8 .

The latch U 1 i outputs a signal V 10 with a high level at every rising edge of the output signal V 9 of the AND gate U 1 h , and outputs a signal V 10 with a low level at every rising edge of the output signal V 6 of the short pulse trigger U 1 f.

The NAND gate U 1 j performs a NAND operation with the output signal V 10 of the latch U 1 i and the output signal V 5 of the comparator U 1 e as inputs, and outputs the bleed switch on-off control signal Vd as shown in FIG. 8 .

The operation of the analog controller 130 will be described again.

The inverting amplifier 133 inverts and amplifies the sampling signal Vs with a gain of −Ra/Rb to generate an inverted sampling signal.

On the other hand, the tracking clock signal generator 136 generates a pulse at every falling edge of the power switch control signal Vout to generate the tracking clock signal Vt_clk.

Due to this, the transistor T 5 is turned on at a falling edge of the power switch control signal Vout, so the tracking signal Vt has magnitude of the inverted sampling signal at the falling edge of the power switch control signal Vout. However, when the bleed switch on-off control signal has the high level, the transistor T 6 is turned on, so the tracking signal Vt has the low level. That is, the tracking signal Vt has the low level in a duration when the bleed switch on-off control signal has the high level. The smaller the magnitude of the rectified AC signal V+ is, the larger the magnitude of the tracking signal Vt is in a duration when the bleed switch on-off control signal has the low level.

The amplifier 135 amplifies the tracking signal Vt with a gain of Rd/Rc to generate the bleed switch control signal Vg.

According to aspects of embodiments of the present invention, the efficiency of the AC-DC converter can be improved while the flicker of the LED lamp controlled by the TRIAC dimmer is prevented.

The embodiments of the present invention are not implemented only by a device and/or method, but can be implemented through a program for realizing functions corresponding to the configuration of the embodiments of the present invention and a recording medium having the program recorded thereon. These implementations can be realized by the ordinarily skilled person in the art from the description of the above-described embodiment.

While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.