Fault-tolerant unit and method for through-silicon via

This application claims the priority benefits of U.S. provisional application Ser. No. 61/468,078, filed on Mar. 28, 2011 and Taiwan application serial no. 100120191, filed on Jun. 9, 2011. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

1. Technical Field

The disclosure relates to a chip stacking structure having through-silicon vias (TSVs). Particularly, the disclosure relates to a fault-tolerant unit and a fault-tolerant method for TSV.

2. Related Art

A three-dimensional (3D) integrated circuit (IC) is a chip stacking structure formed by stacking a plurality of chips. FIG. 1 is a schematic diagram of a conventional chip stacking structure. The chip stacking structure 100 includes a chip 110 and a chip 120 , and a plurality of through-silicon via (TSV) structures is disposed between the chip 110 and the chip 120 . Based on considerations of circuit layout and winding, a same signal or power can be transmitted between the two adjacent chips 110 and 120 through the TSV structures. The TSV structure includes a TSV, a pad and a micro bump, wherein the TSV is disposed in the chip 110 of the upper layer, and the pad and the micro bump are disposed between the chip 110 and the chip 120 .

For example, the TSV structures TSV 1 , TSV 2 and TSV 3 shown in FIG. 1 transmit a clock signal CLK of the chip 110 to different clock trees in the chip 120 . The appearances of the TSV structures TSV 1 , TSV 2 and TSV 3 shown FIG. 1 are only drawn as an example. However, once the TSV structure is faulty, the 3D IC cannot normally work due to failure of signal transmission. Therefore, performance of the TSV structures is one of important factors influencing a yield of the 3D ICs.

The disclosure is directed to a fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV). The fault-tolerant unit has a TSV fault-tolerant effect without adding additional TSV structures.

The disclosure provides a fault-tolerant unit for TSV including n TSV structures TSV 1 -TSVn, n nodes N 1 1 -N 1 n , n nodes N 2 1 -N 2 n and a switch module. The nodes N 1 1 -N 1 n are disposed on a first chip of a chip stacking structure. The nodes N 2 1 -N 2 n are disposed on a second chip of the chip stacking structure. The TSV structure TSVi is electrically connected between the node N 1 i and the node N 2 i , where 1≦i≦n. The switch module is disposed on the second chip. The switch module is connected between the nodes N 2 1 -N 2 n and a test path of the second chip. In a normal operation state, the switch module disconnects the test path and the nodes N 2 1 -N 2 n when the TSV structures TSV 1 -TSVn are valid. The switch module connects the node N 2 i to at least one of the other nodes N 2 1 -N 2 n when the TSV structure TSVi is faulty in the normal operation state. In a test state, the switch module connects the test path to the nodes N 2 1 -N 2 n .

The disclosure provides a fault-tolerant method for TSV, which includes following steps. n TSV structures TSV 1 -TSVn are configured between a first chip and a second chip of a chip stacking structure, where the TSV structure TSVi is electrically connected between a first node N 1 i of the first chip and a second node N 2 i of the second chip, where 1≦i≦n, and n is an integer. A switch module is disposed on the second chip, where the switch module is connected between the second nodes N 2 1 -N 2 n and a test path of the second chip. In a normal operation state, the switch module disconnects the test path and the second nodes N 2 1 -N 2 n when the TSV structures TSV 1 -TSVn are valid. In the normal operation state, the switch module connects the second node N 2 i to at least one second node N 2 j (where j is not equal to i) of the other second nodes when the TSV structure TSVi is faulty. In a test state, the switch module connects the test path to the second nodes N 2 1 -N 2 n .

According to the above descriptions, the TSV structures TSV 1 -TSVn having the same signal characteristic in the chip stacking structure are used to form a fault-tolerant unit, and the fault-tolerant unit is unnecessary to add additional TSV structures. Namely, in the normal operation state, the TSV structures TSV 1 -TSVn respectively transmit a plurality of signals (for example, clock signals) having the same characteristic from the first chip to a plurality of circuit modules (for example, clock trees) of the second chip. When the TSV structure TSVi is faulty and cannot transmit a signal to the node N 2 i of the second chip, the switch module can transmit a signal (a signal having the same characteristic) of the other TSV structure to the node N 2 i . Therefore, the fault-tolerant unit of the disclosure may have a TSV fault tolerant effect.

In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a conventional chip stacking structure.

FIG. 2 is a functional block schematic diagram of a fault-tolerant unit for through-silicon via (TSV) according to an exemplary embodiment of the disclosure.

FIG. 3 is a functional block schematic diagram of a switch module of FIG. 2 according to an exemplary embodiment of the disclosure.

FIG. 4A is a schematic diagram of test/verification performed before stacking a first chip and a second chip.

FIG. 4B is a schematic diagram of a normal operation of a first chip and a second chip after chip stacking.

FIG. 5 is a schematic diagram of a fault-tolerant unit for TSV of FIG. 2 according to an exemplary embodiment of the disclosure.

FIG. 6 is a functional block schematic diagram of a self control unit according to an exemplary embodiment of the disclosure.

FIG. 7 is a circuit schematic diagram of a control circuit of FIG. 6 according to an exemplary embodiment of the disclosure.

FIG. 8 is a schematic diagram of a fault-tolerant unit for TSV of FIG. 2 according to another exemplary embodiment of the disclosure.

FIG. 9 is a functional block schematic diagram of a fault-tolerant unit for TSV according to another exemplary embodiment of the disclosure.

FIG. 10 is a schematic diagram of the fault-tolerant unit for TSV of FIG. 9 according to an exemplary embodiment of the disclosure.

FIG. 2 is a functional block schematic diagram of a fault-tolerant unit for through-silicon via (TSV) according to an exemplary embodiment of the disclosure. The fault-tolerant unit 200 for TSV includes n TSV structures (for example, TSV 1 , TSV 2 , TSV 3 , . . . , TSVn in FIG. 2 ), n first nodes (for example, N 1 1 , N 1 2 , N 1 3 , . . . , N n in FIG. 2 ), n second nodes (for example, N 2 1 , N 2 2 , N 2 3 , . . . , N 2 n in FIG. 2 ), and a switch module 210 , where n is an integer. The first nodes N 1 1 -N 1 n , are disposed on a first chip of a chip stacking structure, and the second nodes N 2 1 -N 2 n are disposed on a second chip of the chip stacking structure, where the first chip is stacked on the second chip. After the first chip is stacked on the second chip, the TSV structure TSVi is electrically connected between the first node N 1 i and the second node N 2 i , where 1≦i≦n.

The switch module 210 is disposed on the second chip. The switch module 210 is connected between the second nodes N 2 1 -N 2 n and a test path of the second chip, and is coupled to nodes N 2 1 ′, N 2 2 ′, N 2 3 ′, . . . , N 2 n ′ in FIG. 2 . The aforementioned test path is a redundant path for verifying a function of the second chip before chip stacking. Before the chip stacking, a verification/test platform can provide a clock signal TCLK to the second chip through the test path, so as to verify the function of the second chip. Therefore, in such test state, the TSV structures TSV 1 -TSVn are still not connected to the nodes N 2 1 ′-N 2 n ′, and the switch module 210 connects the test path used for transmitting the clock signal TCLK to the second nodes N 2 1 -N 2 n .

In the present embodiment, the fault-tolerant unit 200 for TSV further includes n delay adjustment modules (for example, DL 1 , DL 2 , DL 3 , . . . , DL n in FIG. 2 ) disposed on the second chip. The second nodes N 2 1 -N 2 n are respectively connected to different clock trees in the second chip. The delay adjustment module DL i is coupled between the second node N 2 i and the TSV structure TSV i , and coupled between the second node N 2 i and the switch module 210 , as that shown in FIG. 2 . In such test state, the delay adjustment modules DL 1 -DL n respectively transmit the clock signal TCLK from the switching module 210 to the second nodes N 2 1 -N 2 n by approximately a same delay amount.

After the chip stacking, the TSV structure TSVi is electrically connected between the first node N 1 i and the node N 2 i ′, and the aforementioned test path on the second chip for transmitting the clock signal TCLK is blocked from the second nodes N 2 1 -N 2 n by the switch module 210 . In a normal operation state, ideally, the TSV structures TSV 1 -TSVn are all valid, namely, the TSV structures TSV 1 -TSVn can respectively transmit the clock signal CLK from the first nodes N 1 1 -N 1 n in the first chip to the nodes N 2 1 ′-N 2 n ′. In the normal operation state, when the TSV structures TSV 1 -TSVn are all valid, the switch module 210 disconnects the test path and the second nodes N 2 1 -N 2 n , and the delay adjustment modules DL 1 -DL n respectively transmit the clock signal CLK from the TSV structures TSV 1 -TSVn to the second nodes N 2 1 -N 2 n through the nodes N 2 1 ′-N 2 n ′ by a first delay time.

In the normal operation state, when the TSV structure TSVi in the TSV structures TSV 1 -TSVn is faulty, the switch module 210 connects the second node N 2 i to at least one second node N 2 j ′ (where j is not equal to i) of the other second nodes, and the delay adjustment module DL i transmits the clock signal CLK between the switch module 210 and the second node N 2 i by a second delay time smaller than the first delay time (without passing through a buffer B i ). For example, when the TSV structure TSV 1 is faulty, the switch module 210 connects the second node N 2 1 to at least one of the other second nodes N 2 2 ′-N 2 n ′ (for example, the second node N 2 3 ′), and disconnects the other second nodes (for example, N 2 2 ′ and N 2 n ′) and the test path, namely, connects the second node N 2 1 to the node N 2 3 ′. Therefore, the clock tree corresponding to the TSV structure TSV 1 can obtain the clock signal CLK through the TSV structure TSV 3 and the switch module 210 . Moreover, a delay time of the delay adjustment module DL 1 is less than a delay time of the delay adjustment module DL 3 to compensate a signal delay amount of the clock signal CLK passing through the switch module 210 .

In the present exemplary embodiment, any means can be used to set a connection state (a connection configuration) of the delay adjustment modules DL 1 -DL n and the switch module 210 . For example, the connection state of the switch module 210 is set by a fuse mechanism. If it is discovered that the TSV structure TSV 1 is faulty in the test/verification performed after the chip stacking, a fuse configuration is changed in a subsequent process to set the connection state of the switch module 210 to be as that described above. Alternatively, a detecting circuit is used to set the connection state (the connection configuration) of the delay adjustment modules DL 1 -DL n and the switch module 210 . For example, when the detecting circuit detects that the TSV structure TSV 1 is faulty, or when the detecting circuit detects that the node N 2 1 ′ does not have the clock signal, the detecting circuit can automatically control the connection state of the switch module 210 to be as that described above.

In the present embodiment, the delay adjustment module DL i includes a buffer B i and a multiplexer M i . For example, the delay adjustment module DL 1 includes a buffer B 1 and a multiplexer M 1 , the delay adjustment module DL 2 includes a buffer B 2 and a multiplexer M 2 , the delay adjustment module DL 3 includes a buffer B 3 and a multiplexer M 3 , and the delay adjustment module DL n includes a buffer B n and a multiplexer M n . An input terminal of the buffer B i is coupled to the TSV structure TSVi through the node N 2 i ′. A first input terminal of the multiplexer M i is coupled to an output terminal of the buffer B i , a second input terminal of the multiplexer M i is coupled to the switch module 210 , and an output terminal of the multiplexer M i is coupled to the second node N 2 i . When the TSV structure TSVi is faulty, the multiplexer M i selects to connect the switch module 210 to the second node N 2 i . When the TSV structure TSVi is valid, the multiplexer M i selects to connect the output terminal of the buffer B i to the second node N 2 i . For example, when the TSV structure TSV 1 is faulty, the switch module 210 connects the second node N 2 1 to the TSV structure TSV 3 through the node N 2 3 ′, the multiplexer M 1 selects to connect the switch module 210 to the second node N 2 1 , and the multiplexer M 3 selects to connect the output terminal of the buffer B 3 to the second node N 2 3 . Therefore, the delay time of the delay adjustment module DL 1 is smaller than the delay time of the delay adjustment module DL 3 to compensate a signal delay amount of the clock signal CLK passing through the switch module 210 .

If the signal delay amount for the switch module 210 transmitting the clock signal CLK is smaller than a circuit design specification, namely, the signal delay amount of the switch module 210 is tolerable, the buffers B 1 -B n can be omitted/removed. If the buffers B 1 -B n are omitted, the first input terminal of the multiplexer M i is directly connected to the node N 2 i ′.

According to FIG. 2 , the fault-tolerant unit 200 for TSV is unnecessary to add any redundant TSV structures, and implements a TSV fault-tolerant effect. In the normal operation state, the TSV structures TSV 1 -TSVn respectively supply the clock signal CLK to different clock trees. When the TSV structure TSVi in the TSV structures TSV 1 -TSVn is faulty, the switch module 210 can change an electrical path of the TSV structures TSV 1 -TSVn, so that the clock tree corresponding to the faulty TSV structure TSVi can obtain the clock signal CLK. Therefore, the fault-tolerant unit 200 for TSV can improve a chip stacking yield.

FIG. 3 is a functional block schematic diagram of the switch module 210 of FIG. 2 according to an exemplary embodiment of the disclosure. Related descriptions of FIG. 2 can be referred for descriptions of the embodiment of FIG. 3 . Referring to FIG. 2 and FIG. 3 , the switch module 210 includes a redundant path 311 , a test switch TGT, n first fault-tolerant switches (for example, TG 1 , TG 2 , TG 3 , . . . , TGn) and n second fault-tolerant switches (for example, TG 1 x , TG 2 x , TG 3 x , . . . , TGnx). The test switch TGT, the first fault-tolerant switches TG 1 -TGn and the second fault-tolerant switches TG 1 x -TGnx can be switches, transmission gates, transistors, AND gates or fuse circuits, etc. A plurality of detecting terminals of a self control unit 320 are respectively connected to the nodes N 2 1 ′-N 2 n ′ (or the second ends of the TSV structures TSV 1 -TSVn). A plurality of output terminals of the self control unit 320 are respectively connected to control terminals of the multiplexers M 1 -M n , control terminals of the first fault-tolerant switches TG 1 -TGn, control terminals of the second fault-tolerant switches TG 1 x -TGnx and a control terminal of the test switch TGT. When the node N 2 i ′ has a signal (or when the TSV structure TSVi is valid), the self control unit 320 controls the multiplexer M i to connect the output terminal of the buffer B i to the second node N 2 i . When the node N 2 i ′ does not have the signal (or the TSV structure TSVi is faulty), the self control unit 320 controls the multiplexer M i to connect the first fault-tolerant switch TGi to the second node N 2 i .

The test switch TGT is connected between the redundant path 311 and the test path used for transmitting the clock signal TCLK. The test switch TGT is controlled by the self control unit 320 . When the test path for transmitting the clock signal TCLK has a signal, the self control unit 320 controls the test switch TGT to connect the test path to the redundant path 311 . Before the chip stacking, the TSV structures TSV 1 -TSVn are still not connected to the nodes N 2 1 ′-N 2 n ′ on the second chip of the lower layer, and the self control unit 320 turns on the test switch TGT. The clock signal TCLK can be transmitted to the redundant path 311 to test the second chip. After the chip stacking, the test path no longer transmits the clock signal TCLK, and the fault-tolerant unit 200 for TSV can be operated in the normal operation state, so that the self control unit 320 turns off the test switch TGT.

The first terminal of the first fault-tolerant switch TGi in the first fault-tolerant switches TG 1 -TGn is connected to the redundant path 311 , and the second terminal of the first fault-tolerant switch TGi is connected to the second node N 2 i through the multiplexer Mi. The first terminal of the second fault-tolerant switch TGix in the second fault-tolerant switches TG 1 x -TGnx is connected to the TSV structure TSVi through the node N 2 i ′, and the second terminal of the second fault-tolerant switch TGix is connected to the second terminal of the first fault-tolerant switch TGi. The first fault-tolerant switches TG 1 -TGn and the second fault-tolerant switches TG 1 x -TGnx are controlled by the self control unit 320 . In the test state before the chip stacking, none of the nodes N 2 1 ′-N 2 n ′ has a signal, and the self control unit 320 turns on the first fault-tolerant switches TG 1 -TGn and turns off the second fault-tolerant switches TG 1 x -TGnx. Therefore, the clock signal TCLK can be transmitted to different clock trees of the second chip through the test switch TGT, the redundant path 311 , the first fault-tolerant switches TG 1 -TGn, the multiplexers M 1 -M n and the second nodes N 2 1 -N 2 n , so as to test the second chip. In the normal operation state after the chip stacking, when the TSV structures TSV 1 -TSVn are all valid, the nodes N 2 1 ′-N 2 n ′ all have signals, and the self control unit 320 turns off the first fault-tolerant switches TG 1 -TGn, so that the switch module 210 does not interfere a normal operation of the second chip. Now, whether the second fault-tolerant switches TG 1 x -TGnx are all in a turn on state or a turn off state, the normal operation of the second chip is not influenced.

In the normal operation state, when the TSV structure TSVi in the TSV structures TSV 1 -TSVn is faulty, namely, the node N 2 i ′ does not has the signal, the self control unit 320 turns on the first fault-tolerant switch TGi and another first fault-tolerant switch TGj in the first fault-tolerant switches TG 1 -TGn, and turns off the other first fault-tolerant switches, and further turns off the second fault-tolerant switch TGix and turns on the other second fault-tolerant switches. For example, when the TSV structure TSV 1 is faulty, the self control unit 320 turns on the first fault-tolerant switch TG 1 and another first fault-tolerant switch (for example, the first fault-tolerant switch TG 3 ) in the first fault-tolerant switches TG 1 -TGn, and turns off the other first fault-tolerant switches (for example, the first fault-tolerant switches TG 2 and TGn in the FIG. 3 ), and further turns off the second fault-tolerant switch TG 1 x and turns on the other second fault-tolerant switches TG 2 x -TGnx. Therefore, besides that the clock signal CLK is transmitted to the clock tree corresponding to the TSV structure TSV 3 through the TSV structure TSV 3 , the buffer B 3 , the multiplexer M 3 and the second node N 2 3 , it is also transmitted to the clock tree corresponding to the TSV structure TSV 1 through the TSV structure TSV 3 , the second fault-tolerant switch TG 3 x , the first fault-tolerant switch TG 3 , the redundant path 311 , the first fault-tolerant switch TG 1 , the multiplexer M 1 and the second node N 2 1 .

In the following descriptions, two TSV structures (n=2) are taken as an example to describe implementation details of the fault-tolerant unit 200 for TSV of FIG. 2 . FIG. 4A is a schematic diagram of test/verification performed before stacking a first chip 410 and a second chip 420 . Referring to a left part of FIG. 4A , the first chip 410 is configured with a clock tree to facilitate transmitting the clock signal CLK. The second chip 420 is configured with a test path (shown by a dot line) to facilitate transmitting the clock signal TCLK (used for testing) to different clock trees (for example, clock trees 431 and 432 ). The right part of FIG. 4 is an equivalent circuit of partial clock trees of the second chip 420 before the chip stacking. In the test state, the switches TG 1 and TG 2 are turned on. Therefore, the clock signal TCLK used for testing can be transmitted to the clock tree 431 through the test path and the switch TG 1 , and transmitted to the clock tree 432 through the test path and the switch TG 2 .

FIG. 4B is a schematic diagram of a normal operation of the first chip 410 and the second chip 420 after chip stacking. Referring to a left part of FIG. 4B , the TSV structures TSV 1 , TSV 2 and TSV 3 are disposed between the first chip 410 and the second chip 420 , so that the clock signal CLK of the first chip 410 can be transmitted to different clock trees of the second chip 420 through the TSV structures TSV 1 , TSV 2 and TSV 3 . The right part of FIG. 4B is an equivalent circuit of partial clock trees of the second chip 420 after chip stacking. When the second chip 420 normally operates, the switches TG 1 and TG 2 are turned off, and the prior test path (shown by the dot lines) becomes a redundant path of the second chip 420 . Based on isolation of the switches TG 1 and TG 2 , the redundant path does not interfere transmission of the clock signal CLK. The clock signal CLK can be transmitted to the clock tree 431 from the first chip 410 through the TSV structure TSV 1 , and transmitted to the clock tree 432 through the TSV structure TSV 2 .

FIG. 5 is a schematic diagram of the fault-tolerant unit 200 for TSV of FIG. 2 according to the exemplary embodiment of the disclosure. Related descriptions of FIG. 2 , FIG. 3 , FIG. 4A and FIG. 4B can be referred for descriptions of the exemplary embodiment of FIG. 5 . Referring to the lower part of FIG. 5 , the TSV structures TSV 1 , TSV 2 and TSV 3 are disposed between the first chip 410 and the second chip 420 , so that the clock signal CLK of the first chip 410 can be transmitted to different clock trees of the second chip 420 through the TSV structures TSV 1 , TSV 2 and TSV 3 .

The upper part of FIG. 5 is an equivalent circuit of the fault-tolerant unit 200 for TSV of the second chip 420 after chip stacking. Before the chip stacking, the self control unit 320 turns on the test switch TGT through a control signal ENT, turns on the first fault-tolerant switches TG 1 -TG 2 through a control signal EN, and turns off the second fault-tolerant switches TG 1 x -TG 2 x through control signals EN 1 and EN 2 . Meanwhile, the self control unit 320 controls the multiplexer M 1 to connect the first fault-tolerant switch TG 1 of the switch module 210 to the clock tree 431 through the control signal EN 1 , and controls the multiplexer M 2 to connect the first fault-tolerant switch TG 2 of the switch module 210 to the clock tree 432 through the control signal EN 2 . In the test state, the clock signal TCLK used for testing can be transmitted to the clock tree 431 through the test path, the redundant path 311 , the switch TG 1 and the multiplexer M 1 , and transmitted to the clock tree 432 through the test path, the redundant path 311 , the switch TG 2 and the multiplexer M 2 .

After the chip stacking, the second chip 420 can normally operate, and the self control unit 320 turns off the test switch TGT through the control signal ENT, so that the redundant path 311 is isolated from the test path. The self control unit 320 can detect the nodes N 2 1 ′ and N 2 2 ′ to identify whether the TSV structures TSV 1 and TSV 2 are faulty. When the TSV structures TSV 1 and TSV 2 are valid, the self control unit 320 turns off the first fault-tolerant switches TG 1 -TG 2 through the control signal EN. Meanwhile, the self control unit 320 controls the multiplexer M 1 to connect the output terminal of the buffer B 1 to the clock tree 431 through the control signal EN 1 , and controls the multiplexer M 2 to connect the output terminal of the buffer B 2 to the clock tree 432 through the control signal EN 2 . Therefore, the clock signal CLK can be transmitted to the clock tree 431 through the TSV structure TSV 1 , the node N 2 1 ′, the buffer B 1 and the multiplexer M 1 , and the clock signal CLK can also be transmitted to the clock tree 432 through the TSV structure TSV 2 , the node N 2 2 ′, the buffer B 2 and the multiplexer M 2 .

When the TSV structure TSV 1 is faulty, the self control unit 320 turns off the test switch TGT through the control signal ENT, turns on the first fault-tolerant switches TG 1 -TG 2 through the control signal EN, turns off the second fault-tolerant switch TG 1 x through the control signal EN 1 , controls the multiplexer M 1 to connect the first fault-tolerant switch TG 1 to the clock tree 431 through the control signal EN 1 , turns on the second fault-tolerant switch TG 2 x through the control signal EN 2 , and controls the multiplexer M 2 to connect the output terminal of the buffer B 2 to the clock tree 432 through the control signal EN 2 . Therefore, besides that the TSV structure TSV 2 transmits the clock signal CLK to the clock tree 432 through the node N 2 2 ′, the buffer B 2 and the multiplexer M 2 , the TSV structure TSV 2 also transmits the clock signal CLK to the clock tree 431 through the node N 2 2 ′, the second fault-tolerant switch TG 2 x , the first fault-tolerant switch TG 2 , the redundant path 311 , the first fault-tolerant switch TG 1 and the multiplexer M 1 . A delay time of the buffer B 2 is approximately equal to a total delay time of the second fault-tolerant switch TG 2 x , the first fault-tolerant switch TG 2 , the redundant path 311 and the first fault-tolerant switch TG 1 . Therefore, the clock tree 431 corresponding to the faulty TSV structure TSV 1 can obtain the clock signal CLK from the valid TSV structure TSV 2 .

Deduced by analogy, when the TSV structure TSV 2 is faulty, the self control unit 320 controls the multiplexer M 1 to connect the output terminal of the buffer B 1 to the clock tree 431 through the control signal EN 1 , turns on the second fault-tolerant switch TG 1 x through the control signal EN 1 , turns off the second fault-tolerant switch TG 2 x through the control signal EN 2 , and controls the multiplexer M 2 to connect the first fault-tolerant switch TG 2 to the clock tree 432 through the control signal EN 2 . Therefore, besides that the TSV structure TSV 1 transmits the clock signal CLK to the clock tree 431 through the node N 2 1 ′, the buffer B 1 and the multiplexer M 1 , the TSV structure TSV 1 also transmits the clock signal CLK to the clock tree 432 through the second fault-tolerant switch TG 1 x , the first fault-tolerant switch TG 1 , the redundant path 311 , the first fault-tolerant switch TG 2 and the multiplexer M 2 . A delay time of the buffer B 1 is approximately equal to a total delay time of the second fault-tolerant switch TG 1 x , the first fault-tolerant switch TG 1 , the redundant path 311 and the first fault-tolerant switch TG 2 . Therefore, the clock tree 432 corresponding to the faulty TSV structure TSV 2 can obtain the clock signal CLK from the valid TSV structure TSV 1 .

Table 1 is a truth table of the above switches TG 1 , TG 2 , TG 1 x , TG 2 x and TGT. The control signals ENT, EN, EN 1 and EN 2 used for controlling the switches TG 1 , TG 2 , TG 1 x , TG 2 x and TGT and the multiplexers M 1 and M 2 can be set according to a manual mechanism, or can be automatically set by the self control unit 320 according to the states of the TSV structures TSV 1 and TSV 2 . Implementation of the self control unit 320 is described in detail later.

In the table 1, when the TSV structures TSV 1 and TSV 2 are all valid (in a good state), the second fault-tolerant switches TG 1 x and TG 2 x can be turned on. In another exemplary embodiment, when the TSV structures TSV 1 and TSV 2 are all valid, the second fault-tolerant switches TG 1 x and TG 2 x can be turned off to avoid noises of the redundant path 311 and the first fault-tolerant switches TG 1 and TG 2 from interfering the clock signals CLK at the node N 2 1 ′ and N 2 2 ′.

FIG. 6 is a functional block schematic diagram of the self control unit 320 according to the exemplary embodiment of the disclosure. The self control unit 320 includes a first control circuit 610 , a second control circuit 620 , a third control circuit 630 and an NAND gate 640 . The first control circuit 610 is used to detect the clock signal TCLK, and correspondingly generates the control signal ENT to the test switch TGT. When the clock signal TCLK does not exist, the control signal ENT is logic 0 to turn off the test switch TGT. When the first control circuit 610 detects the clock signal TCLK, the control signal ENT is logic 1 to turn on the test switch TGT. The second control circuit 620 is used to detect the TSV structure TSV 1 (for example, detects whether the node N 2 1 ′ has a signal), and correspondingly generates the control signal EN 1 to the multiplexer M 1 and the second fault-tolerant switch TG 1 x . When the TSV structure TSV 1 is faulty (for example, the node N 2 1 ′ does not have a signal), the control signal EN 1 is logic 0, so that the multiplexer M 1 selects to transmit the clock signal CLK output by the first fault-tolerant switch TG 1 to the clock tree 431 , and the second fault-tolerant switch TG 1 x is turned off in response to the control signal EN 1 to avoid the output signal of the first fault-tolerant switch TG 1 from interfering the second control circuit 620 . When the second control circuit 620 detects that the TSV structure TSV 1 is valid (for example, the node N 2 1 ′ has a signal), the control signal EN 1 is logic 1, so that the multiplexer M 1 selects to transmit the clock signal CLK output by the buffer B 1 to the clock tree 431 , and the second fault-tolerant switch TG 1 x is turned on in response to the control signal EN 1 .

The third control circuit 630 is used to detect the TSV structure TSV 2 (for example, detects whether the node N 2 2 ′ has a signal), and correspondingly generates the control signal EN 2 to the multiplexer M 2 and the second fault-tolerant switch TG 2 x . When the TSV structure TSV 2 is faulty (for example, the node N 2 2 ′ does not have a signal), the control signal EN 2 is logic 0, so that the multiplexer M 2 selects to transmit the clock signal CLK output by the first fault-tolerant switch TG 2 to the clock tree 432 , and the second fault-tolerant switch TG 2 x is turned off in response to the control signal EN 2 to avoid the output signal of the first fault-tolerant switch TG 2 from interfering the third control circuit 630 . When the third control circuit 630 detects that the TSV structure TSV 2 is valid (for example, the node N 2 2 ′ has a signal), the control signal EN 2 is logic 1, so that the multiplexer M 1 selects to transmit the clock signal CLK output by the buffer B 2 to the clock tree 432 , and the second fault-tolerant switch TG 2 x is turned on in response to the control signal EN 2 .

The first input terminal of the NAND gate 640 receives the control signal EN 1 output by the second control circuit 620 , the second input terminal of the NAND gate 640 receives the control signal EN 2 output by the third control circuit 630 , and an output terminal of the NAND gate 640 outputs the control signal EN to the first fault-tolerant switches TG 1 and TG 2 . When the control signal EN 1 and EN 2 are all logic 1, namely, when the TSV structures TSV 1 and TSV 2 are all valid, the control signal EN turns off the first fault-tolerant switches TG 1 and TG 2 , or otherwise turns on the first fault-tolerant switches TG 1 and TG 2 .

FIG. 7 is a circuit schematic diagram of the first control circuit 610 of FIG. 6 according to the exemplary embodiment of the disclosure. Implementation of the other control circuits 620 and 630 of FIG. 6 can refer to the related descriptions of the control circuit 610 . Referring to FIG. 7 , the first control circuit 610 includes a NOT gate 611 , a P-channel metal oxide semiconductor (PMOS) transistor 612 , a NOT gate 613 , an N-channel metal oxide semiconductor (NMOS) transistor 614 and a NOT gate 615 . When the clock signal TCLK exists, the clock signal TCLK is regularly transited between the logic 1 and the logic 0. When the clock signal TCLK is the logic 1, the PMOS 612 is turned on, and the NOT gate 613 outputs the logic 0. The logic 0 output by the NOT gate 613 turns off the NMOS transistor 614 , and the control signal ENT output by the NOT gate 615 is the logic 1. When the clock signal TCLK is the logic 0, the PMOS transistor 612 is turned off. In case that the PMOS transistor 612 and the NMOS transistor 614 are all turned off, a logic state of an input terminal of the NOT gate 613 is temporarily maintained to the logic 1 due to a parasitic capacitance, so that the NOT gate 613 outputs the logic 0. The logic 0 output by the NOT gate 613 turns off the NMOS transistor 614 , and the control signal ENT output by the NOT gate 615 is maintained to the logic 1.

When the clock signal TCLK does not exist, an input terminal of the NOT gate 611 may have a state of the logic 0, a floating state or a high impedance state, so that an output terminal of the NOT gate 611 is maintained to the logic 1, and the PMOS transistor 612 is maintained to be turned off. In case that the NMOS transistor 614 is turned off, the logic state of the input terminal of the NOT gate 613 is transited from the logic 1 to the logic 0 within a predetermined time due to a leakage effect of the parasitic capacitance. Once the input terminal of the NOT gate 613 is the logic 0, the NMOS transistor 614 is turned on, and the control signal ENT output by the NOT gate 615 is transited to the logic 0. Therefore, the self control unit 320 can automatically control the test gate TGT according to presence or absence of the clock signal TCLK.

The first chip 410 and the second chip 420 of the above exemplary embodiment are connected to each other, though the exemplary embodiment of the disclosure is not limited thereto. For example, FIG. 8 is a schematic diagram of the fault-tolerant unit 200 for TSV of FIG. 2 according to another exemplary embodiment of the disclosure. Related descriptions of FIG. 5 can be referred for the fault-tolerant unit 200 for TSV of FIG. 8 . Different to the exemplary embodiment of FIG. 5 , the chip stacking structure further includes at least one third chip 830 . The at least one third chip 830 is stacked between the first chip 410 and the second chip 420 , and the TSV structures TSV 1 -TSV 3 penetrate through the at least one third chip 830 and are respectively connected between the first nodes N 1 1 -N 1 3 and the second nodes N 2 1 -N 2 3 .

According to the above descriptions, a fault-tolerant method for TSV is provided below. The fault-tolerant method for TSV includes following steps. n TSV structures TSV 1 -TSVn are configured between the first chip and the second chip of a chip stacking structure, where the TSV structure TSVi is electrically connected between a first node N 1 i of the first chip and a second node N 2 i of the second chip, where 1≦i≦n, and n is an integer. A switch module is disposed on the second chip, where the switch module is connected between the second nodes N 2 1 -N 2 n and a test path of the second chip. In a normal operation state, the switch module disconnects the test path and the second nodes N 2 1 -N 2 n when the TSV structures TSV 1 -TSVn are valid. In the normal operation state, the switch module connects the second node N 2 i to at least one second node N 2 of the other second nodes when the TSV structure TSVi is faulty. In a test state, the switch module connects the test path to the second nodes N 2 1 -N 2 n .

In some embodiments, the fault-tolerant method for TSV further includes following steps. When the TSV structure TSVi is valid, a signal of the node N 2 1 ′ is transmitted to a second node N 2 i of the second chip by a first delay time, and when the TSV structure TSVi is faulty, the signal of the first fault-tolerant switches TGi is transmitted to the second node N 2 i of the second chip by a second delay time less than the first delay time.

In the above exemplary embodiments, pseudo codes of fault-tolerant 3D clock network synthesis are as follows:

In the above pseudo codes, TFU represents the aforementioned fault-tolerant unit 200 for TSV. “double TSV technique” represents a conventional fault-tolerant technique using redundant TSVs. The greater the “feasible range T” is, the longer the redundant path 311 is, and the greater the signal delay time is.

According to the above descriptions, the TSV structures TSV 1 -TSVn having the same signal characteristic in the chip stacking structure are used to form the fault-tolerant unit 200 . It is unnecessary to add additional TSV structures to the fault-tolerant unit 200 . Namely, in the normal operation state, the TSV structures TSV 1 -TSVn transmit a plurality of signals (for example, the clock signals CLK) having the same characteristic from the first chip 410 to a plurality of circuit modules (for example, the clock trees 431 and 432 ) of the second chip 420 . The TSV structures TSV 1 -TSVn are not redundant TSVs. When the TSV structure TSVi is faulty, and cannot transmit the clock signal CLK to the node N 2 i of the second chip 420 , the switch module 210 can transmit a signal (having the same characteristic) of the other TSV structure to the node N 2 i . Therefore, the fault-tolerant unit 200 can achieve a TSV fault-tolerant effect for TSVs in the chip stacking structure.

FIG. 9 is a functional block schematic diagram of a fault-tolerant unit 900 for TSV according to another exemplary embodiment of the disclosure. The fault-tolerant unit 900 for TSV includes n TSV structures (for example, TSV 1 , TSV 2 , TSV 3 , . . . , TSVn in FIG. 9 ), n first nodes (for example, N 1 1 , N 1 2 , N 1 3 , . . . , N 1 n in FIG. 9 ), n second nodes (for example, N 2 1 , N 2 2 , N 2 3 , . . . , N 2 n in FIG. 9 ), n delay adjustment modules (for example, DL 1 , DL 2 , DL 3 , . . . , DL n in FIG. 9 ), a switch module 910 and a self control unit 920 , where n is an integer. Related descriptions of the fault-tolerant unit 200 can be referred for an implementation of the fault-tolerant unit 900 . Different to the fault-tolerant unit 200 , the second fault-tolerant switches (for example, the second fault-tolerant switches TG 1 x -TGnx of FIG. 3 ) are omitted in the fault-tolerant unit 900 .

Referring to FIG. 9 , if a signal delay amount for the switch module 910 transmitting the clock signal CLK is less than a circuit design specification, namely the signal delay amount of the switch module 910 is tolerable, the delay adjustment modules DL 1 -DL n shown in FIG. 9 can be omitted/removed. If the delay adjustment module DL i is omitted, the second node N 2 i is directly connected to the node N 2 i ′ and the switch module 910 , namely, the node N 2 i ′ is connected to a clock tree in the second chip 420 .

FIG. 10 is a schematic diagram of the fault-tolerant unit 900 for TSV of FIG. 9 according to the exemplary embodiment of the disclosure. Related descriptions of FIG. 2 and FIG. 5 can be referred for the exemplary embodiment of FIG. 10 . The switch module 910 includes the redundant path 311 , the test switch TGT and n fault-tolerant switches. In the present exemplary embodiment, n is 2, so that only the fault-tolerant switches TG 1 and TG 2 are illustrated in FIG. 10 . Referring to a lower part of FIG. 10 , the TSV structures TSV 1 , TSV 2 and TSV 3 are configured between the first chip 410 and the second chip 420 , so that the clock signal CLK of the first chip 410 can be transmitted to different clock trees of the second chip 420 through the TSV structures TSV 1 , TSV 2 and TSV 3 . The upper part of FIG. 10 is an equivalent circuit of the fault-tolerant unit 900 for TSV on the second chip 420 after the chip stacking.

Within a predetermined time after power on, after the circuit and devices are stable, the self control unit 920 can detect whether the test path has the clock signal TCLK for once, and detects whether the nodes N 2 1 ′-N 2 n ′ have signals for once. Before the chip stacking, when the test path used for transmitting the clock signal TCLK has the signal, the self control unit 920 turns on the test switch TGT through the control signal ENT, so that the test path is connected to the redundant path 311 . When none of the nodes N 2 1 ′-N 2 n ′ has a signal, the self control unit 920 turns on the fault-tolerant switches TG 1 -TG 2 through the control signal EN. Meanwhile, the self control unit 320 controls the multiplexer M 1 to connect the fault-tolerant switch TG 1 of the switch module 910 to the clock tree 431 through the control signal EN 1 , and controls the multiplexer M 2 to connect the fault-tolerant switch TG 2 of the switch module 910 to the clock tree 432 through the control signal EN 2 . In the test state, the clock signal TCLK used for testing can be transmitted to the clock tree 431 through the test path, the redundant path 311 , the switch TG 1 and the multiplexer M 1 , and transmitted to the clock tree 432 through the test path, the redundant path 311 , the switch TG 2 and the multiplexer M 2 .

After the chip stacking, the second chip 420 can normally operate. Namely, the TSV structures TSV 1 -TSVn are respectively connected to the nodes N 2 1 ′-N 2 n ′, and the test path no longer transmits the clock signal TCLK. Therefore, the self control unit 920 turns off the test switch TGT through the control signal ENT, so that the redundant path 311 is isolated from the test path. The self control unit 920 can detect the nodes N 2 1 ′ and N 2 2 ′ to identify whether the TSV structures TSV 1 and TSV 2 are faulty. When the self control unit 920 detects that the TSV structures TSV 1 and TSV 2 are all valid (i.e. the nodes N 2 1 ′ and N 2 2 ′ have signals), the self control unit 920 stops detecting the TSV structures TSV 1 -TSVn, i.e. stops detecting the nodes N 2 1 ′ and N 2 2 ′. Then, the self control unit 920 turns off the fault-tolerant switches TG 1 -TG 2 through the control signal EN. Meanwhile, the self control unit 920 controls the multiplexer M 1 to connect the output terminal of the buffer B 1 to the clock tree 431 through the control signal EN 1 , and controls the multiplexer M 2 to connect the output terminal of the buffer B 2 to the clock tree 432 through the control signal EN 2 . Therefore, the clock signal CLK can be transmitted to the clock tree 431 through the TSV structure TSV 1 , the node N 2 1 ′, the buffer B 1 and the multiplexer M 1 , and the clock signal CLK can also be transmitted to the clock tree 432 through the TSV structure TSV 2 , the node N 2 2 ′, the buffer B 2 and the multiplexer M 2 .

When the self control unit 920 detects that the TSV structure TSV 1 is faulty, i.e. detects that the node N 2 1 ′ does not have a signal, the self control unit 920 stops detecting the TSV structures TSV 1 -TSV 2 . Then, besides turning off the test switch TGT through the control signal ENT, the self control unit 920 further turns on the fault-tolerant switches TG 1 -TG 2 through the control signal EN. Meanwhile, the self control unit 920 controls the multiplexer M 1 to connect the fault-tolerant switch TG 1 to the clock tree 431 through the control signal EN 1 , and controls the multiplexer M 2 to connect the output terminal of the buffer B 2 to the clock tree 432 through the control signal EN 2 . Therefore, besides that the TSV structure TSV 2 transmits the clock signal CLK to the clock tree 432 through the node N 2 2 ′, the buffer B 2 and the multiplexer M 2 , the TSV structure TSV 2 also transmits the clock signal CLK to the clock tree 431 through the node N 2 2 ′, the fault-tolerant switch TG 2 , the redundant path 311 , the fault-tolerant switch TG 1 and the multiplexer M 1 . A delay time of the buffer B 2 is approximately equal to a total delay time of the fault-tolerant switch TG 2 , the redundant path 311 and the fault-tolerant switch TG 1 . Therefore, the clock tree 431 corresponding to the faulty TSV structure TSV 1 can obtain the clock signal CLK from the valid TSV structure TSV 2 .

Deduced by analogy, when the self control unit 920 detects that the TSV structure TSV 2 is faulty, i.e. detects that the node N 2 2 ′ does not have a signal, the self control unit 920 stops detecting the TSV structures TSV 1 -TSV 2 . Then, the self control unit 320 controls the multiplexer M 1 to connect the output terminal of the buffer B 1 to the clock tree 431 through the control signal EN 1 , and controls the multiplexer M 2 to connect the fault-tolerant switch TG 2 to the clock tree 432 through the control signal EN 2 . Therefore, besides that the TSV structure TSV 1 transmits the clock signal CLK to the clock tree 431 through the node N 2 1 ′, the buffer B 1 and the multiplexer M 1 , the TSV structure TSV 1 also transmits the clock signal CLK to the clock tree 432 through the fault-tolerant switch TG 1 , the redundant path 311 , the fault-tolerant switch TG 2 and the multiplexer M 2 . A delay time of the buffer B 1 is approximately equal to a total delay time of the fault-tolerant switch TG 1 , the redundant path 311 and the fault-tolerant switch TG 2 . Therefore, the clock tree 432 corresponding to the faulty TSV structure TSV 2 can obtain the clock signal CLK from the valid TSV structure TSV 1 .

Table 2 is a truth table of the above switches TG 1 , TG 2 and TGT. The control signals ENT, EN, EN 1 and EN 2 used for controlling the switches TG 1 , TG 2 , and TGT and the multiplexers M 1 and M 2 can be set according to a manual mechanism, or can be automatically set by the self control unit 920 according to the states of the TSV structures TSV 1 and TSV 2 .

The above manual mechanism is, for example, to set the connection states of the switches TG 1 , TG 2 , TGT and the multiplexers M 1 and M 2 according to a fuse mechanism. If it is discovered that the TSV structure TSV 1 is faulty in the test/verification performed after the chip stacking, a fuse configuration is changed in a subsequent process to set the connection states of the switches TG 1 , TG 2 , TGT and the multiplexers M 1 and M 2 according to the table 2.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.