Angle detection apparatus

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-019397, filed on Feb. 1, 2011, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate to an angle detection apparatus.

In an angle detection apparatus of a rotary shaft of a motor or the like, a resolver is used for angle detection. The resolver receives an excitation signal, and generates signals by amplitude-modulating the excitation signal in accordance with a rotation angle.

Two angle signals (i.e. a SIN Φ component and a COS Φ component of an angle) outputted by the resolver may have a phase shift due to influence of a signal delay in propagation from the resolver to digital conversion. The occurrence of the phase shift leads to the problem of deterioration in accuracy of angle detection of the rotary shaft. Also, the occurrence of a change in amplitude leads to the problem of the deterioration in the accuracy of the angle detection of the rotary shaft.

FIG. 1 is a block diagram showing an angle detection apparatus according to a first embodiment;

FIG. 2 is a block diagram showing configurations of A-D (analog-to-digital) converter units according to the first embodiment;

FIG. 3 is a block diagram showing configurations of delay circuits according to the first embodiment;

FIG. 4 is a block diagram showing an angle detection apparatus of a comparative example according to the first embodiment;

FIG. 5 is a block diagram showing an angle detection apparatus according to a second embodiment;

FIG. 6 is a block diagram showing configurations of A-D converter units according to the second embodiment;

FIG. 7 is a block diagram showing an angle detection apparatus according to a third embodiment;

FIG. 8 is a block diagram showing a configuration of an amplitude detection unit according to the third embodiment;

FIGS. 9A and 9B are graphs showing generation of a signal S 11 and a signal S 12 , respectively, according to the third embodiment;

FIG. 10 is a block diagram showing an angle detection apparatus according to a fourth embodiment; and

FIG. 11 is a graph showing generation of a signal S 31 according to the fourth embodiment.

According to one embodiment, an angle detection apparatus performs angle detection of a rotary shaft of a rotating device, and generates a first signal and a second signal orthogonal to the first signal by amplitude-modulating an excitation signal in accordance with a rotation angle using a resolver. The first A-D converter unit receives the first signal, and performs analog-to-digital conversion of the first signal. The second A-D converter unit receives the second signal, and performs analog-to-digital conversion of the second signal. The first delay circuit receives a third signal outputted by the first A-D converter unit, and performs a phase adjustment of the third signal. The second delay circuit receives a fourth signal outputted by the second A-D converter unit, and performs a phase adjustment of the fourth signal. The phase detection adjustment unit monitors phases of signals outputted by the first and second delay circuits, and gives phase adjustment commands to the first and second delay circuits, when a phase shift occurs.

Plural further embodiments will be described below with reference to the drawings. In the drawings, the same reference numerals designate the same or similar portions.

An angle detection apparatus according to a first embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing the angle detection apparatus. FIG. 2 is a block diagram showing configurations of A-D (analog-to-digital) converter units. FIG. 3 is a block diagram showing configurations of delay circuits. FIG. 4 is a block diagram showing an angle detection apparatus of a comparative example. The first embodiment involves detecting phases of two signals outputted by a resolver through the A-D converter units, and, at the occurrence of a phase shift, performing a phase adjustment to make the phases coincide with each other, using the delay circuits.

As shown in FIG. 1 , an angle detection apparatus 90 includes a resolver 2 , an A-D converter unit 3 , an A-D converter unit 4 , a delay circuit 5 , a delay circuit 6 , a multiplication unit 7 , a multiplication unit 8 , a subtracter 9 , a synchronous detection unit 10 , an angular velocity calculation unit 11 , an integrator 12 , a cosine table 13 , a sine table 14 , a bus 15 , a microprocessor unit 16 , and an excitation signal generation unit 17 .

The resolver 2 is mounted to a motor 1 as a rotating device, and performs angle detection of the motor 1 . Upon receipt of Kex(t) as an excitation signal RS outputted by the excitation signal generation unit 17 , the resolver 2 generates a signal Kex(t)·SIN Φ by amplitude-modulating the excitation signal RS and a signal Kex(t)·COS Φ as a quadrature signal of the signal Kex(t)·SIN Φ in accordance with a rotation angle Φ of a rotary shaft of the motor 1 as the rotating device.

The signal Kex(t)·SIN Φ is inputted to the A-D converter unit 3 , and the signal Kex(t)·COS Φ is inputted to the A-D converter unit 4 . The A-D converter unit 3 is provided between the resolver 2 and the delay circuit 5 , and generates an analog-to-digital converted signal. The A-D converter unit 4 is provided between the resolver 2 and the delay circuit 6 , and generates an analog-to-digital converted signal.

As shown in FIG. 2 , the A-D converter unit 3 includes a ΔΣ A-D converter 21 and a digital filter 41 . The digital filter 41 includes an LPF (low-pass filter) 23 and a decimation filter 25 . The A-D converter unit 4 includes a ΔΣ A-D converter 22 and a digital filter 42 . The digital filter 42 includes an LPF 24 and a decimation filter 26 .

The ΔΣ A-D converter 21 receives the signal Kex(t)·SIN Φ, and the ΔΣ A-D converter 22 receives the signal Kex(t)·COS Φ. The ΔΣ A-D converter 21 and the ΔΣ A-D converter 22 each perform sampling using an oversampling frequency fos as a sufficiently higher frequency than a target sampling frequency, and perform analog-to-digital conversion thereby to reduce quantization noise. The ΔΣ A-D converter 21 and the ΔΣ A-D converter 22 have a resolution of 12 to 16 bits, for example, and receive the oversampling frequency fos about 2 5 times the target sampling frequency.

The LPF 23 is provided between the ΔΣ A-D converter 21 and the decimation filter 25 , and eliminates quantization noise in a no-pass region (high frequency band) outputted by the ΔΣ A-D converter 21 . The LPF 24 is provided between the ΔΣ A-D converter 22 and the decimation filter 26 , and eliminates quantization noise in a no-pass region (high frequency band) outputted by the ΔΣ A-D converter 22 .

The decimation filter 25 generates digital code having an ensured S/N (signal-to-noise) ratio by decimating signals outputted by the LPF 23 , and outputs a signal S 1 to the delay circuit 5 . The decimation filter 26 generates digital code having an ensured S/N ratio by decimating signals outputted by the LPF 24 , and outputs a signal S 2 to the delay circuit 6 .

The delay circuit 5 is provided between the A-D converter unit 3 and the multiplication unit 7 , and the delay circuit 6 is provided between the A-D converter unit 4 and the multiplication unit 8 . The delay circuit 5 and the delay circuit 6 have the same circuit configuration.

The delay circuit 5 performs a phase adjustment of the signal S 1 outputted by the A-D converter unit 3 in response to a command from the microprocessor unit 16 . The delay circuit 6 performs a phase adjustment of the signal S 2 outputted by the A-D converter unit 4 in response to on a command from the microprocessor unit 16 . Here, the phase adjustment is such an adjustment to make the phase of the signal S 1 to coincide with the phase of the signal S 2 .

A signal Sph 1 outputted by the delay circuit 5 and a signal Sph 2 outputted by the delay circuit 6 are inputted via the bus 15 to the microprocessor unit 16 , and are periodically monitored by the microprocessor unit 16 . The microprocessor unit 16 functions as a phase detection adjustment unit. When the microprocessor unit 16 determines that a phase shift occurs in the signal Sph 1 and the signal Sph 2 , the microprocessor unit 16 outputs a signal Scm 1 to the delay circuit 5 via the bus 15 , and outputs a signal Scm 2 to the delay circuit 6 via the bus 15 . The delay circuit 5 and the delay circuit 6 delay the signals and thereby perform a phase adjustment to make the phases coincide with each other in response to on the commands (namely, the signal Scm 1 and the signal Scm 2 ) from the microprocessor unit 16 .

The phase adjustment will be described in more detail with reference to FIG. 3 . As shown in FIG. 3 , the delay circuit 5 includes n series-connected flip-flops (namely, a flip-flop FF 1 , a flip-flop FF 2 , a flip-flop FF 3 , a flip-flop FF 4 , . . . , a flip-flop FFn), and a selector MUX 1 . The delay circuit 6 includes n series-connected flip-flops (namely, a flip-flop FF 1 a , a flip-flop FF 2 a , a flip-flop FF 3 a , a flip-flop FF 4 a , . . . , a flip-flop FFna), and a selector MUX 1 a.

The flip-flop FF 1 receives the signal S 1 at a D port, latches the signal S 1 on the rising edge of a clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 2 and the selector MUX 1 . The flip-flop FF 2 receives the signal outputted by the flip-flop FF 1 at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 3 and the selector MUX 1 . The flip-flop FF 3 receives the signal outputted by the flip-flop FF 2 at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 4 and the selector MUX 1 . The flip-flop FF 4 receives the signal outputted by the flip-flop FF 3 at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 5 (not shown) and the selector MUX 1 . The flip-flop FFn receives the signal outputted by the flip-flop FF(n−1) (not shown) at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the selector MUX 1 .

The selector MUX 1 receives the signals outputted at the Q ports of the flip-flop FF 1 , the flip-flop FF 2 , the flip-flop FF 3 , the flip-flop FF 4 , . . . , the flip-flop FFn, respectively, and selectively outputs the signal Sph 1 as a delay output signal obtained by performing a phase adjustment of the signal S 1 by delaying the signal S 1 by a predetermined time interval in response to the signal Scm 1 as a delay output select signal outputted by the microprocessor unit 16 .

The flip-flop FF 1 a receives the signal S 2 at a D port, latches the signal S 2 on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 2 a and the selector MUX 1 a . The flip-flop FF 2 a receives the signal outputted by the flip-flop FF 1 a at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 3 a and the selector MUX 1 a . The flip-flop FF 3 a receives the signal outputted by the flip-flop FF 2 a at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 4 a and the selector MUX 1 a . The flip-flop FF 4 a receives the signal outputted by the flip-flop FF 3 a at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the flip-flop FF 5 a (not shown) and the selector MUX 1 a . The flip-flop FFna receives the signal outputted by the flip-flop FF(n−1)a (not shown) at a D port, latches the signal on the rising edge of the clock signal Sclk, and outputs the latched signal at a Q port to the selector MUX 1 a.

The selector MUX 1 a receives the signals outputted from the Q ports of the flip-flop FF 1 a , the flip-flop FF 2 a , the flip-flop FF 3 a , the flip-flop FF 4 a , . . . , the flip-flop FFna, respectively, and selectively outputs the signal Sph 2 as a delay output signal in response to the signal Scm 2 as a delay output select signal outputted by the microprocessor unit 16 . Here, the signal Sph 2 is the signal S 2 delayed by a predetermined time interval and adjusted in terms of phase.

The multiplication unit 7 is provided between the delay circuit 5 and the subtracter 9 , and receives the phase-adjusted signal Sph 1 outputted by the delay circuit 5 . The multiplication unit 7 outputs a signal obtained by multiplying the phase-adjusted signal by a cosine function value COS θ with respect to a rotation angle θ as the previous calculated result fed back into the multiplication unit 7 by the cosine table 13 .

The multiplication unit 8 is provided between the delay circuit 6 and the subtracter 9 , and receives the phase-adjusted signal Sph 2 outputted by the delay circuit 6 . The multiplication unit 8 outputs a signal obtained by multiplying the phase-adjusted signal by a sine function value SIN θ with respect to the rotation angle θ as the previous calculated result fed back into the multiplication unit 8 by the sine table 14 .

The subtracter 9 is provided between the multiplication units 7 , 8 and the synchronous detection unit 10 . The subtracter 9 subtracts the output signal from the multiplication unit 8 from the output signal from the multiplication unit 7 thereby to generate a signal Kex(t)·SIN(θ−Φ).

The synchronous detection unit 10 performs synchronous detection in synchronization with the excitation signal RS by sampling an output of the signal Kex(t)·SIN(θ−Φ) outputted by the subtracter 9 . In other words, components of the excitation signal RS outputted by the subtracter 9 are eliminated, so that a signal SIN(θ−Φ) is outputted by the synchronous detection unit 10 .

The angular velocity calculation unit 11 is provided between the synchronous detection unit 10 and the integrator 12 . The angular velocity calculation unit 11 calculates angular velocity V of the motor 1 as the rotating device by integrating the signal outputted by the synchronous detection unit 10 .

The integrator 12 integrates the angular velocity V outputted by the angular velocity calculation unit 11 thereby to calculate the rotation angle θ of the motor 1 as the rotating device.

In the angle detection apparatus 90 , if the signal SIN(θ−Φ) outputted by the synchronous detection unit 10 is a control deviation ε, when the rotation angle θ as an output angle is equal to the rotation angle Φ as an input angle (θ=Φ), the control deviation ε is equal to zero (ε=0), and an equilibrium state is maintained. When the rotation angle Φ as the input angle changes to Φa, the control deviation ε is not equal to zero, and the rotation angle θ as the output angle is fed back so that θ becomes equal to Φa (θ=Φa) according to the polarity of the control deviation ε, and thereby, the control deviation ε becomes equal to zero (ε=0) and thus the equilibrium state is reached.

As shown in FIG. 4 , an angle detection apparatus 100 of the comparative example includes a resolver 2 , an A-D converter unit 3 , an A-D converter unit 4 , a multiplication unit 7 , a multiplication unit 8 , a subtracter 9 , a synchronous detection unit 10 , an angular velocity calculation unit 11 , an integrator 12 , a cosine table 13 , a sine table 14 , and an excitation signal generation unit 17 .

The angle detection apparatus 100 of the comparative example is not provided with a delay circuit 5 and a delay circuit 6 , as compared to the angle detection apparatus 90 of the first embodiment. Thus, description will be given only with regard to the points of difference.

The multiplication unit 7 is provided between the A-D converter unit 3 and the subtracter 9 , and receives an analog-to-digital converted signal. The multiplication unit 7 outputs a signal obtained by multiplying a phase-adjusted signal by a cosine function value COS θ with respect to a rotation angle θ as the previous calculated result fed back into the multiplication unit 7 by the cosine table 13 .

The multiplication unit 8 is provided between the A-D converter unit 4 and the subtracter 9 , and receives an analog-to-digital converted signal. The multiplication unit 8 outputs a signal obtained by multiplying a phase-adjusted signal by a sine function value SIN θ with respect to the rotation angle θ as the previous calculated result fed back into the multiplication unit 8 by the sine table 14 . In the angle detection apparatus 100 of the comparative example, phase adjustments of the signals outputted by the A-D converter unit 3 and the A-D converter unit 4 are not performed.

As described above, the angle detection apparatus of the first embodiment includes the resolver 2 , the A-D converter unit 3 , the A-D converter unit 4 , the delay circuit 5 , the delay circuit 6 , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , the cosine table 13 , the sine table 14 , the bus 15 , the microprocessor unit 16 , and the excitation signal generation unit 17 . The microprocessor unit 16 receives the signal Sph 1 outputted by the delay circuit 5 and the signal Sph 2 outputted by the delay circuit 6 , via the bus 15 , and periodically monitors the signal Sph 1 and the signal Sph 2 . If the microprocessor unit 16 determines that a phase shift occurs in the signal Sph 1 and the signal Sph 2 , the microprocessor unit 16 outputs the signal Scm 1 to the delay circuit 5 via the bus 15 , and outputs the signal Scm 2 to the delay circuit 6 via the bus 15 . In response to the commands from the microprocessor unit 16 , the delay circuit 5 and the delay circuit 6 delay the signals and thereby perform a phase adjustment to make the phases coincide with each other.

Thus, even if a phase shift occurs in input, the angle detection of the rotary shaft of the motor 1 can be performed with high accuracy. Also, delay values of the delay circuit 5 and the delay circuit 6 can be appropriately set by using the flip-flops, and thus, the angle detection apparatus 90 having resistance to a change with time can be provided.

Incidentally, in the first embodiment, the microprocessor unit 16 detects a phase shift by periodically monitoring the signal Sph 1 and the signal Sph 2 . However, it is to be understood that the invention is not necessarily so limited. For example, a phase detection function may be provided externally to the microprocessor unit 16 .

An angle detection apparatus according to a second embodiment will be described with reference to the drawings. FIG. 5 is a block diagram showing the angle detection apparatus. FIG. 6 is a block diagram showing configurations of A-D converter units. In the second embodiment, after an A-D conversion process, a phase adjustment is performed to make the phases coincide with each other.

Hereinafter, the same constituent portions as those of the first embodiment are designated by the same reference numerals, description of the same portions will be omitted, and description will be given only with regard to different portions.

As shown in FIG. 5 , an angle detection apparatus 91 includes a resolver 2 , an A-D converter unit 3 a , an A-D converter unit 4 a , a multiplication unit 7 , a multiplication unit 8 , a subtracter 9 , a synchronous detection unit 10 , an angular velocity calculation unit 11 , an integrator 12 , a cosine table 13 , a sine table 14 , a bus 15 , a microprocessor unit 16 , and an excitation signal generation unit 17 .

A signal Kex(t)·SIN Φ outputted by the resolver 2 is inputted to the A-D converter unit 3 a , and a signal Kex(t)·COS Φ outputted by the resolver 2 is inputted to the A-D converter unit 4 a . The A-D converter unit 3 a is provided between the resolver 2 and the multiplication unit 7 , and performs analog-to-digital conversion. The A-D converter unit 4 a is provided between the resolver 2 and the multiplication unit 8 , and performs analog-to-digital conversion.

A signal Sph 1 a outputted by the A-D converter unit 3 a and a signal Sph 2 a outputted by the A-D converter unit 4 a are inputted via the bus 15 to the microprocessor unit 16 , and are periodically monitored by the microprocessor unit 16 . The microprocessor unit 16 functions as a phase detection adjustment unit. When the microprocessor unit 16 determines that a phase shift occurs in the signal Sph 1 a and the signal Sph 2 a , the microprocessor unit 16 outputs a signal Scm 1 a to the A-D converter unit 3 a via the bus 15 , and outputs a signal Scm 2 a to the A-D converter unit 4 a via the bus 15 .

As shown in FIG. 6 , the A-D converter unit 3 a includes a ΔΣ A-D converter 21 , a delay circuit 5 , and a digital filter 41 . The digital filter 41 includes an LPF 23 and a decimation filter 25 . The A-D converter unit 4 a includes a ΔΣ A-D converter 22 , a delay circuit 6 , and a digital filter 42 . The digital filter 42 includes an LPF 24 and a decimation filter 26 .

The delay circuit 5 is provided between the ΔΣ A-D converter 21 and the digital filter 41 . The delay circuit 5 performs a phase adjustment of a signal outputted by the ΔΣ A-D converter 21 , based on a command (namely, the signal Scm 1 a ) from the microprocessor unit 16 . The delay circuit 6 is provided between the ΔΣ A-D converter 22 and the digital filter 42 . The delay circuit 6 performs a phase adjustment of a signal outputted by the ΔΣ A-D converter 22 , based on a command (namely, the signal Scm 2 a ) from the microprocessor unit 16 .

Here, the output signals from the ΔΣ A-D converter 21 and the ΔΣ A-D converter 22 are higher in sampling frequency and fewer in the number of bits than the signal Sph 1 a outputted by the decimation filter 25 and the signal Sph 2 a outputted by the decimation filter 26 . Thus, a finer signal phase adjustment can be set, as compared to the first embodiment.

As described above, the angle detection apparatus of the second embodiment includes the resolver 2 , the A-D converter unit 3 a , the A-D converter unit 4 a , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , the cosine table 13 , the sine table 14 , the bus 15 , the microprocessor unit 16 , and the excitation signal generation unit 17 . The A-D converter unit 3 a includes the ΔΣ A-D converter 21 , the delay circuit 5 , the LPF 23 , and the decimation filter 25 . The A-D converter unit 4 a includes the ΔΣ A-D converter 22 , the delay circuit 6 , the LPF 24 , and the decimation filter 26 . The microprocessor unit 16 receives the signal Sph 1 a outputted by the decimation filter 25 and the signal Sph 2 a outputted by the decimation filter 26 , via the bus 15 , and periodically monitors the signal Sph 1 a and the signal Sph 2 a . When the microprocessor unit 16 determines that a phase shift occurs in the signal Sph 1 a and the signal Sph 2 a , the microprocessor unit 16 outputs a signal Scm 1 a to the delay circuit 5 via the bus 15 , and outputs a signal Scm 2 a to the delay circuit 6 via the bus 15 . The delay circuit 5 and the delay circuit 6 delay the signals and thereby perform a phase adjustment to make the phases coincide with each other, based on the commands from the microprocessor unit 16 .

Thus, even if a phase shift occurs in input, the angle detection of the rotary shaft of the motor 1 can be performed with high accuracy. Also, the delay values of the delay circuit 5 and the delay circuit 6 can be appropriately set by using the flip-flops, and thus, the angle detection apparatus 91 having resistance to a change with time can be provided.

An angle detection apparatus according to a third embodiment will be described with reference to the drawings. FIG. 7 is a block diagram showing the angle detection apparatus. FIG. 8 is a block diagram showing a configuration of an amplitude detection unit. FIGS. 9A and 9B are graphs showing generation of a signal S 11 and a signal S 12 , respectively. In the third embodiment, amplitude adjustment units perform an amplitude adjustment.

Hereinafter, the same constituent portions as those of the first embodiment are designated by the same reference numerals, description of the same portions will be omitted, and description will be given only with regard to different portions.

As shown in FIG. 7 , an angle detection apparatus 92 includes a resolver 2 , an A-D converter unit 3 , an A-D converter unit 4 , an amplitude adjustment unit 81 , an amplitude adjustment unit 82 , a multiplication unit 7 , a multiplication unit 8 , a subtracter 9 , a synchronous detection unit 10 , an angular velocity calculation unit 11 , an integrator 12 , a cosine table 13 , a sine table 14 , a bus 15 , a microprocessor unit 16 , an excitation signal generation unit 17 , and an amplitude detection unit 18 .

The amplitude adjustment unit 81 is provided between the A-D converter unit 3 and the multiplication unit 7 , amplitude detection unit 18 . The amplitude adjustment unit 82 is provided between the A-D converter unit 4 and the multiplication unit 8 , amplitude detection unit 18 . The amplitude adjustment unit 81 and the amplitude adjustment unit 82 have the same circuit configuration.

The amplitude adjustment unit 81 performs an amplitude adjustment of a signal S 1 outputted by the A-D converter unit 3 , based on a command from the microprocessor unit 16 as an amplitude adjustment calculation unit. The amplitude adjustment unit 82 performs an amplitude adjustment of a signal S 2 outputted by the A-D converter unit 4 , based on a command from the microprocessor unit 16 as the amplitude adjustment calculation unit.

The amplitude detection unit 18 is provided between the amplitude adjustment units 81 , 82 and the bus 15 . The amplitude detection unit 18 receives a signal Sa 1 as a SIN amplitude detection input outputted by the amplitude adjustment unit 81 , and generates a signal Sks 1 as a first amplitude detection signal. The amplitude detection unit 18 receives a signal Sat as a COS amplitude detection input outputted by the amplitude adjustment unit 82 , and generates a signal Sks 2 as a second amplitude detection signal.

As shown in FIG. 8 , the amplitude detection unit 18 includes a first detection unit 51 , a second detection unit 52 , a third detection unit 53 , and a fourth detection unit 54 .

The first detection unit 51 is provided between the amplitude adjustment unit 81 and the second detection unit 52 . The first detection unit 51 includes a first maximum value detection unit 61 and a latch circuit 71 . The first maximum value detection unit 61 receives the signal Sa 1 , and calculates the maximum value for each excitation. The latch circuit 71 data latches the maximum value calculated by the first maximum value detection unit 61 , based on an excitation signal RS.

The second detection unit 52 is provided between the first detection unit 51 and the bus 15 . The second detection unit 52 includes a second maximum value detection unit 62 and a latch circuit 72 . The second maximum value detection unit 62 receives the signal latched by the latch circuit 71 , and calculates the maximum value for each rotation. The latch circuit 72 data latches the maximum value calculated by the second maximum value detection unit 62 , based on a signal S 11 obtained by a trigger circuit (not shown) dividing a signal of the rotation angle θ outputted by the angle detection apparatus 92 into four portions, and outputs the signal Sks 1 .

As shown in FIG. 9A , the signal of the rotation angle θ is divided by the trigger circuit into four portions (2 bits), namely, Quad 1 (data ( 00 )), Quad 2 (data ( 01 )), Quad 3 (data ( 10 )), and Quad 4 (data ( 11 )). When changing from the data ( 11 ) to the data ( 00 ), the signal S 11 changes to the signal in an enable state. The maximum value calculated by the second maximum value detection unit 62 is data latched, based on the signal S 11 in the enable state.

The third detection unit 53 is provided between the amplitude adjustment unit 82 and the fourth detection unit 54 . The third detection unit 53 includes a third maximum value detection unit 63 and a latch circuit 73 . The third maximum value detection unit 63 receives the signal Sat, and calculates the maximum value for each excitation. The latch circuit 73 data latches the maximum value calculated by the third maximum value detection unit 63 , in response to an excitation signal RS.

The fourth detection unit 54 is provided between the third detection unit 53 and the bus 15 . The fourth detection unit 54 includes a fourth maximum value detection unit 64 and a latch circuit 74 . The fourth maximum value detection unit 64 receives the signal latched by the latch circuit 73 , and calculates the maximum value for each rotation. The latch circuit 74 data latches the maximum value calculated by the third maximum value detection unit 63 , in response to a signal S 12 obtained by a trigger circuit (not shown) dividing a signal cosine (COS) of the rotation angle θ into four portions, and outputs the signal Sks 2 .

As shown in FIG. 9B , the signal cosine (COS) of the rotation angle θ is divided by the trigger circuit into four portions (2 bits), namely, Quad 4 (data ( 11 )), Quad 1 (data ( 00 )), Quad 2 (data ( 01 )), and Quad 3 (data ( 10 )). When changing from the data ( 10 ) to the data ( 11 ), the signal S 12 changes to the signal in an enable state. The maximum value calculated by the fourth maximum value detection unit 64 is data latched in response to the signal S 12 in the enable state.

The signal Sks 1 and the signal Sks 2 outputted by the amplitude detection unit 18 are inputted via the bus 15 to the microprocessor unit 16 , and are monitored at regular intervals by the microprocessor unit 16 . The microprocessor unit 16 functions as the amplitude adjustment calculation unit. When the microprocessor unit 16 determines that a change in amplitude occurs in the signal Sa 1 and the signal Sa 2 , the microprocessor unit 16 outputs a signal Sos 1 as an amplitude adjustment signal to the amplitude adjustment unit 81 via the bus 15 and outputs a signal Sos 2 as an amplitude adjustment signal to the amplitude adjustment unit 82 via the bus 15 . In other words, the amplitude adjustment unit 81 and the amplitude adjustment unit 82 perform an amplitude adjustment in response to commands from the microprocessor unit 16 .

As described above, the angle detection apparatus of the third embodiment includes the resolver 2 , the A-D converter unit 3 , the A-D converter unit 4 , the amplitude adjustment unit 81 , the amplitude adjustment unit 82 , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , the cosine table 13 , the sine table 14 , the bus 15 , the microprocessor unit 16 , the excitation signal generation unit 17 , and the amplitude detection unit 18 . The amplitude detection unit 18 detects the amplitude of the signal Sa 1 outputted by the amplitude adjustment unit 81 , and detects the amplitude of the signal Sa 2 outputted by the amplitude adjustment unit 82 . The microprocessor unit 16 receives the amplitude detection signal outputted by the amplitude detection unit 18 through the bus 15 , and monitors the amplitude detection signal at regular intervals. If the microprocessor unit 16 determines that a change in amplitude occurs in the signal Sa 1 and the signal Sa 2 , the microprocessor unit 16 outputs the signal Sos 1 to the amplitude adjustment unit 81 via the bus 15 and outputs the signal Sos 2 to the amplitude adjustment unit 82 via the bus 15 . The amplitude adjustment unit 81 and the amplitude adjustment unit 82 perform an amplitude adjustment of the signals in response to the commands from the microprocessor unit 16 .

Thus, even at the occurrence of a change in amplitude of an input, the angle detection of the rotary shaft of the motor 1 can be performed with high accuracy.

An angle detection apparatus according to a fourth embodiment will be described with reference to the drawings. FIG. 10 is a block diagram showing the angle detection apparatus. FIG. 11 is a graph showing generation of a signal S 31 . In the fourth embodiment, an amplitude adjustment unit is used to perform a phase adjustment in accordance with an electrical angle of the resolver.

Hereinafter, the same portions as those of the third embodiment are designated by the same reference numerals, description of the portions will be omitted, and different portions alone will be described.

As shown in FIG. 10 , an angle detection apparatus 93 includes a resolver 2 , an A-D converter unit 3 , an A-D converter unit 4 , an amplitude adjustment unit 81 , an amplitude adjustment unit 82 , a multiplication unit 7 , a multiplication unit 8 , a subtracter 9 , a synchronous detection unit 10 , an angular velocity calculation unit 11 , an integrator 12 , a cosine table 13 , a sine table 14 , a bus 15 , a microprocessor unit 16 , an excitation signal generation unit 17 , an amplitude detection unit 18 , a memory 31 , a DMAC (direct memory access controller) 32 , and an angle detection unit 33 . The amplitude adjustment unit 81 , the amplitude adjustment unit 82 , the amplitude detection unit 18 , the microprocessor unit 16 , the memory 31 , and the DMAC 32 are connected via the bus 15 .

The angle detection unit 33 is provided between the integrator 12 and the DMAC 32 . The angle detection unit 33 receives a signal of a rotation angle θ outputted by the angle detection apparatus 93 . As shown in FIG. 11 , the angle detection unit 33 detects the signal of the rotation angle θ for each rotation, and generates the signal S 31 as an angle detection signal.

The memory 31 includes a first memory area 311 and a second memory area 312 . The first memory area 311 stores information on the amplitude detection signals (namely, a signal Sks 1 and a signal Sks 2 ) outputted by the amplitude detection unit 18 . The second memory area 312 stores an amplitude adjustment value calculated from a result of amplitude detection by the microprocessor unit 16 .

The DMAC 32 starts operation in response to a command from the microprocessor unit 16 . The DMAC 32 receives the signal S 31 , reads out the amplitude adjustment value stored in the second memory area 312 of the memory 31 for every one electrical angle of the resolver 2 , and transfers the amplitude adjustment value via the bus 15 to the amplitude adjustment unit 81 and the amplitude adjustment unit 82 .

The microprocessor unit 16 functions as the amplitude adjustment calculation unit. The microprocessor unit 16 reads out the amplitude detection signal information stored in the first memory area 311 of the memory 31 via the bus 15 , and calculates the amplitude adjustment value. In other words, by the DMAC 32 that has received the command from the microprocessor unit 16 , the amplitude adjustment unit 81 and the amplitude adjustment unit 82 perform the amplitude adjustment.

As described above, the angle detection apparatus of the fourth embodiment includes the resolver 2 ; the A-D converter unit 3 , the A-D converter unit 4 , the amplitude adjustment unit 81 , the amplitude adjustment unit 82 , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , the cosine table 13 , the sine table 14 , the bus 15 , the microprocessor unit 16 , the excitation signal generation unit 17 , the amplitude detection unit 18 , the memory 31 , the DMAC 32 , and the angle detection unit 33 . The DMAC 32 receives the signal S 31 outputted by the angle detection unit 33 , reads out the amplitude adjustment value stored in the second memory area 312 of the memory 31 for every one electrical angle of the resolver 2 , and transfers the amplitude adjustment value to the amplitude adjustment unit 81 and the amplitude adjustment unit 82 . By the DMAC 32 , the amplitude adjustment unit 81 and the amplitude adjustment unit 82 perform the amplitude adjustment of the signal.

Thus, even if a change in amplitude occurs in input, the angle detection of the rotary shaft of the motor 1 can be performed with high accuracy. Also, as compared to the third embodiment, operations, control commands and the like executed by the microprocessor unit 16 can be reduced, thus enabling the use of a relatively inexpensive microprocessor unit and hence enabling a reduction in system cost of the angle detection apparatus 93 .

It is to be understood that the invention is not limited to the above-described embodiments, and various changes could be made thereto without departing from the basic concept and scope of the invention.

In the first to fourth embodiments, the microprocessor unit 16 is used. However, it is to be understood that the invention is not necessarily so limited. For example, a CPU (central processing unit) or the like may be used in place of the microprocessor unit. Also, in the first and second embodiments, the flip-flops are used in the delay circuit 5 and the delay circuit 6 . However, it is to be understood that the invention is not necessarily so limited. For example, latch circuits may be used in place of the flip-flops. In the first embodiment, the A-D converter unit 3 , the A-D converter unit 4 , the delay circuit 5 , the delay circuit 6 , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , the cosine table 13 , the sine table 14 , the bus 15 , the microprocessor unit 16 , and the excitation signal generation unit 17 are provided in a package or a semiconductor chip. In the second embodiment, the A-D converter unit 3 a , the A-D converter unit 4 a , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , the cosine table 13 , the sine table 14 , the bus 15 , the microprocessor unit 16 , and the excitation signal generation unit 17 are provided in a package or a semiconductor chip. In the third embodiment, the A-D converter unit 3 , the A-D converter unit 4 , the amplitude adjustment unit 81 , the amplitude adjustment unit 82 , the multiplication unit 7 , the multiplication unit 8 , the subtracter 9 , the synchronous detection unit 10 , the angular velocity calculation unit 11 , the integrator 12 , a cosine table 13 , a sine table 14 , a bus 15 , a microprocessor unit 16 , the excitation signal generation unit 17 , and the amplitude detection unit 18 are provided in a package or a semiconductor chip.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intend to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of the other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.