Drive device having amplifier unit for applying gradation reference voltage

The present invention relates to a drive device for driving a display panel. More specifically, the present invention relates to a drive device of a display panel capable of applying a gradation voltage to a data line of a liquid crystal display panel according to an input video signal.

In a liquid crystal display panel of an active matrix type, a plurality of scanning lines is arranged to extend in a horizontal direction of a two-dimensional screen, and a plurality of data lines is arranged to extend in a vertical direction of the two-dimensional screen. Each of the scanning lines is arranged to cross each of the data lines. An electrode functioning as a pixel is disposed at a crossing point of each of the scanning lines and each of the data lines. Further, the liquid crystal display panel is provided with a drive device for applying a voltage to each of the data lines according to a brightness level indicated with an input video signal.

Patent Reference has disclosed a conventional drive device. The conventional drive device is configured to generate a voltage (referred to as a gradation voltage) for each gradient representing 64 scales of a brightness range that the input video signal can display. Then, the conventional drive device selects one of the gradation voltages corresponding to the brightness level indicated with the input video signal, and applies the gradation voltage to the data line.

Patent Reference: Japanese Patent Publication No. 2002-366115

In the conventional drive device disclosed in Patent Reference, a gradation voltage generation circuit is provided for inverting a polarity of the gradation voltage in a specific cycle, thereby preventing the liquid crystal display panel from deteriorating due to a problem such as burning out of the pixel. The gradation voltage generation circuit includes a switch for alternately switching between the gradation reference voltage with a positive polarity (VHP) and the gradation reference voltage with a negative polarity (VHN) in the specific cycle, so that the gradation reference voltage is applied to an input line of an amplifier. The amplifier amplifies the gradation reference voltage applied to the input line, so that the gradation voltage with the polarity switched in the specific cycle is generated.

In the conventional drive device described above, immediately after the gradation reference voltage with the positive polarity is applied to the input line of the amplifier, the input line is maintained at the voltage with the positive polarity. Similarly, immediately after the gradation reference voltage with the negative polarity is applied to the input line of the amplifier, the input line is maintained at the voltage with the negative polarity.

Accordingly, when the polarity of the gradation reference voltage is inverted, the gradation reference voltage with the negative polarity is applied to the input line of the amplifier maintained at the voltage with the positive polarity. Similarly, the gradation reference voltage with the positive polarity is applied to the input line of the amplifier maintained at the voltage with the negative polarity. As a result, immediately after the polarity of the gradation reference voltage is inverted, a temporary voltage variance is created on the input line of the amplifier. Accordingly, the voltage variance may have an influence on the gradation voltage to cause a ripple, thereby causing deterioration of an image displayed on the liquid crystal display panel.

In view of the problems described above, an object of the present invention is to provide a drive device capable of solving the problems of the conventional drive device. In the present invention, it is possible to invert a polarity of a gradation voltage without causing deterioration of an image.

Further objects and advantages of the invention will be apparent from the following description of the invention.

In order to attain the objects described above, according to a first aspect of the present invention, a drive device for driving a display panel through alternately applying a positive polarity gradation voltage and a negative polarity gradation voltage corresponding to a brightness level indicated with a video signal to a data line of the display panel. The drive device includes an amplifier unit for alternately switching and applying a gradation reference voltage with a positive polarity and a gradation reference voltage with a negative polarity to an input line, and for amplifying a voltage applied to the input to obtain an amplified gradation voltage; and a voltage generation unit for generating the positive polarity gradation voltage and the negative polarity gradation voltage according to the amplified gradation voltage.

According to the first aspect of the present invention, the amplifier unit is arranged to select and apply to the input line one of the positive polarity gradation voltage and the negative polarity gradation voltage immediately before the amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity. The one of the positive polarity gradation voltage and the negative polarity gradation voltage has a polarity the same as that of one of the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity to be applied to the input line after the amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity.

According to a second aspect of the present invention, a drive device for driving a display panel through alternately applying a positive polarity gradation voltage and a negative polarity gradation voltage corresponding to a brightness level indicated with a video signal to a data line of the display panel. The drive device includes a first amplifier unit for alternately applying a gradation reference voltage with a positive polarity and a gradation reference voltage with a negative polarity to an input line, and for amplifying a voltage applied to the input to obtain a first amplified gradation voltage; and a second amplifier unit for alternately applying the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity in a phase different from that of the first amplifier unit to the input line, and for amplifying a voltage applied to the input to obtain a second amplified gradation voltage.

According to the second aspect of the present invention, the drive device further includes a first selection unit for selecting one of the first amplified gradation voltage and the first amplified gradation voltage having the positive polarity as a positive polarity drive gradation voltage; a second selection unit for selecting one of the first amplified gradation voltage and the first amplified gradation voltage having the negative polarity as a negative polarity drive gradation voltage; a positive polarity gradation voltage generation unit for generating the positive polarity gradation voltage according to the positive polarity drive gradation voltage; and a negative polarity gradation voltage generation unit for generating the negative polarity gradation voltage according to the negative polarity drive gradation voltage.

According to the second aspect of the present invention, the first amplifier unit is arranged to select one of the positive polarity gradation voltage and the negative polarity gradation voltage immediately before the first amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity. The one of the positive polarity gradation voltage and the negative polarity gradation voltage has a polarity the same as that of the gradation reference voltage with the positive polarity or the gradation reference voltage with the negative polarity to be applied to the input line after the first amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity.

According to the second aspect of the present invention, the second amplifier unit is arranged to select one of the positive polarity gradation voltage and the negative polarity gradation voltage immediately before the second amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity. The one of the positive polarity gradation voltage and the negative polarity gradation voltage has a polarity the same as that of the gradation reference voltage with the positive polarity or the gradation reference voltage with the negative polarity to be applied to the input line after the second amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity.

As described above, in the present invention, when the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity are alternately applied to the input line of the amplifier unit, immediately before the amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity, the amplifier unit is arranged to apply one of the positive polarity gradation voltage and the negative polarity gradation voltage having a polarity the same as that of the gradation reference voltage with the positive polarity or the gradation reference voltage with the negative polarity to be applied to the input line after the second amplifier unit switches between the gradation reference voltage with the positive polarity and the gradation reference voltage with the negative polarity.

Accordingly, a voltage variance on the input line becomes small between immediately before the polarity of the gradation reference voltage is switched and immediately after the polarity of the gradation reference voltage is switched. Therefore, it is possible to reduce a ripple generated in a waveform of the gradation voltage, thereby minimizing deterioration of an image to be displayed.

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device having a drive device according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of a data driver of the drive device according to the embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a gradation voltage generation unit of the data driver of the drive device according to the embodiment of the present invention;

FIG. 4 is a time chart showing a polarity inversion signal generated with a polarity inversion signal generation unit and a polarity inversion control signal generated with a polarity inversion control unit of the drive device according to the embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a polarity inversion control unit of the drive device according to the embodiment of the present invention;

FIG. 6 is a block diagram showing a configuration of a VREF amplifier of the drive device according to the embodiment of the present invention;

FIG. 7 is a block diagram showing configurations of a positive polarity side ladder resistor and a negative polarity side ladder resistor of the drive device according to the embodiment of the present invention; and

FIG. 8 is a time chart showing an internal operation of the gradation voltage generation unit of the drive device according to the embodiment of the present invention.

Hereunder, preferred embodiments of the present invention will be explained with reference to the accompanying drawings.

In embodiments of the present invention, a gradation reference voltage with a positive polarity and a gradation reference voltage with a negative polarity are alternately applied to an input line of a single amplifier unit to obtain an amplified gradation voltage. Then, a gradation voltage with a positive polarity or a gradation voltage with a negative polarity is generated according to the amplified gradation voltage. Immediately before the gradation reference voltage is switched, the gradation voltage having a polarity the same as that of the gradation reference voltage to be applied to the input line after the gradation reference voltage is switched is applied to the input line.

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device having a drive device according to the embodiment of the present invention. As shown in FIG. 1 , the liquid crystal display device includes a drive control unit 10 , a scanning driver 11 , a data driver 12 , and a display panel 20 as a color TFT (Thin Film Transistor) liquid crystal panel.

In the embodiment, the display panel 20 includes a number m of scanning lines S 1 to Sm arranged to extend in a horizontal direction of a two-dimensional screen and a number n of data lines D 1 to Dn arranged to extend in a vertical direction of the two-dimensional screen for driving a liquid crystal layer (not shown). A display cell functioning as a pixel (a red pixel, a green pixel, or a blue pixel) is disposed in an area (an area surrounded by a hidden line) at a crossing point of each of the scanning lines and each of the data lines. Each of the display cells includes a transistor (not shown) to be turned on according to a scanning pulse supplied from the scanning driver 11 through the scanning lines. When the transistor is turned on, a drive pulse supplied from the data driver 12 through the data lines is applied to electrodes sandwiching the liquid crystal layer.

In the embodiment, the drive control unit 10 is provided for generating a frame synchronization signal LS indicating a drive timing per frame and various drive control signals (described later) according to an input video signal, and for supplying the frame synchronization signal LS and the drive control signals to the scanning driver 11 and the data driver 12 . Further, the drive control unit 10 is provided for sequentially generating pixel data PD representing a brightness level per individual pixel with, for example, eight bits, and for supplying the pixel data PD to the data driver 12 .

In the embodiment, the scanning driver 11 is provided for generating a scanning pulse having a specific peak voltage according to the frame synchronization signal LS supplied from the drive control unit 10 , and for sequentially and selectively supplying the scanning pulse to each of the scanning lines S 1 to Sm of the display panel 20 .

In the embodiment, the data driver 12 is provided for generating a drive pulse having a gradation voltage corresponding to the brightness level represented with the pixel data per the pixel data PD of each of the pixels supplied from the drive control unit 10 , and for applying the drive pulse to each of the data lines D 1 to Dn of the display panel 20 .

FIG. 2 is a block diagram showing a configuration of the data driver 12 of the drive device according to the embodiment of the present invention. As shown in FIG. 2 , the data driver 12 includes a data latch 120 , gradation voltage selection units 1211 to 121 n , and a gradation voltage generation unit 122 .

In the embodiment, the data latch 120 is provided for sequentially retrieving the pixel data supplied from the drive control unit 10 . Every time the data latch 120 retrieves the pixel data for one horizontal scanning line (the n number), the data latch 120 is provided for supplying the n number of pixel data PD 1 to PD 2 to the gradation voltage selection units 1211 to 121 n , respectively.

In the embodiment, each of the gradation voltage selection units 1211 to 121 n is provided for selecting a pair of a positive polarity gradation voltage and a negative polarity gradation voltage (vh and vl) having a gradation voltage (an absolute value) corresponding to the brightness level indicated with the pixel data PD among positive polarity gradation voltages vh 0 to vh 63 and negative polarity gradation voltages vl 0 to vl 63 supplied from the gradation voltage generation unit 122 . Further, each of the gradation voltage selection units 1211 to 121 n is provided for alternately applying on a periodic basis the drive pulse having the positive polarity gradation voltage vh thus selected and the drive pulse having the negative polarity gradation voltage vl thus selected to the data lines D 1 to Dn of the display panel 20 .

For example, when the pixel data PD 1 indicating the maximum brightness level is supplied to the gradation voltage selection unit 1211 , the gradation voltage selection unit 1211 selects the positive polarity gradation voltage vh 63 and the negative polarity gradation voltage vl 63 corresponding to the maximum brightness level among the positive polarity gradation voltages vh 0 to vh 63 and the negative polarity gradation voltages vl 0 to vl 63 . Then, the gradation voltage selection unit 1211 alternately applies on a periodic basis the drive pulse having the positive polarity gradation voltage vh 63 and the drive pulse having the negative polarity gradation voltage vl 63 to the data line D 1 of the display panel 20 . As described above, when the drive pulse having the positive polarity gradation voltage vh and the drive pulse having the negative polarity gradation voltage vl are alternately applied on a periodic basis to the data line D of the display panel 20 , it is possible to prevent screen deterioration of the display panel 20 similar to burning out.

FIG. 3 is a block diagram showing a configuration of the gradation voltage generation unit 122 of the data driver 12 of the drive device according to the embodiment of the present invention. In the embodiment, the gradation voltage generation unit 122 is provided for generating the gradation voltages with the positive polarity vh 0 to vh 63 and the gradation voltages with the negative polarity vl 0 to vl 63 .

As shown in FIG. 3 , the gradation voltage generation unit 122 includes VREF amplifier AH 1 to AH 5 as a positive polarity gradation voltage generation unit; selectors SH 1 to SH 5 ; a positive polarity side ladder resistor RH; VREF amplifier AL 1 to AL 5 as a negative polarity gradation voltage generation unit; selectors SL 1 to SL 5 ; a positive polarity side ladder resistor RH; a polarity inversion signal generation unit RV; and a polarity inversion control unit RC.

In the embodiment, the polarity inversion signal generation unit RV is provided for generating a polarity inversion signal REV for switching from a logic level 1 to a logic level 0 or from a logic level 0 to a logic level 1 (refer to FIG. 4 ) according to the frame synchronization signal LS supplied from the drive control unit 10 . Further, the polarity inversion signal generation unit RV is provided for supplying the polarity inversion signal REV to each of the polarity inversion control unit RC, the selectors SH 1 to SH 5 , and the selectors SL 1 to S 15 .

In the embodiment, the polarity inversion control unit RC is provided for generating polarity inversion control signals TA to TD and QTA to QTD.

FIG. 5 is a block diagram showing a configuration of the polarity inversion control unit RC of the drive device according to the embodiment of the present invention.

As shown in FIG. 5 , the polarity inversion control unit RC includes a delay circuit D 1 . The delay circuit D 1 is provided for supplying a signal obtained by delaying the polarity inversion signal REV by a specific period of time d 1 to an or gate OR 1 and an and gate AD 1 . The or gate OR 1 is provided for determining a logic sum of the polarity inversion signal REV and the signal obtained by delaying the polarity inversion signal REV by a specific period of time d 1 , and for outputting a signal representing the logic sum as a polarity inversion control signal TA. The and gate AD 1 is provided for determining a logic product of the polarity inversion signal REV and the signal obtained by delaying the polarity inversion signal REV by a specific period of time d 1 , and for outputting a signal representing the logic product as a polarity inversion control signal TB.

In the embodiment, the polarity inversion control unit RC further includes a delay circuit D 2 . The delay circuit D 2 is provided for supplying a signal obtained by delaying the polarity inversion signal REV by a specific period of time d 2 shorter than a specific period of time d 1 to an inverter V 1 . The inverter V 1 is provided for supplying a signal obtained by inverting a logic level of the polarity inversion signal REV delayed by a specific period of time d 2 to a nor gate NR 1 . The nor gate NR 1 is provided for determining a logic product of the signal obtained by inverting the logic level of the polarity inversion signal REV and the signal obtained by delaying the polarity inversion signal REV by a specific period of time d 2 through the delay circuit D 2 , and for outputting a signal representing the logic product as a polarity inversion control signal TC.

In the embodiment, the polarity inversion control unit RC further includes a delay circuit D 3 . The delay circuit D 3 is provided for supplying a signal obtained by delaying the polarity inversion signal REV by a specific period of time d 2 to an inverter V 2 . The inverter V 2 is provided for supplying a signal obtained by inverting the logic level of the polarity inversion signal REV delayed by a specific period of time d 2 to a nand gate ND 1 . The nand gate ND 1 is provided for determining a logic product of the signal obtained by inverting the logic level of the polarity inversion signal REV and the signal obtained by delaying the polarity inversion signal REV by a specific period of time d 2 through the delay circuit D 3 , and for outputting a signal representing the logic product as a polarity inversion control signal TD.

In the embodiment, the polarity inversion control unit RC further includes an inverter V 3 . The inverter V 3 is provided for supplying a signal obtained by inverting the logic level of the polarity inversion signal REV as a polarity inversion signal REV 1 to an or gate OR 2 , an and gate AD 2 , a nor gate NR 2 , a nand gate ND 2 , a delay circuit D 4 , a delay circuit D 5 , and a delay circuit D 6 .

In the embodiment, the polarity inversion control unit RC further includes a delay circuit D 4 . The delay circuit D 4 is provided for supplying a signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 1 to an or gate OR 2 and an and gate AD 2 . The or gate OR 2 is provided for determining a logic sum of the polarity inversion signal REV 1 and the signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 1 , and for outputting a signal representing the logic sum as a polarity inversion control signal QTA. The and gate AD 2 is provided for determining a logic product of the polarity inversion signal REV 1 and the signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 1 , and for outputting a signal representing the logic product as a polarity inversion control signal QTB.

In the embodiment, the polarity inversion control unit RC further includes a delay circuit D 5 . The delay circuit D 5 is provided for supplying a signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 2 to an inverter V 4 . The inverter V 4 is provided for supplying a signal obtained by inverting a logic level of the polarity inversion signal REV 1 delayed by a specific period of time d 2 to the nor gate NR 2 . The nor gate NR 2 is provided for determining a logic product of the signal obtained by inverting the logic level of the polarity inversion signal REV 1 and the signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 2 through the delay circuit D 5 , and for outputting a signal representing the logic product as a polarity inversion control signal QTC.

In the embodiment, the polarity inversion control unit RC further includes a delay circuit D 6 . The delay circuit D 6 is provided for supplying a signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 2 to an inverter V 5 . The inverter V 5 is provided for supplying a signal obtained by inverting the logic level of the polarity inversion signal REV 1 delayed by a specific period of time d 2 to the nand gate ND 2 . The nand gate ND 2 is provided for determining a logic product of the signal obtained by inverting the logic level of the polarity inversion signal REV 1 and the signal obtained by delaying the polarity inversion signal REV 1 by a specific period of time d 2 through the delay circuit D 6 , and for outputting a signal representing the logic product as a polarity inversion control signal QTD.

With the configuration described above, according to the polarity inversion signal REV supplied from the polarity inversion signal generation unit RV, the polarity inversion control unit RC generates the polarity inversion control signals TA to TD and QTA to QTD changing from the logic level 0 to the logic level 1 or from the logic level 1 to the logic level 0 at the timings shown in FIG. 4 . FIG. 4 is a time chart showing the polarity inversion signal generated with the polarity inversion signal generation unit RV and the polarity inversion control signal generated with the polarity inversion control unit RC of the drive device according to the embodiment of the present invention.

As shown in FIG. 4 , when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1, the polarity inversion control signal TA is similarly switched from the logic level 0 to the logic level 1. Further, when the polarity inversion signal REV is switched from the logic level 1 to the logic level 0, the polarity inversion control signal TA is switched from the logic level 1 to the logic level 0 after the specific period of time d 1 is elapsed. When the polarity inversion signal REV is switched from the logic level 1 to the logic level 0, the polarity inversion control signal TB is similarly switched from the logic level 1 to the logic level 0. Further, when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1, the polarity inversion control signal TB is switched from the logic level 0 to the logic level 1 after the specific period of time d 1 is elapsed.

In the embodiment, the polarity inversion control signal TC becomes the logic level 1 for the specific period of time d 2 only when the polarity inversion signal REV is switched from the logic level 1 to the logic level 0. Further, the polarity inversion control signal TD becomes the logic level 1 for the specific period of time d 2 only when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1. When the polarity inversion signal REV 1 is switched from the logic level 0 to the logic level 1, the polarity inversion control signal QTA is similarly switched from the logic level 0 to the logic level 1. Further, when the polarity inversion signal REV 1 is switched from the logic level 1 to the logic level 0, the polarity inversion control signal QTA is switched from the logic level 1 to the logic level 0 after the specific period of time d 1 is elapsed.

As shown in FIG. 4 , when the polarity inversion signal REV 1 is switched from the logic level 1 to the logic level 0, the polarity inversion control signal QTB is similarly switched from the logic level 1 to the logic level 0. Further, when the polarity inversion signal REV 1 is switched from the logic level 0 to the logic level 1, the polarity inversion control signal QTB is switched from the logic level 0 to the logic level 1 after the specific period of time dl is elapsed. Further, the polarity inversion control signal QTC becomes the logic level 1 for the specific period of time d 2 only when the polarity inversion signal REV 1 is switched from the logic level 1 to the logic level 0. Further, the polarity inversion control signal QTD becomes the logic level 1 for the specific period of time d 2 only when the polarity inversion signal REV 1 is switched from the logic level 0 to the logic level 1.

In the embodiment, the polarity inversion control unit RC is provided for supplying the polarity inversion control signals Ta to TD to the VREF amplifiers AH 1 to AH 5 , respectively, and for supplying the polarity inversion control signals QTA to QTD to the VREF amplifiers AL 1 to AL 5 , respectively.

In the embodiment, an entire range of brightness capable of being displayed with the input video signal is divided into 64 scales from the zero gradation to the 63rd gradation. each of the VREF amplifiers AH 1 to AH 5 and the VREF amplifiers AL 1 to AL 5 corresponding to the 63rd gradation, the 55th gradation, the 31st gradation, the 7th gradation, and the zero gradation are constantly applied to each of the VREF amplifiers AH 1 to AH 5 . Similarly, gradation reference voltages with the negative polarity VL 63 , VL 55 , VL 31 , VL 7 , and VL 0 corresponding to the 63th gradation, the 55th gradation, the 31st gradation, the seventh gradation, and the zero-th gradation are constantly applied to each of the VREF amplifiers AL 1 to AL 5 .

More specifically, as shown in FIG. 3 , the gradation reference voltage with the positive polarity VH 63 and the gradation reference voltage with the negative polarity VL 63 are applied to the VREF amplifier AH 1 , and the gradation reference voltage with the positive polarity VH 55 and the gradation reference voltage with the negative polarity VL 55 are applied to the VREF amplifier AH 2 . Further, the gradation reference voltage with the positive polarity VH 31 and the gradation reference voltage with the negative polarity VL 31 are applied to the VREF amplifier AH 3 , and the gradation reference voltage with the positive polarity VH 7 and the gradation reference voltage with the negative polarity VL 7 are applied to the VREF amplifier AH 4 . Lastly, the gradation reference voltage with the positive polarity VH 0 and the gradation reference voltage with the negative polarity VL 0 are applied to the VREF amplifier AH 5 .

In the embodiment, each of the VREF amplifiers AH 1 to AH 5 and the VREF amplifiers AL 1 to AL 5 has an identical configuration. FIG. 6 is a block diagram showing a configuration of each of the VREF amplifiers AH 1 to AH 5 and the VREF amplifiers AL 1 to AL 5 of the drive device according to the embodiment of the present invention.

As shown in FIG. 6 , each of the VREF amplifiers AH 1 to AH 5 and the VREF amplifiers AL 1 to AL 5 includes transmission gates TG 1 to TG 4 as first to fourth switching elements; inverters V 11 to V 14 , and an operation amplifier AMP formed of a voltage follower circuit.

In the embodiment, the gradation reference voltage with the positive polarity VH (VH 63 , VH 55 , VH 31 , VH 7 , or VH 0 ) is constantly supplied to the transmission gate TG 1 . Further, the polarity inversion control signal TA (QTA) is supplied to a p-channel gate terminal of the transmission gate TG 1 , and the signal obtained through inverting the logic level of the polarity inversion control signal TA (QTA) with the inverter V 11 is supplied to an n-channel gate terminal of the transmission gate TG 1 . Accordingly, when the polarity inversion control signal TA (QTA) is at the logic level 1, the transmission gate TG 1 is turned off. When the polarity inversion control signal TA (QTA) is at the logic level 0, the transmission gate TG 1 is turned on, so that the transmission gate TG 1 applies the gradation reference voltage with the positive polarity VH constantly supplied thereto to the input line L 1 .

In the embodiment, the gradation voltage with the positive polarity vh (vh 63 , vh 55 , vh 31 , vh 7 , or vh 0 ) generated with the positive polarity side ladder resistor RH (described later) is supplied to the transmission gate TG 3 . Further, the polarity inversion control signal TC (QTC) is supplied to an n-channel gate terminal of the transmission gate TG 3 , and the signal obtained through inverting the logic level of the polarity inversion control signal TC (QTC) with the inverter V 13 is supplied to a p-channel gate terminal of the transmission gate TG 3 . Accordingly, when the polarity inversion control signal TC (QTC) is at the logic level 0, the transmission gate TG 3 is turned off. When the polarity inversion control signal TC (QTC) is at the logic level 1, the transmission gate TG 3 is turned on, so that the transmission gate TG 3 applies the gradation voltage with the positive polarity vh supplied thereto to the input line L 1 .

In the embodiment, the gradation voltage with the negative polarity vl (vl 63 , vl 55 , vl 31 , vl 7 , or vl 0 ) generated with the negative polarity side ladder resistor RL (described later) is supplied to the transmission gate TG 4 . Further, the polarity inversion control signal TD (QTD) is supplied to an re-channel gate terminal of the transmission gate TG 4 , and the signal obtained through inverting the logic level of the polarity inversion control signal TD (QTD) with the inverter V 14 is supplied to a p-channel gate terminal of the transmission gate TG 4 . Accordingly, when the polarity inversion control signal TD (QTD) is at the logic level 0, the transmission gate TG 4 is turned off. When the polarity inversion control signal TD (QTD) is at the logic level 1, the transmission gate TG 4 is turned on, so that the transmission gate TG 3 applies the gradation voltage with the negative polarity vl supplied thereto to the input line L 1 .

In the embodiment, the gradation voltage with the negative polarity vl (vl 63 , vl 55 , vl 31 , vl 7 , or vl 0 ) generated with the negative polarity side rudder resistor RL (described later) is supplied to the transmission gate TG 4 . Further, the polarity inversion control signal TD (QTD) is supplied to an n-channel gate terminal of the transmission gate TG 4 , and the signal obtained through inverting the logic level of the polarity inversion control signal TD (QTD) with the inverter V 14 is supplied to a p-channel gate terminal of the transmission gate TG 4 . Accordingly, when the polarity inversion control signal TD (QTD) is at the logic level 0, the transmission gate TG 4 is turned off. When the polarity inversion control signal TD (QTD) is at the logic level 1, the transmission gate TG 4 is turned on, so that the transmission gate TG 3 applies the gradation voltage with the negative polarity vl supplied thereto to the input line L 1 .

In the embodiment, the operation amplifier AMP is provided for generating an amplified gradation voltage VX (VY) having a voltage value the same as that of the voltage (VH, VL, vh, or vl) applied to the input line L 1 .

With the configuration described above, in the embodiment, the VREF amplifier AH 1 selects one of the gradation reference voltages VH 63 and VL 63 and the gradation voltages vh 63 and vl 63 at the timing corresponding to the polarity inversion control signals TA to TD as shown in FIG. 4 . Then, the VREF amplifier AH 1 supplies an amplified gradation voltage VX 63 having a voltage value the same as that of selected one of the gradation reference voltages VH 63 and VL 63 and the gradation voltages vh 63 and vl 63 to each of the selectors SH 1 and SL 1 .

Similarly, in the embodiment, the VREF amplifier AH 2 selects one of the gradation reference voltages VH 55 and VL 55 and the gradation voltages vh 55 and vl 55 at the timing corresponding to the polarity inversion control signals TA to TD as shown in FIG. 4 . Then, the VREF amplifier AH 2 supplies an amplified gradation voltage VX 55 having a voltage value the same as that of selected one of the gradation reference voltages VH 55 and VL 55 and the gradation voltages vh 55 and vl 55 to each of the selectors SH 2 and SL 2 .

Similarly, in the embodiment, the VREF amplifier AH 3 selects one of the gradation reference voltages VH 31 and VL 31 and the gradation voltages vh 31 and vl 31 at the timing corresponding to the polarity inversion control signals TA to TD as shown in FIG. 4 . Then, the VREF amplifier AH 3 supplies an amplified gradation voltage VX 31 having a voltage value the same as that of selected one of the gradation reference voltages VH 31 and VL 31 and the gradation voltages vh 31 and vl 31 to each of the selectors SH 3 and SL 3 .

Similarly, in the embodiment, the VREF amplifier AH 4 selects one of the gradation reference voltages VH 7 and VL 7 and the gradation voltages vh 7 and vl 7 at the timing corresponding to the polarity inversion control signals TA to TD as shown in FIG. 4 . Then, the VREF amplifier AH 4 supplies an amplified gradation voltage VX 7 having a voltage value the same as that of selected one of the gradation reference voltages VH 7 and VL 7 and the gradation voltages vh 7 and vl 7 to each of the selectors SH 4 and SL 4 .

Similarly, in the embodiment, the VREF amplifier AH 5 selects one of the gradation reference voltages VH 0 and VL 0 and the gradation voltages vh 0 and vl 0 at the timing corresponding to the polarity inversion control signals TA to TD as shown in FIG. 4 . Then, the VREF amplifier AH 5 supplies an amplified gradation voltage VX 0 having a voltage value the same as that of selected one of the gradation reference voltages VH 0 and VL 0 and the gradation voltages vh 0 and vl 0 to each of the selectors SH 5 and SL 5 .

Further, in the embodiment, the VREF amplifier AL 1 selects one of the gradation reference voltages VH 63 and VL 63 and the gradation voltages vh 63 and vl 63 at the timing corresponding to the polarity inversion control signals QTA to QTD as shown in FIG. 4 . Then, the VREF amplifier AL 1 supplies an amplified gradation voltage VY 63 having a voltage value the same as that of selected one of the gradation reference voltages VH 63 and VL 63 and the gradation voltages vh 63 and vl 63 to each of the selectors SH 1 and SL 1 .

Similarly, in the embodiment, the VREF amplifier AL 2 selects one of the gradation reference voltages VH 55 and VL 55 and the gradation voltages vh 55 and vl 55 at the timing corresponding to the polarity inversion control signals QTA to QTD as shown in FIG. 4 . Then, the VREF amplifier AL 2 supplies an amplified gradation voltage VY 55 having a voltage value the same as that of selected one of the gradation reference voltages VH 55 and VL 55 and the gradation voltages vh 55 and vl 55 to each of the selectors SH 2 and SL 2 .

Similarly, in the embodiment, the VREF amplifier AL 3 selects one of the gradation reference voltages VH 31 and VL 31 and the gradation voltages vh 31 and vl 31 at the timing corresponding to the polarity inversion control signals QTA to QTD as shown in FIG. 4 . Then, the VREF amplifier AL 3 supplies an amplified gradation voltage VY 31 having a voltage value the same as that of selected one of the gradation reference voltages VH 31 and VL 31 and the gradation voltages vh 31 and vl 31 to each of the selectors SH 3 and SL 3 .

Similarly, in the embodiment, the VREF amplifier AL 4 selects one of the gradation reference voltages VH 7 and VL 7 and the gradation voltages vh 7 and vl 7 at the timing corresponding to the polarity inversion control signals QTA to QTD as shown in FIG. 4 . Then, the VREF amplifier AL 4 supplies an amplified gradation voltage VY 7 having a voltage value the same as that of selected one of the gradation reference voltages VH 7 and VL 7 and the gradation voltages vh 7 and vl 7 to each of the selectors SH 4 and SL 4 .

Similarly, in the embodiment, the VREF amplifier AL 5 selects one of the gradation reference voltages VH 0 and VL 0 and the gradation voltages vh 0 and vl 0 at the timing corresponding to the polarity inversion control signals QTA to QTD as shown in FIG. 4 . Then, the VREF amplifier AL 5 supplies an amplified gradation voltage VY 0 having a voltage value the same as that of selected one of the gradation reference voltages VH 0 and VL 0 and the gradation voltages vh 0 and vl 0 to each of the selectors SH 5 and SL 5 .

In the embodiment, the selector SH 1 selects one of the amplified gradation voltages VY 63 and VX 63 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SH 1 selects the amplified gradation voltage VX 63 , and when the polarity inversion signal REV is at the logic level 0, the selector SH 1 selects the amplified gradation voltage VY 63 . Then, the selector SH 1 supplies selected one of the amplified gradation voltages VY 63 and VX 63 as a positive polarity drive gradation voltage GH 63 to the positive polarity side ladder resistor RH.

In the embodiment, the selector SH 2 selects one of the amplified gradation voltages VY 55 and VX 55 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SH 2 selects the amplified gradation voltage VX 55 , and when the polarity inversion signal REV is at the logic level 0, the selector SH 2 selects the amplified gradation voltage VY 55 . Then, the selector SH 2 supplies selected one of the amplified voltages VY 55 and VX 55 as a positive polarity drive gradation voltage GH 55 to the positive polarity side ladder resistor RH.

In the embodiment, the selector SH 3 selects one of the amplified gradation voltages VY 31 and VX 31 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SH 3 selects the amplified gradation voltage VX 31 , and when the polarity inversion signal REV is at the logic level 0, the selector SH 3 selects the amplified gradation voltage VY 31 . Then, the selector SH 3 supplies selected one of the amplified voltages VY 31 and VX 31 as a positive polarity drive gradation voltage GH 31 to the positive polarity side ladder resistor RH.

In the embodiment, the selector SH 4 selects one of the amplified gradation voltages VY 7 and VX 7 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SH 4 selects the amplified gradation voltage VX 7 , and when the polarity inversion signal REV is at the logic level 0, the selector SH 4 selects the amplified gradation voltage VY 7 . Then, the selector SH 4 supplies selected one of the amplified voltages VY 7 and VX 7 as a positive polarity drive gradation voltage GH 7 to the positive polarity side ladder resistor RH.

In the embodiment, the selector SH 5 selects one of the amplified gradation voltages VY 0 and VX 0 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SH 5 selects the amplified gradation voltage VX 0 , and when the polarity inversion signal REV is at the logic level 0, the selector SH 5 selects the amplified gradation voltage VY 0 . Then, the selector SH 5 supplies selected one of the amplified voltages VY 0 and VX 0 as a positive polarity drive gradation voltage GH 0 to the positive polarity side ladder resistor RH.

FIG. 7 is a block diagram showing configurations of the positive polarity side ladder resistor RH and the negative polarity side ladder resistor LH of the drive device according to the embodiment of the present invention.

As shown in FIG. 7 , the positive polarity side ladder resistor RH includes 63 resistors R 1 to R 63 connected in series. The positive polarity drive gradation voltage GH 0 supplied from the selector SH 5 is applied to one end portion of the resistor R 1 of the positive polarity side ladder resistor RH, and the other end portion of the resistor R 1 is connected to one end portion of the resistor R 2 .

In the embodiment, the positive polarity drive gradation voltage GH 7 supplied from the selector SH 4 is applied to a connecting point of the resistors R 7 and R 8 of the positive polarity side ladder resistor RH. The positive polarity drive gradation voltage GH 31 supplied from the selector SH 3 is applied to a connecting point of the resistors R 31 and R 32 of the positive polarity side ladder resistor RH. The positive polarity drive gradation voltage GH 55 supplied from the selector SH 2 is applied to a connecting point of the resistors R 55 and R 55 of the positive polarity side ladder resistor RH. Further, in the positive polarity side ladder resistor RH, one end portion of the resistor R 62 is connected to one end portion of the resistor R 63 . The positive polarity drive gradation voltage GH 63 supplied from the selector SH 1 is applied to the other end portion of the resistor R 63 .

Accordingly, the gradation voltages with the positive polarity vh 0 to vh 63 for the 64 scales are generated at the connecting points of the resistors R 0 to R 63 according to the positive polarity drive gradation voltages GH 0 , GH 7 , GH 31 , GH 55 , and GH 63 applied to the five connecting points of the positive polarity side ladder resistor RH. The gradation voltages with the positive polarity vh 0 to vh 63 have different voltage values, and are supplied to each of the gradation voltage selection units 1211 to 121 n . In other words, the positive polarity side ladder resistor RH generates the gradation voltages with the positive polarity vh 0 to vh 63 as the gradation voltages corresponding to each of the zero scale to the 63rd scale of the brightness range divided into the 64 scales that the input video signal can display.

In the embodiment, among the gradation voltages with the positive polarity vh 0 to vh 63 , the gradation voltage with the positive polarity vh 63 is supplied to each of the VREF amplifiers AH 1 and AL 1 . The gradation voltage with the positive polarity vh 55 is supplied to each of the VREF amplifiers AH 2 and AL 2 . The gradation voltage with the positive polarity vh 31 generated with the positive polarity side ladder resistor RH is supplied to each of the VREF amplifiers AH 3 and AL 3 . The gradation voltage with the positive polarity vh 7 is supplied to each of the VREF amplifiers AH 4 and AL 4 . The gradation voltage with the positive polarity vh 0 is supplied to each of the VREF amplifiers AH 5 and AL 5 .

In the embodiment, the selector SL 1 selects one of the amplified gradation voltages VY 63 and VX 63 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SL 1 selects the amplified gradation voltage VY 63 , and when the polarity inversion signal REV is at the logic level 0, the selector SL 1 selects the amplified gradation voltage VX 63 . Then, the selector SL 1 supplies selected one of the amplified gradation voltages VY 63 and VX 63 as a negative polarity drive gradation voltage GL 63 to the negative polarity side ladder resistor RL.

In the embodiment, the selector SL 2 selects one of the amplified gradation voltages VY 55 and VX 55 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SL 2 selects the amplified gradation voltage VY 55 , and when the polarity inversion signal REV is at the logic level 0, the selector SL 2 selects the amplified gradation voltage VX 55 . Then, the selector SL 2 supplies selected one of the amplified voltages VY 55 and VX 55 as a negative polarity drive gradation voltage GL 55 to the negative polarity side ladder resistor RL.

In the embodiment, the selector SL 3 selects one of the amplified gradation voltages VY 31 and VX 31 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SL 3 selects the amplified gradation voltage VY 31 , and when the polarity inversion signal REV is at the logic level 0, the selector SL 3 selects the amplified gradation voltage VX 31 . Then, the selector SL 3 supplies selected one of the amplified voltages VY 31 and VX 31 as a negative polarity drive gradation voltage GL 31 to the negative polarity side ladder resistor RL.

In the embodiment, the selector SL 4 selects one of the amplified gradation voltages VY 7 and VX 7 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector SL 4 selects the amplified gradation voltage VY 7 , and when the polarity inversion signal REV is at the logic level 0, the selector SL 4 selects the amplified gradation voltage VX 7 . Then, the selector SL 4 supplies selected one of the amplified voltages VY 7 and VX 7 as a negative polarity drive gradation voltage GL 7 to the negative polarity side ladder resistor RL.

In the embodiment, the selector SL 5 selects one of the amplified gradation voltages VY 0 and VX 0 according to the logic level of the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 1, the selector S 15 selects the amplified gradation voltage VY 0 , and when the polarity inversion signal REV is at the logic level 0, the selector SL 5 selects the amplified gradation voltage VX 0 . Then, the selector SL 5 supplies selected one of the amplified voltages VY 0 and VX 0 as a negative polarity drive gradation voltage GL 0 to the negative polarity side ladder resistor RL.

In the embodiment, the negative polarity side ladder resistor LH has a configuration identical to that of the positive polarity side ladder resistor RH shown in FIG. 7 . The negative polarity drive gradation voltage GL 0 supplied from the selector SL 5 is applied to one end portion of the resistor R 1 of the negative polarity side ladder resistor RL, and the other end portion of the resistor R 1 is connected to one end portion of the resistor R 2 .

In the embodiment, the negative polarity drive gradation voltage GL 7 supplied from the selector SL 4 is applied to a connecting point of the resistors R 7 and R 8 of the negative polarity side ladder resistor RL. The negative polarity drive gradation voltage GL 31 supplied from the selector SL 3 is applied to a connecting point of the resistors R 31 and R 32 of the negative polarity side ladder resistor RL. The negative polarity drive gradation voltage GL 55 supplied from the selector SL 2 is applied to a connecting point of the resistors R 55 and R 55 of the negative polarity side ladder resistor RL. Further, in the negative polarity side ladder resistor RL, one end portion of the resistor R 62 is connected to one end portion of the resistor R 63 . The negative polarity drive gradation voltage GL 63 supplied from the selector SL 1 is applied to the other end portion of the resistor R 63 .

Accordingly, the gradation voltages with the negative polarity vl 0 to vl 63 for the 64 scales are generated at the connecting points of the resistors R 0 to R 63 according to the negative polarity drive gradation voltages GL 0 , GL 7 , GL 31 , GL 55 , and GL 63 applied to the five connecting points of the negative polarity side ladder resistor RL. The gradation voltages with the negative polarity vl 0 to vl 63 have different voltage values, and are supplied to each of the gradation voltage selection units 1211 to 121 n . In other words, the negative polarity side ladder resistor RL generates the gradation voltages with the negative polarity vl 0 to vl 63 as the gradation voltages corresponding to each of the zero scale to the 63rd scale of the brightness range divided into the 64 scales that the input video signal can display.

In the embodiment, among the gradation voltages with the negative polarity vl 0 to vl 63 , the gradation voltage with the negative polarity vl 63 is supplied to each of the VREF amplifiers AH 1 and AL 1 . The gradation voltage with the negative polarity vl 55 is supplied to each of the VREF amplifiers AH 2 and AL 2 . The gradation voltage with the negative polarity vl 31 generated with the negative polarity side ladder resistor RL is supplied to each of the VREF amplifiers AH 3 and AL 3 . The gradation voltage with the negative polarity vl 7 is supplied to each of the VREF amplifiers AH 4 and AL 4 . The gradation voltage with the negative polarity vl 0 is supplied to each of the VREF amplifiers AH 5 and AL 5 .

An internal operation of the gradation voltage generation unit 122 having the configuration shown in FIG. 3 will be explained next with reference to FIG. 8 . In the operation, mainly the selectors Sh 1 and SL 1 and the VREF amplifiers AH 1 and AL 1 for generating the 63rd gradation voltage, that is, the positive polarity gradation voltage vh 63 and the negative polarity gradation voltage vl 63 , will be focused. FIG. 8 is a time chart showing the internal operation of the gradation voltage generation unit 122 of the drive device according to the embodiment of the present invention.

In the embodiment, each of the transmission gates TG 1 to TG 4 of the VREF amplifier AH 1 are switched from the on state to the off state or from the off state to the on state at timings shown in FIG. 8 according to the polarity inversion control signals TA to TD generated based on the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 0, the transmission gate TG 1 is turned on according to the polarity inversion control signal TA with the logic level 0. Accordingly, the gradation reference voltage with the positive polarity VH 63 is supplied to the operation amplifier AMP through the input line L 1 . As a result, during this period of time, as shown in FIG. 8 , the VREF amplifier AH 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation reference voltage with the positive polarity VH 63 .

Further, when the polarity inversion signal REV is at the logic level 1, the transmission gate TG 2 is turned on according to the polarity inversion control signal TB with the logic level 1. Accordingly, the gradation reference voltage with the negative polarity VL 63 is supplied to the operation amplifier AMP through the input line L 1 . As a result, during this period of time, as shown in FIG. 8 , the VREF amplifier AH 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation reference voltage with the negative polarity VL 63 .

In the embodiment, as shown in FIG. 8 , during a period of time from when the polarity inversion signal REV is switched from the logic level 1 to the logic level 0 to when the specific period of time d 1 is elapsed, both the transmission gates TG 1 and TG 2 are in the off state, and the transmission gate TG 3 is in the on state for the specific period of time d 2 (d 2 is smaller than d 1 , d 2 <d 1 ). Accordingly, during this period of time, the gradation voltage with the positive polarity vh 63 generated with the positive polarity side ladder resistor RH is supplied to the operation amplifier AMP through the input line L 1 . As a result, as shown in FIG. 8 , the VREF amplifier AH 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation voltage with the positive polarity vh 63 .

Further, in the embodiment, as shown in FIG. 8 , during a period of time from when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1 to when the specific period of time d 1 is elapsed, both the transmission gates TG 1 and TG 2 are in the off state, and the transmission gate TG 4 is in the on state for the specific period of time d 2 (d 2 is smaller than d 1 , d 2 <d 1 ). Accordingly, during this period of time, the gradation voltage with the negative polarity vl 63 generated with the negative polarity side ladder resistor RL is supplied to the operation amplifier AMP through the input line L 1 . As a result, as shown in FIG. 8 , the VREF amplifier AH 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation voltage with the negative polarity vl 63 .

As explained above, when the polarity inversion signal REV is at the logic level 0, the VREF amplifier AH 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation reference voltage with the positive polarity VH 63 or the gradation voltage with the positive polarity vh 63 . On the other hand, when the polarity inversion signal REV is at the logic level 1, the VREF amplifier AH 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation reference voltage with the negative polarity VL 63 or the gradation voltage with the negative polarity vl 63 . In other words, depending on the logic level of the polarity inversion signal REV, the VREF amplifier AH 1 alternately generates the gradation reference voltage with the positive polarity VH 63 or the gradation voltage with the positive polarity vh 63 , and the gradation reference voltage with the negative polarity VL 63 or the gradation voltage with the negative polarity vl 63 .

In the embodiment, each of the transmission gates TG 1 to TG 4 of the VREF amplifier AL 1 are switched from the on state to the off state or from the off state to the on state at timings shown in FIG. 8 according to the polarity inversion control signals QTA to QTD generated based on the polarity inversion signal REV. More specifically, when the polarity inversion signal REV is at the logic level 0, the transmission gate TG 2 is turned on according to the polarity inversion control signal QTA with the logic level 1. Accordingly, the gradation reference voltage with the negative polarity VL 63 is supplied to the operation amplifier AMP through the input line L 1 . As a result, during this period of time, as shown in FIG. 8 , the VREF amplifier AL 1 generates the amplified gradation voltage VY 63 having the voltage the same as that of the gradation reference voltage with the negative polarity VL 63 .

Further, when the polarity inversion signal REV is at the logic level 1, the transmission gate TG 1 is turned on according to the polarity inversion control signal QTA with the logic level 0. Accordingly, the gradation reference voltage with the positive polarity VH 63 is supplied to the operation amplifier AMP through the input line L 1 . As a result, during this period of time, as shown in FIG. 8 , the VREF amplifier AL 1 generates the amplified gradation voltage VY 63 having the voltage the same as that of the gradation reference voltage with the positive polarity VH 63 .

In the embodiment, as shown in FIG. 8 , during a period of time from when the polarity inversion signal REV is switched from the logic level 1 to the logic level 0 to when the specific period of time d 1 is elapsed, both the transmission gates TG 1 and TG 2 are in the off state, and the transmission gate TG 4 is in the on state for the specific period of time d 2 (d 2 is smaller than d 1 , d 2 <d 1 ). Accordingly, during this period of time, the gradation voltage with the negative polarity vl 63 generated with the negative polarity side ladder resistor RL is supplied to the operation amplifier AMP through the input line L 1 . As a result, as shown in FIG. 8 , the VREF amplifier AL 1 generates the amplified gradation voltage VY 63 having the voltage the same as that of the gradation voltage with the negative polarity vl 63 .

Further, in the embodiment, as shown in FIG. 8 , during a period of time from when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1 to when the specific period of time d 1 is elapsed, both the transmission gates TG 1 and TG 2 are in the off state, and the transmission gate TG 3 is in the on state for the specific period of time d 2 (d 2 is smaller than d 1 , d 2 <d 1 ). Accordingly, during this period of time, the gradation voltage with the positive polarity vh 63 generated with the positive polarity side ladder resistor RH is supplied to the operation amplifier AMP through the input line L 1 . As a result, as shown in FIG. 8 , the VREF amplifier AL 1 generates the amplified gradation voltage VX 63 having the voltage the same as that of the gradation voltage with the positive polarity vh 63 .

As explained above, when the polarity inversion signal REV is at the logic level 0, the VREF amplifier AL 1 generates the amplified gradation voltage VY 63 having the voltage the same as that of the gradation reference voltage with the negative polarity VL 63 or the gradation voltage with the negative polarity vl 63 . On the other hand, when the polarity inversion signal REV is at the logic level 1, the VREF amplifier AL 1 generates the amplified gradation voltage VY 63 having the voltage the same as that of the gradation reference voltage with the positive polarity VH 63 or the gradation voltage with the positive polarity vh 63 . In other words, depending on the logic level of the polarity inversion signal REV, the VREF amplifier AL 1 alternately generates the gradation reference voltage with the positive polarity VH 63 or the gradation voltage with the positive polarity vh 63 , and the gradation reference voltage with the negative polarity VL 63 or the gradation voltage with the negative polarity vl 63 .

In the embodiment, the amplified gradation voltages VX 63 and VY 63 generated with the VREF amplifiers AH 1 and AL 1 are supplied to the selectors SH 1 and SL 1 , respectively. In the next step, out of the amplified gradation voltages VX 63 and VY 63 , when the polarity inversion signal REV is at the logic level 0, the selector SH 1 selects the amplified gradation voltage VX 63 . Further, when the polarity inversion signal REV is at the logic level 1, the selector SH 1 selects the amplified gradation voltage VY 63 . In the next step, the selector SH 1 supplies selected one of the amplified gradation voltages VX 63 and VY 63 to the positive polarity side ladder resistor RH as the positive polarity drive gradation voltage GH 63 . Accordingly, as shown in FIG. 8 , regardless of the logic level of the polarity inversion signal REV, the selector SH 1 always supplies the positive polarity drive gradation voltage GH 63 equal to the gradation reference voltage with the positive polarity VH 63 or the gradation voltage with the positive polarity vh 63 to the positive polarity side ladder resistor RH.

In the embodiment, out of the amplified gradation voltages VX 63 and VY 63 , when the polarity inversion signal REV is at the logic level 0, the selector SL 1 selects the amplified gradation voltage VY 63 . Further, when the polarity inversion signal REV is at the logic level 1, the selector SL 1 selects the amplified gradation voltage VX 63 . In the next step, the selector SL 1 supplies selected one of the amplified gradation voltages VX 63 and VY 63 to the negative polarity side ladder resistor RL as the negative polarity drive gradation voltage GL 63 . Accordingly, as shown in FIG. 8 , regardless of the logic level of the polarity inversion signal REV, the selector SL 1 always supplies the negative polarity drive gradation voltage GL 63 equal to the gradation reference voltage with the negative polarity VL 63 or the gradation voltage with the negative polarity vl 63 to the negative polarity side ladder resistor RL.

As explained above, the gradation voltage generation unit 122 includes the VREF amplifiers AH and AL. The VREF amplifier AL is provided for alternately amplifying the gradation reference voltage with the positive polarity VH and the gradation reference voltage with the negative polarity VL to obtain the amplified gradation voltage VX. The VREF amplifier AL is provided for alternately amplifying the gradation reference voltage with the negative polarity VL 63 and the gradation reference voltage with the negative polarity VL 63 at the different phase to obtain the amplified gradation voltage VX.

Further, the gradation voltage generation unit 122 includes the selectors SH and SL. The selector SH is provided for alternately selecting the outputs of the VREF amplifiers AH and AL to extract only the positive polarity gradation voltage vh or the positive polarity gradation reference voltage VH. The selector SL is provided for alternately selecting the outputs of the VREF amplifiers AH and AL to extract only the negative polarity gradation voltage vl or the negative polarity gradation reference voltage VL.

In the embodiment, as shown in FIG. 6 , the operation amplifier AMP is connected each of the VREF amplifiers AH and AL. Accordingly, the positive polarity gradation reference voltage VH and the negative polarity gradation reference voltage VL are alternately supplied to the operation amplifier AMP through the input line L 1 . As a result, it is possible to reduce an offset between the positive polarity gradation voltage vh and the negative polarity gradation voltage vl.

In the embodiment, in the VREF amplifiers AH and AL, immediately before the gradation reference voltage with the positive polarity VH is switched to the gradation reference voltage with the negative polarity VL, the input line L 1 of the operation amplifier AMP is maintained at the gradation reference voltage with the positive polarity VH. Similarly, immediately before the gradation reference voltage with the negative polarity VL is switched to the gradation reference voltage with the positive polarity VH, the input line L 1 of the operation amplifier AMP is maintained at the gradation reference voltage with the negative polarity VL.

Accordingly, when the gradation reference voltage with the positive polarity VH is switched to the gradation reference voltage with the negative polarity VL, the gradation reference voltage with the negative polarity VL is applied to the input line L 1 of the operation amplifier AMP. At this moment, the gradation reference voltage with the negative polarity VL tends to shift toward the positive side due to the gradation reference voltage with the positive polarity VH maintained in the input line L 1 just before the application. Similarly, when the gradation reference voltage with the negative polarity VL is switched to the gradation reference voltage with the positive polarity VH, the gradation reference voltage with the positive polarity VH is applied to the input line L 1 of the operation amplifier AMP. At this moment, the gradation reference voltage with the positive polarity VH tends to shift toward the negative side due to the gradation reference voltage with the negative polarity VL maintained in the input line L 1 just before the application.

As a result, when the polarity of the gradation reference voltage (VH and VL) is inverted, a temporary voltage variance is created on the input line L 1 of the operation amplifier AMP. Accordingly, the operation amplifier AMP may output the drive gradation voltage (GH and GL) having a ripple temporarily, thereby causing deterioration of an image displayed.

In order to reduce the ripple, in the embodiment, as shown in FIG. 6 , the VREF amplifiers AH and AL have the transmission gates TG 3 and TG 4 for applying the positive polarity gradation voltage vh and the negative polarity gradation voltage vl to the input line L 1 . With the configuration, it is controlled such that the transmission gates TG 1 to TG 4 are turned on or off as shown in FIG. 8 .

More specifically, when the polarity inversion signal REV is switched from the logic level 1 to the logic level 0, in the VREF amplifier AH, the transmission gates TG 1 and TG 2 are set to the on state first. At this moment, the input line L 1 is in the state maintained in the negative polarity gradation reference voltage VL, that is, the state just before the switch. In the next step, the transmission gate TG 3 is set to the on state for the specific period of time d 2 . Accordingly, the positive polarity gradation voltage vh is applied to the input line L 1 through the transmission gate TG 3 . As a result, the input line L 1 is switched from the state maintained in the negative polarity gradation reference voltage VL to the state of the positive polarity gradation voltage vh.

After the specific period of time d 2 is elapsed, the transmission gate TG 1 is set to the on state. Accordingly, the positive polarity gradation reference voltage VH is applied to the input line L 1 . In other words, after the input line L 1 is maintained in the state of the positive polarity gradation voltage vh, the positive polarity gradation reference voltage VH is applied to the input line L 1 .

In the next step, when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1, in the VREF amplifier AH, the transmission gates TG 1 and TG 2 are set to the off state first. At this moment, the input line L 1 is in the state maintained in the positive polarity gradation reference voltage VH, that is, the state just before the switch. In the next step, the transmission gate TG 4 is set to the on state for the specific period of time d 2 . Accordingly, the negative polarity gradation voltage vl is applied to the input line L 1 through the transmission gate TG 4 . As a result, the input line L 1 is switched from the state maintained in the positive polarity gradation reference voltage VH to the state of the negative polarity gradation voltage vl.

After the specific period of time d 2 is elapsed, the transmission gate TG 2 is set to the on state. Accordingly, the negative polarity gradation reference voltage VL is applied to the input line L 1 . In other words, after the input line L 1 is maintained in the state of the negative polarity gradation voltage vl, the negative polarity gradation reference voltage VL is applied to the input line L 1 .

Further, in the embodiment, when the polarity inversion signal REV is switched from the logic level 1 to the logic level 0, in the VREF amplifier AL, the transmission gates TG 1 and TG 2 are set to the off state first. At this moment, the input line L 1 is in the state maintained in the positive polarity gradation reference voltage VH, that is, the state just before the switch. In the next step, the transmission gate TG 4 is set to the on state for the specific period of time d 2 . Accordingly, the negative polarity gradation voltage vl is applied to the input line L 1 through the transmission gate TG 4 . As a result, the input line L 1 is switched from the state maintained in the positive polarity gradation reference voltage VH to the state of the negative polarity gradation voltage vl.

After the specific period of time d 2 is elapsed, the transmission gate TG 2 is set to the on state. Accordingly, the negative polarity gradation reference voltage VL is applied to the input line L 1 . In other words, after the input line L 1 is maintained in the state of the negative polarity gradation voltage vl, the negative polarity gradation reference voltage VL is applied to the input line L 1 .

In the next step, when the polarity inversion signal REV is switched from the logic level 0 to the logic level 1, in the VREF amplifier AL, the transmission gates TG 1 and TG 2 are set to the off state first. At this moment, the input line L 1 is in the state maintained in the negative polarity gradation reference voltage VL, that is, the state just before the switch. In the next step, the transmission gate TG 3 is set to the on state for the specific period of time d 2 . Accordingly, the positive polarity gradation voltage vh is applied to the input line L 1 through the transmission gate TG 3 . As a result, the input line L 1 is switched from the state maintained in the negative polarity gradation reference voltage VL to the state of the positive polarity gradation voltage vh.

After the specific period of time d 2 is elapsed, the transmission gate TG 1 is set to the on state. Accordingly, the positive polarity gradation reference voltage VH is applied to the input line L 1 . In other words, after the input line L 1 is maintained in the state of the positive polarity gradation voltage vh, the positive polarity gradation reference voltage VH is applied to the input line L 1 .

As explained above, the VREF amplifiers AH and Al stop supplying the gradation reference voltages (VH and VL) to the input line L 1 just before the polarity of the gradation reference voltages (VH and VL) to be applied to the input line L 1 is switched. During the period of time, the VREF amplifiers AH and Al supply the gradation voltages (vh and vl) generated at last to the input line L 1 . In other words, the VREF amplifiers AH and Al supply the gradation voltages (vh and vl) having the polarity the same as that of the gradation reference voltages (VH and VL) to be applied to the input line L 1 after the polarity of the gradation reference voltages (VH and VL) is switched to the input line L 1 just before the polarity of the gradation reference voltages (VH and VL) is switched.

Accordingly, it is possible to minimize the voltage variance on the input line L 1 just before the polarity of the gradation reference voltages (VH and VL) is switched and immediately after the polarity of the gradation reference voltages (VH and VL) is switched. As a result, it is possible to reduce the ripple in the waveform of the gradation voltages (vh and vl) generated at last, thereby preventing the image quality from deteriorating.

The disclosure of Japanese Patent Application No. 2010-206888, filed on Sep. 15, 2010, is incorporated in the application by reference.

While the invention has been explained with reference to the specific embodiments of the invention, the explanation is illustrative and the invention is limited only by the appended claims.