Digitally controlled oscillator

1. Field of the Invention

The invention relates to an oscillator, and more particularly to a digitally controlled oscillator.

2. Description of the Related Art

Generally, a digitally controlled oscillator (DCO) has a relatively wide tuning range in order to execute phase locked loop (PLL), voltage controlled oscillator (VCO) or other circuit digital automatic frequency calibration. In a DCO, the oscillating frequency is adjusted by controlling a plurality of digitally controlled frequency tracking units. In order to provide finer tuning resolutions and wider tuning ranges, a large number of frequency tracking units are needed for the oscillating frequency adjustment.

In a PLL, the DCO will contribute extra quantization noise as the frequency tracking units have finite tuning resolutions. In some improved circuits, the extra quantization noise can be noise shaped by a delta-sigma (4E) modulator, to meet phase noise (PN) requirements. However, the frequency tracking units may increase design complexity and reversely affect the operation frequency of the delta-sigma modulator.

Nevertheless, when the amount of frequency tracking units increases, the performance of the DCO is affected by the mismatches among the capacitors of the frequency tracking units. For example, the mismatch will degrade the phase error, the error vector magnitude (EVM) and the output RF spectrum (ORFS) performances of a direct frequency modulation transmitter using such a DCO implementing a large number of the frequency tracking units. Furthermore, a larger parasitic capacitor will narrow the total tuning range of the oscillating frequency the DCO can provide.

Accordingly, it is difficult to implement a DCO with a fine resolution.

Digitally controlled oscillators are provided. An embodiment of a digitally controlled oscillator is provided. The digitally controlled oscillator comprises: a pair of transistors cross-coupled to each other for generating an output signal; a switched capacitor array coupled to the pair of transistors, for tuning a frequency of the output signal; and a plurality of frequency tracking units coupled to the pair of transistors, for tuning the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance, and a tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.

Furthermore, another embodiment of a digitally controlled oscillator is provided. The digitally controlled oscillator comprises an amplifier with a negative resistance, having a first input terminal, a second input terminal and an output terminal for providing an output signal; and an LC circuit coupled to the first and second input terminals of the amplifier. The LC circuit comprises an inductor coupled between the first and second input terminals of the amplifier; and a plurality of frequency tracking units coupled to the inductor in parallel, each for providing a first capacitance or a second capacitance according to a control signal, so as to finely tune a frequency of the output signal. A tuning resolution of the frequency tracking unit is determined according to a difference between the first and second capacitances.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a digitally controlled oscillator according to an embodiment of the invention;

FIG. 2 shows a schematic illustrating the frequency tracking unit of FIG. 1 according to an embodiment of the invention;

FIG. 3 shows a digitally controlled oscillator according to another embodiment of the invention;

FIG. 4 shows a schematic illustrating the sub-unit of a frequency tracking unit of FIG. 3 according to an embodiment of the invention;

FIG. 5 shows a schematic illustrating the sub-unit of a frequency tracking unit of FIG. 3 according to another embodiment of the invention;

FIG. 6 shows a schematic illustrating the sub-unit frequency tracking unit of FIG. 3 according to another embodiment of the invention;

FIG. 7 shows a digitally controlled oscillator according to another embodiment of the invention; and

FIG. 8 shows a digitally controlled oscillator according to another embodiment of the invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows a digitally controlled oscillator (DCO) 100 according to an embodiment of the invention. The digitally controlled oscillator 100 comprises the transistors M 1 and M 2 , a switched capacitor array 10 , a frequency tracking array 20 , two inductors L 1 and L 2 and a resistor R. The transistors M 1 and M 2 are cross-coupled to each other. The switched capacitor array 10 is coupled to the drains of the transistors M 1 and M 2 , and the frequency tracking array 20 is coupled to the switched capacitor array 10 in parallel. The inductor L 1 is coupled between a common node N com and the drain of the transistor M 1 , and the inductor L 2 is coupled between the common node N com and the drain of the transistor M 2 . The resistor R is coupled between the common node N com and a ground GND.

In FIG. 1 , the switched capacitor array 10 comprises a plurality of switched capacitor units 30 coupled in parallel. Each switched capacitor unit 30 comprises a capacitor C 1 coupled to the drain of the transistor M 1 , a capacitor C 2 coupled to the drain of the transistor M 2 and a switch SW coupled between the capacitors C 1 and C 2 , wherein the switch SW is controlled by an individual control signal. By switching the switches SW of the switched capacitor array 10 , an output frequency of a signal S out can be tuned coarsely. The switched capacitor unit 30 is used as an example for description, and does not limit the invention. Furthermore, the frequency tracking array 20 comprises a plurality of frequency tracking units 40 coupled in parallel, which is used to finely tune the output frequency of the signal S out to a target frequency. In the frequency tracking array 20 , each frequency tracking unit 40 is controlled by an individual control signal that controls the frequency tracking unit 40 to provide a first capacitance or a second capacitance. In the embodiment, the first capacitances of the frequency tracking units 40 are the same, and the second capacitances of the frequency tracking units 40 are the same.

FIG. 2 shows a schematic illustrating the frequency tracking unit 40 of FIG. 1 according to an embodiment of the invention. The frequency tracking unit 40 comprises three capacitors C A1 , C A2 and C B , two resistors R 1 and R 2 and a switch M SW . Referring to FIG. 1 and FIG. 2 together, the capacitor C A1 is coupled between the drain of the transistor M 1 and a node N 1 , and the capacitor C A2 is coupled between the drain of the transistor M 2 and a node N 2 , wherein the capacitors C A1 and C A2 have the same capacitances. The capacitor C B is coupled between the nodes N 1 and N 2 . The resistor R 1 is coupled between the node N 1 and the ground GND, and the resistor R 2 is coupled between the node N 2 and the ground GND. The switch M SW is coupled to the capacitor C B in parallel, which is controlled by an individual control signal S ctrl . When the switch M SW is turned on by the control signal S ctrl , the frequency tracking unit 40 provides an equivalent capacitance C ON according to the capacitors C A1 and C A2 . When the switch M SW is turned off by the control signal ctrl , the frequency tracking unit 40 provides an equivalent capacitance C OFF according to the capacitors C A1 , C A2 and C B . The equivalent capacitances C ON and C OFF are obtained by the following equations:

C ON = C A 2 = C AD C OFF = C A 2 · C B C A 2 + C B = C AD · C B C AD + C B .

Therefore, a unit capacitance C step is obtained according to a difference between the capacitances C ON and C OFF , wherein C step is obtained by the following equation:

In the embodiment, the unit capacitance C step is used as a tuning resolution of the frequency tracking unit 40 for turning the output frequency of the signal S out to a target frequency. Note that the three capacitors C A1 , C A2 and C B , are passive metal capacitors which are insensitive to noise and voltage swings. Furthermore, low fixed parasitical capacitances are obtained and layout structure of the frequency tracking unit 40 is easily matched for the capacitors C A1 , C A2 and C B . For example, the mismatching of the frequency tracking unit 40 is obtained by the following equation:

Δ ⁢ ⁢ C step C step = 2 ⁢ Δ ⁢ ⁢ C AD C AD - Δ ⁢ ⁢ C B C B .

Therefore, the gain factor K DCO of the digitally controlled oscillator 100 of FIG. 1 is obtained by the following equation:

K DCO = C step 2 · C tan ⁢ ⁢ k · f DCO ,

where f DCO represents the output frequency of the signal S out , i.e.

f DCO = 1 2 ⁢ π · LC tan ⁢ ⁢ k ,

wherein C tank and L represent the tank capacitance and inductance, respectively. In one embodiment, each of the capacitors C A1 , C A2 and C B may be formed by a plurality of capacitors connected in series, parallel or combinations thereof.

FIG. 3 shows a digitally controlled oscillator 200 according to another embodiment of the invention. Compared with the digitally controlled oscillator 100 of FIG. 1 , a frequency tracking array 50 of the digitally controlled oscillator 200 comprises a plurality of frequency tracking units 60 coupled in parallel, wherein each frequency tracking unit 60 comprises a sub-unit 70 A coupled between the drain of the transistor M 1 and the ground GND and a sub-unit 70 B coupled between the drain of the transistor M 2 and the ground GND, wherein the sub-units 70 A and 70 B have the same circuit structures. Similarly, each frequency tracking unit 60 is controlled by an individual control signal, i.e. the sub-units 70 A and 70 B of the frequency tracking unit 60 are controlled by the same control signal, wherein the individual control signal controls the sub-units 70 A and 70 B to provide a first capacitance or a second capacitance simultaneously. In the embodiment, the first capacitances of the sub-units 70 A and 70 B of each frequency tracking unit 60 are the same, and the second capacitances of the sub-units 70 A and 70 B of each frequency tracking units 60 are the same.

FIG. 4 shows a schematic illustrating the sub-unit 70 A/ 70 B of FIG. 3 according to an embodiment of the invention. Referring to FIG. 3 and FIG. 4 together, a capacitor C A is coupled to the drain of a corresponding transistor. For example, the capacitor C A of the sub-unit 70 A is coupled to the drain of the transistor Ml, and the capacitor C A of the sub-unit 70 B is coupled to the drain of the transistor M 2 . Furthermore, a capacitor C B is coupled between the capacitor C A and the ground GND, and a switch M SW is coupled to the capacitor C B in parallel, wherein the switch M SW is controlled by an individual control signal S ctrl . When the switch M SW is turned on by the control signal S ctrl , the sub-unit 70 A/ 70 B provides an equivalent capacitance C ON1 according to the capacitor C A . When the switch M SW is turned off by the control signal S ctrl , the sub-unit 70 A/ 70 B provides an equivalent capacitance C OFF1 according to the capacitors C A and C B . The equivalent capacitances C ON1 and C OFF1 are obtained by the following equations:

C ON ⁢ ⁢ 1 = C A C OFF ⁢ ⁢ 1 = C A · C B C A + C B .

Therefore, a unit capacitance C step1 is obtained according to a difference between the capacitances C ON1 and C OFF1 , wherein C step1 is obtained by the following equation:

C step ⁢ ⁢ 1 = C ON ⁢ ⁢ 1 - C OFF ⁢ ⁢ 1 = C A 2 C A + C B .

In the embodiment, the unit capacitance C step1 is used as a tuning resolution of the frequency tracking unit 60 for turning the output frequency of the signal S out to a target frequency. Furthermore, the capacitors C A and C B are passive metal capacitors.

FIG. 5 shows a schematic illustrating the sub-unit 70 A/ 70 B of FIG. 3 according to another embodiment of the invention. Referring to FIG. 3 and FIG. 5 together, the capacitors C A1 and C A2 are coupled to the drain of a corresponding transistor. For example, the capacitors C A1 and C A2 of the sub-unit 70 A are coupled to the drain of the transistor M 1 , and the capacitors C A1 and C A2 of the sub-unit 70 B are coupled to the drain of the transistor M 2 . A capacitor C B1 is coupled between the capacitor C A1 and the ground GND, and a switch M SW1 is coupled to the capacitor C B1 in parallel, wherein the switch M SW1 is controlled by an individual control signal S ctrl . A capacitor C B2 is coupled between the capacitor C A2 and the ground GND, and a switch M SW2 is coupled to the capacitor C B2 in parallel, wherein the switch M SW2 is controlled by a control signal SB ctrl that is complementary to the control signal S ctrl . When the switch M SW1 is turned on by the control signal S ctrl and the switch M SW2 is turned off by the control signal SB ctrl , the sub-unit 70 A/ 70 B provides an equivalent capacitance C ON2 according to the capacitors C A1 , C A2 and C B2 . When the switch M SW1 is turned off by the control signal S cttl and the switch M SW2 is turned on by the control signal SB ctrl , the sub-unit 70 A/ 70 B provides an equivalent capacitance C OFF2 according to the capacitors C A1 , C B1 and C A2 . In the embodiment, the capacitors C A1 and C A2 have the same capacitance C A , thus the equivalent capacitances C ON2 and C OFF2 are obtained by the following equations:

C ON ⁢ ⁢ 2 = C A · C B ⁢ ⁢ 2 C A + C B ⁢ ⁢ 2 + C A C OFF ⁢ ⁢ 2 = C A · C B ⁢ ⁢ 1 C A + C B ⁢ ⁢ 1 + C A .

Therefore, a unit capacitance C step2 is obtained according to a difference between the capacitances C ON2 and C OFF2 , wherein C step2 is obtained by the following equation:

C step ⁢ ⁢ 2 = C ON ⁢ ⁢ 2 - C OFF ⁢ ⁢ 2 = C A 2 ⁡ ( C B ⁢ ⁢ 2 - C B ⁢ ⁢ 1 ) ( C A + C B ⁢ ⁢ 1 ) ⁢ ( C A + C B ⁢ ⁢ 2 ) .

In the embodiment, the unit capacitance C step2 is used as a tuning resolution of the frequency tracking unit 60 for turning the output frequency of the signal S out to a target frequency. Furthermore, the capacitors C A1 , C A2 , C B1 and C B2 are passive metal capacitors.

FIG. 6 shows a schematic illustrating the sub-unit 70 A/ 70 B of FIG. 3 according to another embodiment of the invention. Referring to FIG. 3 and FIG. 6 together, the capacitor C A is coupled to the drain of a corresponding transistor. For example, the capacitors C A of the sub-unit 70 A is coupled to the drain of the transistor M 1 , and the capacitors C A of the sub-unit 70 B is coupled to the drain of the transistor M 2 . Two capacitors C B1 and C B2 are coupled to the capacitor C. A switch M SW1 is coupled between the capacitor C B1 and the ground GND, wherein the switch M SW1 is controlled by an individual control signal S ctrl . A switch M SW2 is coupled between the capacitor C B2 and the ground GND, wherein the switch M SW2 is controlled by a control signal SB ctrl complementary to the control signal S ctrl . When the switch M SW1 is turned on by the control signal S ctrl and the switch M SW2 is turned off by the control signal SB ctrl , the sub-unit 70 A/ 70 B provides an equivalent capacitance C ON3 according to the capacitors C A and C B1 . When the switch M SW1 is turned off by the control signal S ctrl and the switch M SW2 is turned on by the control signal SB ctrl , the sub-unit 70 A/ 70 B provides an equivalent capacitance C OFF3 according to the capacitors C A and C B2 . The equivalent capacitances C ON3 and C OFF3 are obtained by the following equations:

C ON ⁢ ⁢ 3 = C A · C B ⁢ ⁢ 1 C A + C B ⁢ ⁢ 1 C OFF ⁢ ⁢ 3 = C A · C B ⁢ ⁢ 2 C A + C B ⁢ ⁢ 2 .

Therefore, a unit capacitance C step3 is obtained according to a difference between the capacitances C ON3 and C OFF3 , wherein C step3 is obtained by the following equation:

C step ⁢ ⁢ 3 = C ON ⁢ ⁢ 3 - C OFF ⁢ ⁢ 3 = C A 2 ⁡ ( C B ⁢ ⁢ 1 - C B ⁢ ⁢ 2 ) ( C A + C B ⁢ ⁢ 1 ) ⁢ ( C A + C B ⁢ ⁢ 2 ) .

In the embodiment, the unit capacitance C step3 is used as a tuning resolution of the frequency tracking unit 60 for turning the output frequency of the signal S out to a target frequency. Furthermore, the capacitors C A , C B1 and C B2 are passive metal capacitors.

FIG. 7 shows a digitally controlled oscillator 300 according to another embodiment of the invention. The digitally controlled oscillator 300 comprises an amplifier 80 with a negative resistance and an LC circuit 90 . The LC circuit 90 comprises an inductor L coupled between the input terminals In 1 and In 2 of the amplifier 80 , a switched capacitor array 10 and a frequency tracking array 20 , wherein the switched capacitor array 10 and frequency tracking array 20 are coupled to the inductor L in parallel. In one embodiment, the amplifier 80 comprises a pair of transistors cross-coupled to each other, e.g. the transistors M 1 and M 2 of FIG. 1 and FIG. 3 . As described above, the switched capacitor array 10 comprises a plurality of switched capacitor units 30 coupled in parallel. Each switched capacitor unit 30 comprises a capacitor C 1 coupled to the input terminal In 1 of the amplifier 80 , a capacitor C 2 coupled to the input terminal In 2 of the amplifier 80 and a switch SW coupled between the capacitors C 1 and C 2 , wherein the switch SW is controlled by an individual control signal. By switching the switches SW of the switched capacitor array 10 , an output frequency of a signal S out provided by the amplifier 80 can be tuned coarsely. Furthermore, the frequency tracking array 20 comprises a plurality of frequency tracking units 40 coupled between the input terminals In 1 and In 2 of the amplifier 80 , which is used to finely tune the output frequency of the signal S out to a target frequency. In the frequency tracking array 20 , each frequency tracking unit 40 is controlled by an individual control signal that controls the frequency tracking unit 40 to provide a first capacitance (e.g. C ON ) or a second capacitance (e.g. C OFF ), so as to obtain a unit capacitance (e.g. C step ) that is used as a tuning resolution for turning the output frequency of the signal S out .

FIG. 8 shows a digitally controlled oscillator 400 according to another embodiment of the invention. In the digitally controlled oscillator 400 , a frequency tracking array 50 comprises a plurality of frequency tracking units 60 coupled between the input terminals In 1 and In 2 of the amplifier 80 . As described above, each frequency tracking unit 60 comprises a sub-unit 70 A coupled between the input terminal In 1 of the amplifier 80 and the ground GND and a sub-unit 70 B coupled between the input terminal In 2 of the amplifier 80 and the ground GND, wherein the sub-units 70 A and 70 B have the same circuit structures. Similarly, each frequency tracking unit 60 is controlled by an individual control signal, i.e. the sub-units 70 A and 70 B of the frequency tracking unit 60 are controlled by the same control signal, wherein the individual control signal controls the sub-units 70 A and 70 B to provide a first capacitance (e.g. C ON1 , C ON2 and C ON3 ) or a second capacitance (e.g. C OFF1 , C OFF2 and C OFF3 ) simultaneously, so as to obtain a unit capacitance (e.g. C step1 , C step2 and C step3 ) that is used as a tuning resolution for turning the output frequency of the signal S out .

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.