Liquid crystal display panel having different sub-pixels arrangement groups

The disclosure relates to a LCD panel, and more particularly to a LCD panel integrating a gate driver on array (GOA) circuit.

A typical LCD panel comprises plural gate lines connected to a gate driver and plural data lines connected to a data driver (also referred as a source driver). For effectively reducing the number of data lines to reduce the fabricating cost, a LCD panel with a tri-gate pixel configuration has been disclosed. In the tri-gate pixel configuration, the sub-pixels R, G and B of each pixel are sequentially arranged along the data line. In such way, the number of gate drivers is tripled to constitute a complete frame. As known, a LCD panel integrating a gate driver on array (GOA) circuit may reduce the overall fabricating cost.

FIG. 1A is a schematic circuit diagram illustrating a conventional LCD panel, which is disclosed in US Patent Application No. US2007/0091044. The LCD panel has a tri-gate pixel configuration. As shown in FIG. 1A , the LCD panel comprises a data driver and a pixel array. The data driver comprises plural data driver integrated circuits 141 , which are connected with m data lines D 1 ˜Dm. The gate driver is connected with 3n gate lines G 1 ˜G 3 n. The gate driver comprises a first gate driver integrated circuit 150 L and a second gate driver integrated circuit 150 R. The gate driver integrated circuit 150 L is connected with the odd-numbered gate lines. The second gate driver integrated circuit 150 R is connected with the even-numbered gate lines.

For example, the pixel PX 11 comprises three sub-pixels, which are controlled by the gate pulses from a first gate line G 1 , a second gate line G 2 and a third gate line G 3 , respectively. For enhancing the display quality and reducing the overall power consumption of the LCD panel, the data lines are driven by a column inversion driving method. As a result, the driving polarities of every two adjacent data lines are opposite at the same time. Generally, a common voltage Vcom is received by the LCD panel. The data line having a voltage value higher than the common voltage has a positive polarity (+). The data line having a voltage value lower than the common voltage has a negative polarity (−).

The way of arranging the sub-pixels of the LCD panel of FIG. 1A , however, may incur some drawbacks during the process of displaying some regular frames. For example, when the voltages of the data lines are simultaneously changed from a low-level state to a high-level state or simultaneously changed from the high-level state to the low-level state, the common voltage Vcom may be deviated from the original level because of a coupling effect. Under this circumstance, the voltage levels for writing to the sub-pixels are adversely affected, and thus the displaying quality of the frame is usually deteriorated.

FIG. 1B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 1A when bright/dark vertical fringes are displayed. The common voltage Vcom is 4 volts. The even-numbered data lines have the negative polarity. The odd-numbered data lines have the positive polarity. If the voltage value of the data line is equal to the common voltage Vcom, the sub-pixels corresponding to the data line are in the full-bright state. Whereas, if the voltage value of the data line is equal to 0V or 8V, the sub-pixels corresponding to the data line are in the full-dark state.

Obviously, in a case that the data lines of the LCD panel are driven by a column inversion driving method to display the bright/dark vertical fringes, the voltage of the even-numbered data lines (e.g. the second data line D 2 and the fourth data line D 4 ) are alternately changed between 4V and 0V in response to the gate pulses (G 1 ˜G 12 ) of the gate lines. Similarly, the voltage of the odd-numbered data lines (e.g. the third data line D 3 and the fifth data line D 5 ) are alternately changed between 8V and 4V in response to the gate pulses (G 1 ˜G 12 ) of the gate lines. In such way, the bright/dark vertical fringes are shown on the frame.

As can be seen from FIG. 1B , when the voltages of the data lines are simultaneously changed from a low-level state to a high-level state or simultaneously changed from the high-level state to the low-level state (i.e. in the transition condition), the common voltage Vcom may be deviated from the original level because of a coupling effect. Under this circumstance, the voltage levels for writing to the sub-pixels are adversely affected, and thus the displaying quality of the frame is usually deteriorated.

Please refer to FIGS. 2A and 2B . FIG. 2A is a schematic circuit diagram illustrating a gate driver according to the prior art. FIG. 2B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver of FIG. 2A . The gate driver 410 comprises plural shift register units 411 ˜ 418 . According to four clock signals C 1 ˜C 4 , the shift register units 411 ˜ 418 generate four gate pulses g 1 ˜g 4 to the gate line G 1 ˜G 4 of the visible zone 420 , respectively. The operations of the gate driver 410 will be illustrated in more details as follows.

In response to a start signal ST, the first shift register unit 411 and the second shift register unit 412 issue the first gate pulse g 1 and the second gate pulse g 2 to the first gate line G 1 and the second gate line G 2 according to the first clock signal C 1 and the second clock signal C 2 , respectively. The third shift register unit 413 is informed by the first shift register unit 411 to issue the third gate pulse g 3 to the third second gate line G 3 according to the third clock signal C 3 . The fourth shift register unit 414 is informed by the second shift register unit 412 to issue the fourth gate pulse g 4 to the fourth gate line G 4 according to the fourth clock signal C 4 . The operations of the shift register units 415 ˜ 418 and the successive shift register units are similar to those illustrated above, and are not redundantly described herein. The four clock signals C 1 ˜C 4 have the same frequency. In addition, the phase difference between any two adjacent clock signals of the four clock signals C 1 ˜C 4 is 90 degrees.

Please refer to FIG. 2B again. Take the first gate pulse g 1 for example. The first half of the first gate pulse g 1 is a pre-charge time t 1 , and the last half of the first gate pulse g 1 is a data writing time t 2 . Similarly, each of the pulse signals includes a pre-charge time and a data writing time. By this operating method, the gate pulses outputted from every two gate lines neighboring the sub-pixel may be overlapped with each other for a data writing time t 2 . In other words, during the period of writing this data, the voltage of the sub-pixel is adversely affected by the adjacent gate line through the parasitic capacitance between the sub-pixel and the gate line. Under this circumstance, the displaying quality of the frame is deteriorated.

In accordance with an aspect, the present invention provides a LCD device. The LCD device includes plural gate lines, plural data lines, and plural basic arrangement groups. Each of the basic arrangement groups includes a first row, a second row, a third row, a fourth row, a fifth row and a sixth row. The first row includes four sub-pixels corresponding to a first color. In the first row, a switching element of the first sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the (4y+1)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+1)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the fourth sub-pixel has a control terminal connected to the first gate line (6x+1)-th, a first terminal connected to the fourth data line (4y+4)-th, and a second terminal connected to a corresponding storage unit. The second row includes four sub-pixels corresponding to a second color. In the second row, a switching element of the first sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the second data line (4y+2)-th, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+5)-th data line, and a second terminal connected to a corresponding storage unit. The third row includes four sub-pixels corresponding to a third color. In the third row, a switching element of the first sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+1)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit. The fourth row includes four sub-pixels corresponding to the first color. In the fourth row, a switching element of the first sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+5)-th data line, and a second terminal connected to a corresponding storage unit. The fifth row includes four sub-pixels corresponding to the second color. In the fourth row, a switching element of the first sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+1)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit. The sixth row includes four sub-pixels corresponding to the third color. In the sixth row, a switching element of the first sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+7)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+7)-th gate line, a first terminal connected to the (4y+5)-th data line, and a second terminal connected to a corresponding storage unit. In the above formulae, x is zero or a positive integer, and y is zero or a positive integer.

In accordance with another aspect, the present invention provides a LCD device. The LCD device includes plural gate lines, plural data lines, and plural basic arrangement groups. Each of the basic arrangement groups includes a first row, a second row, a third row, a fourth row, a fifth row and a sixth row. The first row includes four sub-pixels corresponding to a first color. In the first row, a switching element of the first sub-pixel has a control terminal connected to the (6x+1)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+1)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the fourth sub-pixel has a control terminal connected to the first gate line (6x+2)-th, a first terminal connected to the fourth data line (4y+5)-th, and a second terminal connected to a corresponding storage unit. The second row includes four sub-pixels corresponding to a second color. In the second row, a switching element of the first sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+1)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the second data line (4y+3)-th, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+2)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit. The third row includes four sub-pixels corresponding to a third color. In the third row, a switching element of the first sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+3)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+5)-th data line, and a second terminal connected to a corresponding storage unit. The fourth row includes four sub-pixels corresponding to the first color. In the fourth row, a switching element of the first sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+1)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+4)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit. The fifth row includes four sub-pixels corresponding to the second color. In the fifth row, a switching element of the first sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+2)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+5)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+5)-th data line, and a second terminal connected to a corresponding storage unit. The sixth row includes four sub-pixels corresponding to the third color. In the sixth row, a switching element of the first sub-pixel has a control terminal connected to the (6x+7)-th gate line, a first terminal connected to the (4y+1)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the second sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+3)-th data line, and a second terminal connected to a corresponding storage unit; a switching element of the third sub-pixel has a control terminal connected to the (6x+7)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit; and a switching element of the fourth sub-pixel has a control terminal connected to the (6x+6)-th gate line, a first terminal connected to the (4y+4)-th data line, and a second terminal connected to a corresponding storage unit. In the above formulae, x is zero or a positive integer, and y is zero or a positive integer.

In accordance with a further aspect, the present invention provides a LCD device. The LCD device includes a visible zone with plural gate lines, and a gate driver module. The gate driver module includes a gate driver and a wiring zone. The gate driver includes a (4z+1)-th shift register unit, a (4z+2)-th shift register unit, a (4z+3)-th shift register unit and a (4z+4)-th shift register unit. The (4z+1)-th shift register unit generates a (4z+1)-th gate pulse according to a first clock signal. The (4z+2)-th shift register unit generates a (4z+2)-th gate pulse according to a second clock signal. The (4z+3)-th shift register unit generates a (4z+3)-th gate pulse according to a third clock signal. The (4z+4)-th shift register unit generates a (4z+4)-th gate pulse according to a fourth clock signal. The wiring zone is used for transmitting the (4z+1)-th gate pulse to the (4z+3) gate line, transmitting the (4z+2)-th gate pulse to the (4z+1)-th gate line, transmitting the (4z+3)-th gate pulse to the (4z+4)-th gate line, transmitting the (4z+4)-th gate pulse to the (4z+2)-th gate line. In the above formulae, z is zero or a positive integer. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have the same frequency. The phase difference between any two adjacent clock signals of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal is 90 degrees.

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

FIG. 1A is a schematic circuit diagram illustrating a conventional LCD panel;

FIG. 1B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 1A when bright/dark vertical fringes are displayed;

FIG. 2A is a schematic circuit diagram illustrating a gate driver according to the prior art;

FIG. 2B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver of FIG. 2A ;

FIG. 3A is a schematic circuit diagram illustrating a conventional LCD panel according to a first embodiment of the present invention;

FIG. 3B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 3A when bright/dark vertical fringes are displayed;

FIG. 4A is a schematic circuit diagram illustrating a conventional LCD panel according to a second embodiment of the present invention;

FIG. 4B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 4A when bright/dark vertical fringes are displayed;

FIG. 5A is a schematic circuit diagram illustrating a gate driver module according to an embodiment of the present invention;

FIG. 5B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver module of FIG. 5A ;

FIG. 6A is a schematic circuit diagram illustrating a gate driver module according to another embodiment of the present invention; and

FIG. 6B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver module of FIG. 6A .

The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

FIG. 3A is a schematic circuit diagram illustrating a conventional LCD panel according to a first embodiment of the present invention. The LCD panel has a tri-gate pixel configuration. As shown in FIG. 3A , the LCD panel comprises a data driver 520 , a gate driver module 510 and a pixel array. The data driver 520 are connected with m data lines D 1 ˜Dm. The gate driver 510 is connected with 3n gate lines G 1 ˜G 3 n.

The data lines are driven by a column inversion driving method. As a result, the driving polarities of every two adjacent data lines are opposite at the same time. For example, the first data line has a positive polarity, the second data line has a negative polarity, and the rest may be deduced by analogy. A common voltage Vcom is received by the LCD panel. The data line having a voltage value higher than the common voltage has a positive polarity (+). The data line having a voltage value lower than the common voltage has a negative polarity (−).

The pixel array of the LCD panel comprises plural sub-pixels. The sub-pixels are divided into plural basic arrangement groups. In the pixel array of the first embodiment, each basic arrangement group includes 6-by-4 sub-pixels. That is, each basic arrangement group is defined by six gate lines and four data lines. For example, as shown in FIG. 3A , the basic arrangement group 530 is connected with the gate lines G 1 ˜G 7 and the data lines D 1 ˜D 5 .

A first row of the basic arrangement group 530 comprises four red sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the first data line D 1 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the first gate line G 1 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the first gate line G 1 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit.

A second row of the basic arrangement group 530 comprises four green sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the fifth data line D 5 , and a second terminal connected to a corresponding storage unit.

A third row of the basic arrangement group 530 comprises four blue sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the first data line D 1 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit.

A fourth row of the basic arrangement group 530 comprises four red sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the fifth data line D 5 , and a second terminal connected to a corresponding storage unit.

A fifth row of the basic arrangement group 530 comprises four green sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the first data line D 1 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit.

A sixth row of the basic arrangement group 530 comprises four blue sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the seventh gate line G 7 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the seventh gate line G 7 , a first terminal connected to the fifth data line D 5 , and a second terminal connected to a corresponding storage unit.

The basic arrangement group 530 is defined by the gate lines G 1 ˜G 7 and the data lines D 1 ˜D 5 . Nevertheless, each basic arrangement group of the pixel array may be defined by the (6x+1)-th gate line to the (6x+7)-th gate line and the (4y+1)-th data line to the (4y+5)-th data line, where x is zero or a positive integer, and y is zero or a positive integer.

In a case that x=y=0, the basic arrangement group 530 is defined by the gate lines G 1 ˜G 7 and the data lines D 1 ˜D 5 . In a case that x=1 and y=0, the basic arrangement group is defined by the gate lines G 7 ˜G 13 and the data lines D 1 ˜D 5 .

During the process of displaying regular frames, the way of arranging the sub-pixels of the LCD panel of FIG. 3A can obviate the drawbacks encountered from the prior art. Since the voltages of the adjacent data lines are no longer simultaneously changed from a low-level state to a high-level state or simultaneously changed from the high-level state to the low-level state, the common voltage Vcom will not be deviated from the original level because of a coupling effect. Under this circumstance, the frame can be normally displayed.

FIG. 3B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 3A when bright/dark vertical fringes are displayed. The common voltage Vcom is 4 volts. The even-numbered data lines have the negative polarity. The odd-numbered data lines have the positive polarity. If the voltage value of the data line is equal to the common voltage Vcom, the sub-pixels corresponding to the data line are in the full-bright state. Whereas, if the voltage value of the data line is equal to 0V or 8V, the sub-pixels corresponding to the data line are in the full-dark state.

Obviously, in a case that the data lines of the LCD panel are driven by a column inversion driving method to display the bright/dark vertical fringes, the voltage of the even-numbered data lines (e.g. the second data line D 2 and the fourth data line D 4 ) are alternately changed between 4V and 0V in response to the gate pulses (G 1 ˜G 12 ) of the gate lines. Similarly, the voltage of the odd-numbered data lines (e.g. the third data line D 3 and the fifth data line D 5 ) are alternately changed between 8V and 4V in response to the gate pulses (G 1 ˜G 12 ) of the gate lines. In such way, the bright/dark vertical fringes are shown on the frame.

As can be seen from FIG. 3B , when the voltages of the even-numbered data lines are changed from a low-level state to a high-level state, the voltages of the odd-numbered data lines are changed from the high-level state to the low-level state. Whereas, when the voltages of the even-numbered data lines are changed from the high-level state to the low-level state, the voltages of the odd-numbered data lines are changed from the low-level state to the high-level state. As a result, the common voltage Vcom will not be deviated from the original level because of a coupling effect. Under this circumstance, the frame can be normally displayed.

FIG. 4A is a schematic circuit diagram illustrating a conventional LCD panel according to a second embodiment of the present invention. The LCD panel has a tri-gate pixel configuration. As shown in FIG. 4A , the LCD panel comprises a data driver 620 , a gate driver module 610 and a pixel array. The data driver 620 are connected with m data lines D 1 ˜Dm. The gate driver 610 is connected with 3n gate lines G 1 ˜G 3 n.

The data lines are driven by a column inversion driving method. As a result, the driving polarities of every two adjacent data lines are opposite at the same time. For example, the first data line has a positive polarity, the second data line has a negative polarity, and the rest may be deduced by analogy. A common voltage Vcom is received by the LCD panel. The data line having a voltage value higher than the common voltage has a positive polarity (+). The data line having a voltage value lower than the common voltage has a negative polarity (−).

In the pixel array of the second embodiment, each basic arrangement group includes 6-by-4 sub-pixels. That is, each basic arrangement group is defined by six gate lines and four data lines. For example, as shown in FIG. 4A , the basic arrangement group 630 is connected with the gate lines G 1 ˜G 7 and the data lines D 1 ˜D 5 .

A first row of the basic arrangement group 630 comprises four red sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the first gate line G 1 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the first gate line G 1 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the fifth data line D 5 , and a second terminal connected to a corresponding storage unit.

A second row of the basic arrangement group 630 comprises four green sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the first data line D 1 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the second gate line G 2 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit.

A third row of the basic arrangement group 630 comprises four blue sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the third gate line G 3 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the fifth data line D 5 , and a second terminal connected to a corresponding storage unit.

A fourth row of the basic arrangement group 630 comprises four red sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the first data line D 1 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the fourth gate line G 4 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit.

A fifth row of the basic arrangement group 630 comprises four green sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the second data line D 2 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the fifth gate line G 5 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the fifth data line D 5 , and a second terminal connected to a corresponding storage unit.

A sixth row of the basic arrangement group 630 comprises four blue sub-pixels. The switching element of the first sub-pixel has a control terminal connected to the seventh gate line G 7 , a first terminal connected to the first data line D 1 , and a second terminal connected to a corresponding storage unit. The switching element of the second sub-pixel has a control terminal connected to the sixth gate line G 6 , a first terminal connected to the third data line D 3 , and a second terminal connected to a corresponding storage unit. The switching element of the third sub-pixel has a control terminal connected to the seventh gate line G 7 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit. The switching element of the fourth sub-pixel has a control terminal connected to the sixth gate line G 4 , a first terminal connected to the fourth data line D 4 , and a second terminal connected to a corresponding storage unit.

The basic arrangement group 630 is defined by the gate lines G 1 ˜G 7 and the data lines D 1 ˜D 5 . Nevertheless, each basic arrangement group of the pixel array may be defined by the (6x+1)-th gate line to the (6x+7)-th gate line and the (4y+1)-th data line to the (4y+5)-th data line, where x is zero or a positive integer, and y is zero or a positive integer.

In a case that x=y=0, the basic arrangement group 530 is defined by the gate lines G 1 ˜G 7 and the data lines D 1 ˜D 5 . In a case that x=1 and y=0, the basic arrangement group is defined by the gate lines G 7 ˜G 13 and the data lines D 1 ˜D 5 .

During the process of displaying regular frames, the way of arranging the sub-pixels of the LCD panel of FIG. 4A can obviate the drawbacks encountered from the prior art. Since the voltages of the adjacent data lines are no longer simultaneously changed from a low-level state to a high-level state or simultaneously changed from the high-level state to the low-level state, the common voltage Vcom will not be deviated from the original level because of a coupling effect. Under this circumstance, the frame can be normally displayed.

FIG. 4B is a schematic timing waveform diagram illustrating the signal change of the LCD panel of FIG. 4A when bright/dark vertical fringes are displayed. The common voltage Vcom is 4 volts. The even-numbered data lines have the negative polarity. The odd-numbered data lines have the positive polarity. If the voltage value of the data line is equal to the common voltage Vcom, the sub-pixels corresponding to the data line are in the full-bright state. Whereas, if the voltage value of the data line is equal to 0V or 8V, the sub-pixels corresponding to the data line are in the full-dark state.

Obviously, in a case that the data lines of the LCD panel are driven by a column inversion driving method to display the bright/dark vertical fringes, the voltage of the even-numbered data lines (e.g. the second data line D 2 and the fourth data line D 4 ) are alternately changed between 4V and 0V in response to the gate pulses (G 1 ˜G 12 ) of the gate lines. Similarly, the voltage of the odd-numbered data lines (e.g. the third data line D 3 and the fifth data line D 5 ) are alternately changed between 8V and 4V in response to the gate pulses (G 1 ˜G 12 ) of the gate lines. In such way, the bright/dark vertical fringes are shown on the frame.

As can be seen from FIG. 4B , when the voltages of the even-numbered data lines are changed from a low-level state to a high-level state, the voltages of the odd-numbered data lines are changed from the high-level state to the low-level state. Whereas, when the voltages of the even-numbered data lines are changed from the high-level state to the low-level state, the voltages of the odd-numbered data lines are changed from the low-level state to the high-level state. As a result, the common voltage Vcom will not be deviated from the original level because of a coupling effect. Under this circumstance, the frame can be normally displayed.

In accordance with the present invention, the gate driver module is specially designed to enhance the displaying quality of the LCD by cross-connecting the layout traces of the wiring zone in a specified manner. By means of the gate driver module, every two adjacent gate lines of the visible zone are no longer overlapped with each other. Since the voltage of the sub-pixel is not adversely affected by the adjacent gate lines, the displaying quality of the frame is enhanced.

Please refer to FIGS. 5A and 5B . FIG. 5A is a schematic circuit diagram illustrating a gate driver module according to an embodiment of the present invention. FIG. 5B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver module of FIG. 5A . The gate driver module 710 comprises a gate driver 720 and a wiring zone 730 . The gate driver 720 comprises plural shift register units 721 ˜ 728 . According to four clock signals C 1 ˜C 4 , the shift register units 721 ˜ 724 generate four gate pulses g 1 ˜g 4 , respectively. The visible zone 740 includes plural gate lines G 1 ˜G 8 . Through the wiring zone 730 , the first gate pulse g 1 is transmitted to the third gate line G 3 , the second gate pulse g 2 is transmitted to the first gate line G 1 , the third gate pulse g 3 is transmitted to the fourth gate line G 4 , and the fourth gate pulse g 4 is transmitted to the second gate line G 2 . The wiring relationships between the shift register units 725 ˜ 728 are similar to the wiring relationships between the shift register units 721 ˜ 724 , and are not redundantly described herein.

In response to a start signal ST, the first shift register unit 721 and the second shift register unit 722 issue the first gate pulse g 1 and the second gate pulse g 2 to the third gate line G 3 and the first gate line G 1 according to the first clock signal C 1 and the second clock signal C 2 , respectively. The third shift register unit 723 is informed by the first shift register unit 721 to issue the third gate pulse g 3 to the fourth gate line G 4 according to the third clock signal C 3 . The fourth shift register unit 724 is informed by the second shift register unit 722 to issue the fourth gate pulse g 4 to the second gate line G 2 according to the fourth clock signal C 4 . The four clock signals C 1 ˜C 4 have the same frequency. In addition, the phase difference between any two adjacent clock signals of the four clock signals C 1 ˜C 4 is 90 degrees.

Please refer to FIG. 5B again. After being processed by the wiring zone 730 , the second gate pulse g 2 on the first gate line G 1 and the fourth gate pulse g 4 on the second gate line G 2 are not overlapped with each other. Similarly, the first gate pulse g 1 on the third clock signal C 3 and the third gate pulse g 3 on the fourth gate line G 4 are not overlapped with each other. In such way, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

In other word, the gate driver 720 comprises a (4z+1)-th shift register unit, a (4z+2)-th shift register unit, a (4z+3)-th shift register unit and a (4z+4)-th shift register unit. According to a first clock signal, the (4z+1)-th shift register unit generates a (4z+1)-th gate pulse. According to a second clock signal, the (4z+2)-th shift register unit generates a (4z+2)-th gate pulse. According to a third clock signal, the (4z+3)-th shift register unit generates a (4z+3)-th gate pulse. According to a fourth clock signal, the (4z+4)-th shift register unit generates a (4z+4)-th gate pulse. By the wiring zone, the (4z+1)-th gate pulse is transmitted to a (4z+3)-th gate line, the (4z+2)-th gate pulse is transmitted to a (4z+1)-th gate line, the (4z+3)-th gate pulse is transmitted to a (4z+4)-th gate line, and the (4z+4)-th gate pulse is transmitted to a (4z+2)-th gate line. In the above formulae, z is zero or a positive integer.

Please refer to FIGS. 6A and 6B . FIG. 6A is a schematic circuit diagram illustrating a gate driver module according to another embodiment of the present invention. FIG. 6B is a schematic timing waveform diagram illustrating associated signals processed by the gate driver module of FIG. 6A . The gate driver module 810 comprises a gate driver 820 and a wiring zone 830 . The gate driver 820 comprises plural shift register units 821 ˜ 828 . According to four clock signals C 1 ˜C 4 , the shift register units 821 ˜ 824 generate four gate pulses g 1 ˜g 4 , respectively. The visible zone 840 includes plural gate lines G 1 ˜G 8 . Through the wiring zone 830 , the first gate pulse g 1 is transmitted to the third gate line G 3 , the second gate pulse g 2 is transmitted to the first gate line G 1 , the third gate pulse g 3 is transmitted to the fourth gate line G 4 , and the fourth gate pulse g 4 is transmitted to the second gate line G 2 . The wiring relationships between the shift register units 825 ˜ 828 are similar to the wiring relationships between the shift register units 821 ˜ 824 , and are not redundantly described herein.

In response to a start signal ST, the first shift register unit 821 and the second shift register unit 822 issue the first gate pulse g 1 and the second gate pulse g 2 to the third gate line G 3 and the first gate line G 1 according to the first clock signal C 1 and the second clock signal C 2 , respectively. The third shift register unit 823 is informed by the first shift register unit 821 to issue the third gate pulse g 3 to the fourth gate line G 4 according to the third clock signal C 3 . The fourth shift register unit 824 is informed by the second shift register unit 822 to issue the fourth gate pulse g 4 to the second gate line G 2 according to the fourth clock signal C 4 . The four clock signals C 1 ˜C 4 have the same frequency. In addition, the phase difference between any two adjacent clock signals of the four clock signals C 1 ˜C 4 is 90 degrees.

Please refer to FIG. 6B again. After being processed by the wiring zone 830 , the second gate pulse g 2 on the first gate line G 1 and the fourth gate pulse g 4 on the second gate line G 2 are not overlapped with each other. Similarly, the first gate pulse g 1 on the third clock signal C 3 and the third gate pulse g 3 on the fourth gate line G 4 are not overlapped with each other. In such way, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

From the above description, the present invention provides a LCD panel with an improved pixel array configuration for using a column inversion driving method to drive the data lines and achieving a stable common voltage Vcom. Moreover, by cross-connecting the layout traces of the wiring zone in a specified manner, the gate pulses outputted from every two gate lines neighboring the sub-pixel are not overlapped with each other, so that the frame can be normally displayed.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.