Semiconductor memory device and method of operating the same

Priority to Korean patent application number 10-2010-0122910 filed on Dec. 3, 2010, the entire disclosure of which is incorporated by reference herein, is claimed.

Exemplary embodiments relate to a semiconductor memory device and a method of operating the same.

As semiconductor technology advances, the operating speed of a semiconductor memory device increases and power consumption thereof decreases.

In increasing the data I/O rate of the semiconductor memory device, data is outputted in synchronism with a reference clock signal and, particularly, with both the rising edge and the falling edge of a clock signal.

In obtaining appropriate system performance, the semiconductor memory device may be designed to output or receive 16, 32, or 64 data at one step. In order to output the plurality of data at one step, appropriate data lines and related circuits (e.g., data output buffers) corresponding to the respective output data amount are to be included in the semiconductor memory device.

If the number of data lines is increased in order to output a large amount of data at one step, the area of the semiconductor memory device may increase. Accordingly, an increase in the number of data lines is to be limited.

Exemplary embodiments relate to a semiconductor memory device and a method of operating the same, which are capable of increasing the amount of data, outputted at once, and the output speed by increasing the loading size of data to be outputted without increasing the number of data lines.

A semiconductor memory device according to an aspect of the present disclosure includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, a multiplexer configured to receive the first and second data in response to third and fourth control signals and alternately output the first and second data in response to a data output signal, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.

A method of operating a semiconductor memory device according to another aspect of the present disclosure includes storing a plurality of data read from selected memory cells in page buffers, storing a first data group of the data in a first register and storing a second data group of the data in a second register group, outputting the first data group stored in the first register group and outputting the second data group stored in the second register group and storing a third data group of the data in the first register group during outputting the second data group.

FIG. 1 shows a semiconductor memory device for illustrating this disclosure;

FIG. 2 is a diagram illustrating a page buffer group, a data I/O circuit, and an I/O pad unit in FIG. 1 ;

FIG. 3A is a timing diagram illustrating a common data output process;

FIG. 3B is a timing diagram illustrating a data output according to an exemplary embodiment of this disclosure;

FIG. 4 is a diagram showing the data output circuit of the data I/O circuit according to an exemplary embodiment of this disclosure;

FIG. 5A is a diagram showing a logic group;

FIG. 5B is a diagram showing the input control unit of a logic group of FIG. 5A ;

FIG. 5C is a diagram showing the output control unit of a logic group of FIG. 5A ;

FIG. 6 is a timing diagram illustrating an operation of reading data in advance;

FIG. 7 is an operational timing diagram illustrating the output of a control signal in FIGS. 5A to 5C ; and

FIG. 8 is a timing diagram illustrating a data output according to an exemplary embodiment of this disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to enable a person of ordinary skill in the art to make and use the exemplary embodiments of the disclosure.

FIG. 1 shows a semiconductor memory device for illustrating this disclosure.

Referring to FIG. 1 , the semiconductor memory device 100 includes a memory cell array 110 , a page buffer group 120 , a data I/O circuit 130 , an I/O pad unit 140 , a peripheral circuit 150 , and a logic group 160 .

The memory cell array 110 includes memory cells for storing data. The memory cells are coupled to word lines (not shown) and bit lines BL. The memory cell array 110 includes first and second banks B 0 and B 1 .

The memory cells can be selected by selecting a word line and a bit line BL.

The page buffer group 120 includes a plurality of page buffers. Each of the page buffers is coupled to at least one bit line and is configured to temporarily store data to be stored in selected memory cells or to read data stored in selected memory cells and store the read data.

The data I/O circuit 130 is operated to perform data I/O between the page buffer group 120 and the I/O pad unit 140 . The data I/O circuit 130 includes a sense circuit SA (not shown) for sensing data outputted from the page buffer group 120 and transferring the sensed data to the I/O pad unit 140 .

The I/O pad unit 140 includes pads PAD coupled to input/output data from/to outside the semiconductor memory device 100 .

The peripheral circuit 150 includes circuits that interact with the page buffer group 120 when data is read from the memory cells or data is stored in the memory cells.

The logic group 160 generates control signals for controlling the operations of the page buffer group 120 , the data I/O circuit 130 , the I/O pad unit 140 , and the peripheral circuit 150 .

The page buffer group 120 , the data I/O circuit 130 , and the I/O pad unit 140 are described as follows.

FIG. 2 is a diagram illustrating the page buffer group, the data I/O circuit, and the I/O pad unit in FIG. 1 .

Referring to FIG. 2 , the page buffer group 120 is coupled to the data I/O circuit 130 through data I/O lines B 0 < 7 : 0 >, BO< 15 : 8 >, B 1 < 7 : 0 >, and B 1 < 15 : 8 >. The data I/O circuit 130 includes sense circuits (hereinafter referred to as IOSAs) 131 for sensing data outputted through the data I/O lines B 0 < 7 : 0 >, BO< 15 : 8 >, B 1 < 7 : 0 >, and B 1 < 15 : 8 >, storage units 132 , and multiplexers 133 .

The IOSAs 131 output the sensed data in response to control signals IO_DOSTB_B 0 and IO_DOSTB_B 1 generated by the logic group 160 . The data outputted from the IOSAs 131 are stored in the storage units 132 .

Here, the storage units 132 store the data received from the IOSAs 131 in response to control signals generated by the logic group 160 and outputs the stored data to the multiplexers 133 .

The multiplexers 133 are coupled between the storage units 132 and the pads 141 of the I/O pad unit 140 . The data outputted from the multiplexers 133 is outputted to global lines GDL_B 0 _< 7 : 0 >, GDL_BO< 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 >. The global lines GDL 1' BO_< 7 : 0 >, GDL_BO< 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > are coupled to the I/O lines IO< 7 : 0 >. The multiplexers 133 transfer data selected according to a bank, from among the data outputted from the storage units 132 , to the I/O lines IO< 7 : 0 > through the global lines GDL_B 0 _< 7 : 0 >, GDL_BO< 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 >. The data is transferred to the pads 141 through the I/O lines IO< 7 : 0 >. The transferred data is externally outputted through the pads 141 . Here, the data is outputted from the pads 141 in response to a control signal RENPAD which is generated by an external controller (not shown) coupled to the logic group 160 or the semiconductor memory device 100 .

FIG. 3A is a timing diagram illustrating a common data output process.

In FIG. 3A , data is transferred to the I/O pad unit 140 through the global lines GDL_B 0 _< 7 : 0 >, GDL_BO< 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > for externally outputting data outputted to a common data I/O line.

Referring to FIG. 3A , data is transferred to the IOSAs 131 in FIG. 2 through the data I/O lines B 0 < 7 : 0 >, B 0 < 15 : 8 >, B 1 < 7 : 0 >, and B 1 < 15 : 8 > and is then loaded on the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > in response to the control signals IO_DOSTB_B 0 and IO_DOSTB_B 1 . The data loaded on the respective data lines is D 0 to D 3 .

After the data is loaded on the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 >, the control signal RENPAD is enabled. The control signal RENPAD is transferred from the logic group 160 or the external controller (not shown) to the I/O pad unit 140 , where the control signal RENPAD is a control signal for data output.

The data loaded on the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > is outputted to the I/O pad unit 140 in response to the control signal RENPAD.

In order to reduce the time that it takes to output data from the semiconductor memory device 100 , the data is loaded on the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > in advance before the data is externally outputted. To this end, each of the storage units 132 has a register. In further increasing the data output speed, next data (that is, fifth data) loaded on the four global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > may not be output at a desired time.

To address such a feature, in an exemplary embodiment of this disclosure, an appropriate storage means such as a pipe latch circuit may be used for the data output, and the number of data loaded in advance is increased in order to increase the output speed.

FIG. 3B is a timing diagram illustrating the data output according to an exemplary embodiment of this disclosure.

Referring to FIG. 3B , the control signals IO_DOSTB_B 0 and IO_DOSTB_B 1 are inputted twice in advance before data is outputted. That is, the data loading operations are first performed twice, and an operation of outputting the data is then performed.

Details of the data I/O circuit 130 are described as follows.

FIG. 4 is a diagram showing details of the data output circuit of the data I/O circuit 130 according to an exemplary embodiment of this disclosure. It is to be noted that FIG. 4 shows portions of the I/O circuit 130 coupled between a data I/O line B 0 < 0 > and a global line GDL_B 0 < 0 >.

Referring to FIG. 4 , the data I/O circuit 130 according to the exemplary embodiment of this disclosure includes the IOSA 131 , the storage unit 132 , and the multiplexer 133 .

Details of the control signal IO_DOSTB_B 0 for controlling the data I/O circuit 130 and the logic group 160 are described later.

The IOSA 131 is enabled in response to the control signal IO_DOSTB_B 0 and configured to sense data outputted from, for example, the data I/O line B 0 < 0 > and output the sensed data.

The data outputted from the IOSA 131 is sent to the storage unit 132 . The storage unit 132 includes first to fourth switches S 1 to S 4 and first and second registers 421 and 422 for temporarily storing the data outputted from the IOSA 131 .

The first and third switches S 1 and S 3 each provide a path so that the data of the IOSA 131 is inputted to the first and the second registers 421 and 422 . The second and fourth switches S 2 and S 4 each provide a path so that the data inputted to the first and second registers 421 and 422 is outputted to the multiplexer 133 . According to an example, while data is outputted from one register, new data is input into the other register.

First and second input switching signals PINB_BO< 0 > and PINB_BO< 1 > and first and second output switching signals POUTB_B 0 < 0 > and POUTB_B 0 < 1 > for operating the first to fourth switches S 1 to S 4 are generated by the logic group 160 .

The multiplexer 133 outputs the data of the first and second registers 421 and 422 to the global line GDL_B 0 < 0 > in response to a control signal SEL_B 0 _SYNCF generated by the logic group 160 .

According to an example, the multiplexer 133 outputs the data, received from the first and the second registers 421 and 422 , in response to enabling of the control signal SEL_B 0 _SYNCF rather than selectively output the data. For example, the multiplexer 133 may output the received data to the output stage like a D flip-flop.

Details of the logic group 160 for outputting the control signals to control the operation of the data I/O circuit 130 are described as follows.

FIG. 5A is a diagram showing the logic group 160 , FIG. 5B is a diagram showing the input control unit of the logic group 160 of FIG. 5A , and FIG. 5C is a diagram showing the output control unit of the logic group 160 of FIG. 5A .

Referring to FIG. 5A , the logic group 160 includes a control logic 510 , an input control unit 520 , and an output control unit 530 .

The control logic 510 generates a control signal for controlling operations of the semiconductor memory device 100 .

For example, the control logic 510 generates the control signals IO_DOSTB_B 0 and IO_DOSTB_B 1 for controlling the operation of the IOSA 131 of the data I/O circuit 130 .

The control logic 510 further generates addresses AX_B 0 < 2 >, AX_B 1 < 2 >, and AX< 2 : 1 >, based on addresses received through the I/O pad unit 140 , a clock signal CK 4 CNT, and first and second bank selection signals SEL_B 0 and SEL_B 1 .

The input control unit 520 generates the first to fourth input switching signals PINB_BO< 0 >, PINB_B 0 < 1 >, PINB_B 1 < 0 >, and PINB_B 1 < 1 > to be inputted to the storage unit 132 of the data I/O circuit 130 , based on the addresses AX_B 0 < 2 > and AX_B 1 < 2 > and the control signals IO_DOSTB_B 0 and IO_DOSTB_B 1 .

The output control unit 530 generates the first to fourth output switching signals POUTB_B 0 < 0 >, POUTB_B 0 < 1 >, POUTB_B 1 < 0 >, and POUTB_B 1 < 1 > and the control signals SEL_B 0 _SYNCF and SEL_B 1 _SYNCF, based on the address AX< 2 : 1 >, the first and the second bank selection signals SEL_B 0 and SEL_B 1 , and the clock signal CK 4 CNT.

Referring to FIG. 5B , the input control unit 520 includes first to fourth input control circuits 521 to 524 for generating the first to fourth input switching signals PINB_B 0 < 0 >, PINB_B 0 < 1 >, PINB_B 1 < 0 >, and PINB_B 1 < 1 >.

The first and second input control circuits 521 and 522 generate the first and second input switching signals PINB_B 0 < 0 > and PINB_B 0 < 1 >, respectively, for storing data, received from the first bank B 0 , in the storage unit 132 .

The third and the fourth input control circuits 523 and 524 generate the third and the fourth input switching signals PINB_B 1 < 0 > and PINB_B 1 < 1 >, respectively, for storing data, received from the second bank B 1 , in the storage unit 132 .

The first input control circuit 521 includes a first inverter IN 1 , a first NAND gate NA 1 , and a first delay unit 521 a.

The first inverter IN 1 inverts the address AX_B 0 < 2 > and outputs an inverted address. The address AX_B 0 < 2 > is included in the column address of the first bank B 0 .

The first NAND gate NA 1 performs a NAND combination of the control signal IO_DOSTB_B 0 and the output of the first inverter IN 1 and outputs a result of the combination. The first delay unit 521 a delays the output of the first NAND gate NA 1 and outputs a delayed output. The output of the first delay unit 521 a is the first input switching signal PINB_B 0 < 0 >.

The second input control circuits 522 includes a second NAND gate NA 2 and a second delay unit 522 a . The second NAND gate NA 2 performs a NAND combination of the address AX_B 0 < 2 > and the control signal IO_DOSTB_B 0 and outputs a result of the combination.

The output of the second NAND gate NA 2 is inputted to the second delay unit 522 a . The second delay unit 522 a delays the output of the second NAND gate NA 2 and outputs a delayed output. The output of the second delay unit 522 a is the second input switching signal PINB_B 0 < 1 >.

The third input control circuits 523 includes a second inverter IN 2 , a third NAND gate NA 3 , and a third delay unit 523 a.

The second inverter IN 2 inverts the address AX_B 1 < 2 > and outputs a delayed address. The address AX_B 1 < 2 > is included in the column address of the second bank B 1 .

The third NAND gate NA 3 performs a NAND combination of the control signal IO_DOSTB_B 1 and the output of the second inverter IN 2 and outputs a result of the combination. The output of the third NAND gate NA 3 is inputted to the third delay unit 523 a.

The third delay unit 523 a delays the output of the third NAND gate NA 3 and outputs a delayed output. The output of the third delay unit 523 a is the third input switching signal PINB_B 1 < 0 >.

The fourth input control circuits 524 includes a fourth NAND gate NA 4 and a fourth delay unit 524 a.

The fourth NAND gate NA 4 performs a NAND combination of the control signal IO_DOSTB_B 1 and the address AX_B 0 < 2 > and outputs a result of the combination. The output of the fourth NAND gate NA 4 is inputted to the fourth delay unit 524 a . The fourth delay unit 524 a delays the output of the fourth NAND gate NA 4 and outputs a delayed output. The output of the fourth delay unit 524 a is the fourth input switching signal PINB_B 1 < 1 >.

The data received from the IOSA 131 is stored in the first and the second registers 421 and 422 of the storage unit 132 in response to the first to the fourth input switching signals PINB_B 0 < 0 >, PINB_B 0 < 1 >, PINB_B 1 < 0 >, and PINB_B 1 < 1 > generated by the first to fourth input control circuits 521 to 524 , respectively.

Details of the output control unit 530 are described as follows.

Referring to FIG. 5C , the output control unit 530 includes first and second output control circuits 531 and 532 .

The first output control circuit 531 generates the first and the second output switching signals POUTB_B 0 < 0 > and POUTB_B 0 < 1 > and the control signal SEL_B 0 _SYNCF. The second output control circuit 532 generates the third and the fourth output switching signals POUTB_B 1 <O> and POUTB_B 1 < 1 > and the control signal SEL_B 1 _SYNCF.

The first output control circuit 531 includes third to seventh inverters IN 3 to IN 7 , first and second AND gates AN 1 and AN 2 , first to fourth D flip-flops DFF 1 to DFF 4 , and a fifth NAND gate NA 5 .

The third inverter IN 3 inverts the address AX< 1 > and outputs an inverted output. The fourth inverter IN 4 inverts the address AX< 2 > and outputs an inverted output.

The outputs of the third and the fourth inverters IN 3 and IN 4 are inputted to the first AND gate AN 1 . The output of the first AND gate AN 1 is inputted to the first D flip-flop DFF 1 . A D flip-flop outputs received data in response to a clock signal (for example, CK 4 CNT in FIG. 5C ). Accordingly, the first D flip-flop DFF 1 transfers the output of the first AND gate AN 1 to the second D flip-flop DFF 2 in response to the clock signal CK 4 CNT.

The second D flip-flop DFF 2 outputs the data, received from the first D flip-flop DFF 1 , in response to the clock signal CK 4 CNT.

The output of the second D flip-flop DFF 2 is sent to the fifth inverter IN 5 . The fifth inverter IN 5 inverts the output of the second D flip-flop DFF 2 and outputs an inverted output.

The output of the fifth inverter IN 5 is the first output switching signal POUTB_B 0 < 0 >.

The sixth inverter IN 6 inverts the address AX< 1 > and outputs an inverted output. The addresses AX< 2 : 1 > correspond to the external addresses of a bank.

The second AND gate AN 2 performs an AND combination of the address AX< 2 > and the output of the sixth inverter IN 6 and outputs a result of the AND operation. The output of the second AND gate AN 2 is inputted to the third D flip-flop DFF 3 . The output of the third D flip-flop DFF 3 is inputted to the fourth D flip-flop DFF 4 . The output of the fourth D flip-flop DFF 4 is inputted to the seventh inverter IN 7 .

The third and fourth D flip-flops DFF 3 and DFF 4 output the input data in response to the clock signal CK 4 CNT.

The seventh inverter IN 7 inverts the output of the fourth D flip-flop DFF 4 and outputs an inverted output. The output of the seventh inverter IN 7 is the second output switching signal POUTB_B 0 < 1 >.

The first and second output switching signals POUTB_B 0 < 0 > and BOUTB_B 0 < 1 > are inputted to the fifth NAND gate NA 5 . The output of the fifth NAND gate NA 5 is the control signal SEL_B 0 _SYNCF.

The second output control circuit 532 includes eighth to tenth inverters IN 8 to IN 10 , third and fourth AND gates AN 3 and AN 4 , fifth to eighth D flip-flops DFF 5 to DFF 8 , and a sixth NAND gate NA 6 .

The eighth inverter IN 8 inverts the address AX< 2 > and outputs an inverted output.

The third AND gate AN 3 performs an AND combination of the address AX< 1 > and the output of the eighth inverter IN 8 and outputs a result of the AND operation. The output of the third AND gate AN 3 is inputted to the fifth D flip-flop DFF 5 .

The output of the fifth D flip-flop DFF 5 is inputted to the sixth D flip-flop DFF 6 . The output of the sixth D flip-flop DFF 6 is inputted to the ninth inverter IN 9 . The ninth inverter IN 9 inverts the output of the sixth D flip-flop DFF 6 and outputs an inverted output. The output of the ninth inverter IN 9 is the third output switching signal POUTB_B 1 < 0 >.

The fourth AND gate AN 4 performs an AND combination of the addresses AX< 2 : 1 > and outputs a result of the AND operation. The output of the fourth AND gate AN 4 is inputted to the seventh D flip-flop DFF 7 . The output of the seventh D flip-flop DFF 7 is inputted to the eighth D flip-flop DFF 8 .

The output of the eighth D flip-flop DFF 8 is inputted to the tenth inverter IN 10 . The output of the tenth inverter IN 10 is the fourth output switching signal POUTB_B 1 < 1 >.

The fifth to eighth D flip-flops DFF 5 to EFF 8 output the input data in response to the clock signal CK 4 CNT.

The sixth NAND gate NA 6 performs a NAND combination of the third and fourth output switching signals POUTB_B 1 < 0 > and POUTB_B 1 < 1 > and outputs a result of the NAND operation. The output of the sixth NAND gate NA 6 is the control signal SEL_B 1 _SYNCF.

The data I/O circuit 130 is operated in response to the control signals generated by the input control unit 520 and the output control unit 530 .

According to an exemplary embodiment of this disclosure, before data is outputted, the data is read twice in advance by the global lines GDL_B 0 < 15 : 0 > and GDL_B 1 < 15 : 0 >. Further, the read data stored in the first and the second registers 421 and 422 of the storage unit 132 is twice the amount stored by performing the data read just once in advance.

FIG. 6 is a timing diagram illustrating the operation of reading data in advance.

Referring to FIG. 6 , before a command input signal CLE (Command Latch Enable) and an address input signal ALE (Address Latch Enable) are enabled, clock cycles of the clock CLK are inputted to output data.

Prior to the input of the clock cycle of the clock CLK at the time of the actual output of read data, the read data is loaded in advance through the global lines in response to the internal clock signal CK 4 CNT. Here, the read data is first stored in the first and the second registers 421 and 422 of the storage unit 132 .

When one of the loaded data is outputted, the register from which the data has been outputted becomes available for receiving new data. Accordingly, new data is loaded on the relevant register.

FIG. 7 is an operational timing diagram illustrating the output of a control signal in FIGS. 5A to 5C .

Referring to FIG. 7 , when the column addresses AX_B 0 < 12 : 2 > and AX_B 1 < 12 : 2 > of the first and the second banks B 0 and B 1 are inputted, the first to fourth input switching signals PINB_B 0 < 0 >, PINB_B 0 < 1 >, PINB_B 1 < 0 >, and PINB_B 1 < 1 > are sequentially outputted in response to the addresses AX_B 0 < 2 > and AX_B 1 < 2 > and the control signals IO_DOSTB_B 0 and IO_DOSTB_B. Accordingly, two bits of data are stored in each of the first and second registers 421 and 422 of the storage unit 132 .

Two bits of data are read twice in advance and then sequentially outputted. Since two b its of data are read twice for each register in advance, a total of the eight bits of data are prepared to in advance be outputted through the four global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 >.

Thereafter, during the time for which first set of four data loaded in advance is outputted through the I/O pad unit 140 , a new set of four data (for example, a third set of four data) is loaded in advance. Accordingly, data can be rapidly outputted without stopping for data load.

FIG. 8 is a timing diagram illustrating a data output according to an exemplary embodiment of this disclosure.

A timing diagram shown in a region 810 of FIG. 8 corresponds to a timing diagram when data is loaded just once in advance on each of the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 >. A timing diagram shown in a region 820 of FIG. 8 corresponds to a timing diagram when data is loaded twice in advance on each of the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > through the data I/O circuit 130 and the logic group 160 of FIG. 4 and FIGS. 5A to 5C according to an exemplary embodiment of this disclosure.

In FIG. 8 , in the case where data is loaded just once in advance on each of the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > (that is, the region 810 ), the data is loaded in advance in response to the bank selection signals SEL_B 0 < 0 >, SEL_B 0 < 1 >, SEL_B 1 < 0 >, and SEL_B 1 < 1 >. To this end, registers (not shown) coupled to the global lines GDL_B 0 < 7 : 0 >, GDL_B 0 < 15 : 8 >, GDL_B 1 < 7 : 0 >, and GDL_B 1 < 15 : 8 > are to be used.

In the case where data is loaded just once in advance as described above at an advance read operation, an additional time for loading new data is taken after the loaded data is outputted.

In the case where data is loaded twice in advance according to the exemplary embodiment of this disclosure, however (that is, the region 820 ), two data loaded in advance is sequentially outputted in response to each of the first to fourth output switching signals POUTB_B 0 < 0 >, POUTB_B 0 < 1 >, POUTB_B 1 < 0 >, and POUTB_B 1 < 1 > according to the operation of FIG. 7 . Here, when one of the two data loaded in advance is outputted, new data is loaded. Accordingly, data can be rapidly outputted without a waiting time for data loading.

Effectiveness of this method is more pronounced when the time taken to load data once is longer than the time taken to output the data.

That is, if the time taken to load data just once is longer than the time taken to output the data, an additional time to load new data is taken after the completion of the output of the loaded data. If two data is loaded in advance as the present disclosure, second data is loaded in advance during the time for which first data is outputted, and an operation of loading third data can be performed in advance. Accordingly, the output of data is not stopped during the time for which data is loaded.

In accordance with the semiconductor memory device and the method of operating the same according to the exemplary embodiments of this disclosure, the amount of data outputted at one step and the data output speed are increased by increasing the size that data to be outputted is loaded. Here, such an increase in the data output speed may be achieved without increasing the number of data lines.