Buck converter with delay circuit

The disclosure generally relates to a buck converter.

Buck converters generally include two metal oxide semiconductor field effect transistors (MOSFETs) connected in series. A pulse width modulation (PWM) module provides a driver to gates of the two MOSFETs to alternatively turn on the two MOSFETs. However, at the time of the buck converters being turned on, a voltage applied to a drain of the MOSFETs must be applied before a voltage applied to the PWM module, or else the MOSFETs would be damaged.

Therefore, an improved buck converter is desired to overcome the above described shortcomings

Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is an illustrative view for a buck converter in accordance with a first embodiment.

FIG. 2 is an illustrative view for a delay circuit in FIG. 1 .

An embodiment of the present disclosure will now be described in detail below and with reference to the drawings.

Referring to FIG. 1 , a buck converter 100 in accordance with a first embodiment includes a power supply unit 110 , a first MOSFET Q 1 , a second MOSFET Q 2 , a PWM module 120 , a filter circuit 130 , a delay circuit 140 and a feedback circuit 150 .

The power supply unit 110 includes a first output terminal Vin and a second output terminal Vcc. The first output terminal Vin provides power to the first MOSFET Q 1 and the second MOSFET Q 2 . The second output terminal Vcc provides power to the PWM module 120 . The power supply unit 110 further includes a power good terminal PG. The power good terminal PG is used to illustrate whether voltages at the first output terminal Vin and the second output terminal Vcc are at predetermined values. When the voltages at the first output terminal Vin and the second output terminal Vcc are at the predetermined values, the power good terminal PG of the power supply unit 110 will output a high level voltage signal. In this embodiment, the power supply unit 110 outputs a voltage about 12V at the first output terminal Vin and outputs a voltage about 5V at the second output terminal Vcc.

A drain of the first MOSFET Q 1 is coupled to the first output terminal Vin and a source of the first MOSFET Q 1 is coupled to a drain of the second MOSFET Q 2 . A source of the second MOSFET Q 2 is coupled to the ground. In this embodiment, the first MOSFET Q 1 and the second MOSFET Q 2 are N-channel normally off device.

The PWM module 120 is coupled to gates of the first MOSFET Q 1 and the second MOSFET Q 2 to alternatively turn on or turn off the first MOSFET Q 1 and the second MOSFET Q 2 . That is, when the PWM module 120 provides a high level voltage signal to turn on the first MOSFET Q 1 , a corresponding low level voltage signal is provided to turn off the second MOSFET Q 2 . Similarly, when the PWM module 120 provides a high level voltage signal to turn on the second MOSFET Q 2 , a corresponding low level voltage signal is provided to turn off the first MOSFET Q 1 . The PWM module 120 further includes an input terminal Vcca for accepting power to the PWM module 120 .

The filter circuit 130 is coupled between the source of the first MOSFET Q 1 and an output node Vout of the buck converter 100 to provide a direct current (DC) voltage at the output node Vout. In this embodiment, the filter circuit 130 includes an inductor L and a first capacitor C 1 . One terminal of the inductor L is coupled to the source of the first MOSFET Q 1 , and the other terminal of the inductor L is coupled to the output node Vout. One terminal of the first capacitor C 1 is coupled to the output node Vout, and the other terminal of the first capacitor C 1 is coupled to the ground.

Referring also to FIG. 2 , the delay circuit 140 is coupled between the second output terminal Vcc and the input terminal Vcca of the PWM module 120 . The delay circuit 140 is used for delaying a voltage applied to the input terminal Vcca of the PWM module 120 . Therefore, the voltage applied to the PWM module 120 is after the voltage applied to the drain of the first MOSFET Q 1 . In this embodiment, the delay circuit 140 includes a third MOSFET Q 3 , a fourth MOSFET Q 4 and a fifth MOSFET Q 5 . A drain of the third MOSFET Q 3 is coupled to the second output terminal Vcca, a source of the third MOSFET Q 3 is coupled to the input terminal Vcca of the PWM module 120 , and a gate of the third MOSFET Q 3 is coupled to a drain of the fourth MOSFET Q 4 through a first resistor R 1 . A source of the fourth MOSFET Q 4 is coupled to the ground, a drain of the fourth MOSFET Q 4 is coupled to the first output terminal Vin through a second resistor R 2 , and a gate of the fourth MOSFET Q 4 is coupled to a drain of the fifth MOSFET Q 5 . A source of the fifth MOSFET Q 5 is coupled to the ground, a drain of the fifth MOSFET Q 5 is coupled to the first output terminal Vin through a third resistor R 3 , and a gate of the fifth MOSFET Q 5 is coupled to the power good terminal PG of the power supply unit 110 through a fourth resistor R 4 . A second capacitor C 2 is coupled between the gate and the drain of the fifth MOSFET Q 5 . In this embodiment, the third MOSFET Q 3 , the fourth MOSFET Q 4 and the fifth MOSFET Q 5 each are N-channel normally off MOSFET. In alternative embodiments, the third MOSFET Q 3 , the fourth MOSFET Q 4 and the fifth MOSFET Q 5 can be P-channel normally off MOSFET.

The operation of the delay circuit 140 will be described in following. When the power supply unit 110 is turned on, the power supply unit 110 provides voltages at the first output terminal Vin and the second output terminal Vcc. When the voltages at the first output terminal Vin and the second output terminal Vcc are at the predetermine values, the power supply unit 110 provides a high level voltage signal at the power good terminal PG. The voltage at the power good terminal PG will charge the second capacitor C 2 through the fourth resistor R 4 and make a voltage at the gate of the fifth MOSFET Q 5 increase gradually. When the voltage at the gate of the fifth MOSFET Q 5 increases to a threshold voltage of the fifth MOSFET Q 5 , the fifth MOSFET Q 5 turns on and the fourth MOSFET Q 4 turns off. Therefore, the voltage at the first output terminal Vin will be directly applied to the gate of the third MOSFET Q 3 through the first resistor R 1 and the second resistor R 2 . And then, the third MOSFET Q 3 is turned on and the voltage at the second output terminal Vcc can be applied to the input node Vcca of the PWM module 120 . In the operating process, a delay time of the delaying circuit 140 is determined by a capacitance of the second capacitor C 2 and a resistance of the fourth resistor R 4 . By changing the capacitance of the second capacitor C 2 or the resistance of the fourth resistor R 4 , the delay time of the delaying circuit 140 can be adjusted. Generally, the delay time of the delaying circuit 140 can be in a range from 100 ms to 200 ms. In alternative embodiments, the fourth resistor R 4 can be adjustable to adjust the delay time of the delaying circuit 140 .

The buck converter 100 can further include a feedback circuit 150 . The feedback circuit 150 is coupled between the output terminal Vout of the buck converter 100 and the PWM module 120 . By detecting the output voltage at the output node Vout, the feedback circuit 150 can settle the output voltage at the output node Vout to a constant value.

It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the disclosure.