Electrostatic discharge protection circuit

(a) Field of the Invention

The invention relates to an electronic circuit, particularly to an electrostatic discharge (ESD) protection circuit.

(b) Description of the Related Art

Electrostatic discharge (ESD) usually is the major cause of damage by electric stress for most electronic components. Such damage is permanent to an electronic component to thereby affect the normal operation of the electronic component. Generally, an electrostatic discharge (ESD) protection circuit is used to prevent electrostatic discharge damage.

A conventional ESD protection circuit uses a voltage rising speed to distinguish whether there is electrostatic discharge or not. However, if the power on operation is so fast to result in voltage quickly rising, the conventional ESD protection circuit cannot distinguish normal power on operation from electrostatic discharge to mistakenly start the ESD protection circuit to have an unexpected current flow through the ESD protection circuit.

One object of the invention is to provide an electrostatic discharge (ESD) protection circuit to prevent the unexpected false operation.

One object of the invention is to provide an electrostatic discharge (ESD) protection circuit to prevent normal turning-on operation from being recognized as electrostatic discharge to mistakenly start the electrostatic discharge (ESD) protection circuit.

One object of the invention is to provide an electrostatic discharge (ESD) protection circuit to prevent from mistakenly starting the electrostatic discharge (ESD) protection circuit due to power charge with quick voltage rising.

One object of the invention is to provide an electrostatic discharge (ESD) protection circuit to prevent from mistakenly starting the electrostatic discharge (ESD) protection circuit due to quick voltage rising.

One embodiment of the invention provides an electrostatic discharge (ESD) protection circuit, having a first node for receiving an input voltage. The ESD protection circuit comprises a voltage-divider generating circuit, a decision circuit, and a switching circuit. The voltage-divider generating circuit outputs a first voltage and a second voltage. The first voltage and the second voltage are used to respond to the variation of the transient voltage of the input voltage. The transient voltages of the first and the second voltage are different. The decision circuit is coupled to the voltage-divider generating circuit, receives the first voltage and the second voltage and determines the voltage level of an output voltage according to the first voltage and the second voltage. The switching circuit is coupled to the decision circuit and is either turned on or turned off according to the output voltage.

The ESD protection circuit according to the invention can recognize either electrostatic discharge or a normal operating voltage even under a condition of quick voltage rising to thereby prevent false operation of the ESD protection circuit.

Other objects and advantages of the invention can be better understood from the technical characteristics disclosed by the invention. In order to clarify the above mentioned and other objects and advantages of the invention, examples accompanying with figures are provided and described in details in the following.

FIG. 1 shows a schematic diagram illustrating an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention.

FIG. 2A shows a schematic diagram illustrating voltage simulation of an electrostatic discharge (ESD) protection circuit under quick voltage rising during powering on the circuit according to one embodiment of the invention.

FIG. 2B shows a schematic diagram illustrating current simulation corresponding to FIG. 2A .

FIG. 3A shows a schematic diagram illustrating voltage simulation of the electrostatic discharge (ESD) protection circuit when an electrostatic voltage V ESD occurs according to one embodiment of the invention.

FIG. 3B shows a schematic diagram illustrating current simulation corresponding to FIG. 3A .

FIG. 4 shows a schematic diagram illustrating an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention.

FIG. 5 shows a schematic diagram illustrating an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention.

FIG. 6 shows a schematic diagram illustrating an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention.

FIG. 7A shows a schematic diagram illustrating voltage simulation of an electrostatic discharge (ESD) protection circuit under quick voltage rising during powering on the circuit according to one embodiment of the invention.

FIG. 7B shows a schematic diagram illustrating current simulation corresponding to FIG. 7A .

FIG. 8A shows a schematic diagram illustrating voltage simulation of the electrostatic discharge (ESD) protection circuit when an electrostatic voltage V ESD occurs according to one embodiment of the invention.

FIG. 8B shows a schematic diagram illustrating current simulation corresponding to FIG. 8A .

FIG. 1 shows a schematic diagram illustrating an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention. As shown in FIG. 1 , the ESD protection circuit 100 comprises a voltage-divider generating circuit 101 , a decision circuit 102 , and a switching circuit 103 . The ESD protection circuit 100 has a node N 1 to receive an input voltage Vin and determines to either turn on or turn off the switching circuit 103 according to the voltage level of the input voltage Vin and the rising speed of the input voltage Vin in a transient period. When the switching circuit 103 is turned on, the current is released to ground potential G via the switching circuit 103 .

In one embodiment, as shown in FIG. 1 , the voltage-divider generating circuit 101 comprises resistors 101 a , 101 b and a capacitor 101 c . One end of the resistor 101 a is coupled to the node N 1 and the other end is coupled to the resistor 101 b in series. The decision circuit 102 is coupled to a node N 2 between the resistors 101 a and 101 b . The capacitor 101 c is coupled to the resistor 101 b . The decision circuit 102 is coupled to a node N 3 between the resistor 101 b and the capacitor 101 c . The nodes N 2 and N 3 separately output voltages V p and V n .

It should be noted that, in one embodiment, when the resistors 101 a and 101 b are coupled in series, the voltage levels of the voltages V p and V n are determined by the resistances of the resistors 101 a , 101 b and the capacitor 101 c . In another embodiment, the number of resistors and capacitors and the coupling method (for example, coupled in series or parallel) are not limited to the above example and can be determined according to a designer. Besides, the resistors and/or capacitors can be implemented by any current or future semiconductor element, such as transistors, etc.

In one embodiment, as shown in FIG. 1 , the decision circuit 102 comprises switches 102 a and 102 b . One end of the switch 102 a is coupled to the node N 2 of the voltage-divider generating circuit 101 , another end is coupled to the input voltage Vin, and the other end is coupled to the switch 102 b to form a node Nj. One end of the switch 102 b is coupled to the node N 3 of the voltage-divider generating circuit 101 , another end is coupled to the node Nj, and the other end is coupled to ground potential G.

The switches 102 a and 102 b receive the voltages V p and V n , respectively, and an output voltage V 3 is determined according to the voltages V p and V n . Thus, the decision circuit 102 varies the voltage level of the output voltage V 3 with the change of the voltage levels of the voltages V p and V n .

In one embodiment, the switch 102 a can be implemented by a P type metal oxide semiconductor field effect transistor (MOSFET) and the switch 102 b can be implemented by an N type MOSFET. Certainly, in another embodiment, the switches 102 a and 102 b are not limited to the above examples and can be implemented by any current or future semiconductor element.

In FIG. 1 as one example, the source electrode of the switch 102 a is coupled to the node N 1 and receives the input voltage Vin. The gate electrode of the switch 102 a determines to turn on or turn off or the current flowing through the switch 102 a according to the voltage level of the voltage V p . Besides, the turn-on voltage V 1 is the voltage difference between the input voltage Vin and the voltage V p , that is, V 1 =Vin−V p . The turn-on voltage V 2 is the voltage difference between the input voltage V n and the ground potential G, that is, V 2 =V n −0. Correspondingly, the drain electrode of the switch 102 b is coupled to the drain electrode of the switch 102 a . The source electrode of the switch 102 b is coupled to the ground potential G and the gate electrode of the switch 102 b determines to turn on or turn off or the current flowing through the switch 102 b according to the voltage level of the voltage V. Therefore, the voltage level of the output voltage V 3 of the decision circuit 102 can be adjusted by controlling the turn-on states of the switches 102 a and 102 b.

In one embodiment, the switching circuit 103 is coupled to the decision circuit 102 and the input voltage Vin and the turn-on or turn off state of the switching circuit 103 or the current flowing through the switch 102 a is determined according to the output voltage V 3 to thereby achieve the purpose of controlling the operation of the switching circuit 103 . For example, when the switching circuit 103 is enabled, the current is released to the ground potential G via the switching circuit 103 . In this embodiment, the switching circuit 103 can be implemented by an N type MOFET but is not limited to this example. In another embodiment, it can be implemented by any current or future semiconductor element.

The following illustrates the ESD protection circuit 100 determines the input voltage Vin received by the node N 1 to be either an operating voltage Vdd under quick start or an electrostatic voltage V ESD . Thus, please refer to FIG. 2A . In one embodiment of the invention, when the input voltage Vin is an operating voltage Vdd under quick start, the relation of the input voltage Vin during the quick power on period Tr (that is, the input voltage Vin is quick rising, usually Tr is smaller than 10 μs), the voltage V p and the resistors 101 a , 101 b substantially satisfies the following equations:

where Z 1 and Z 2 separately represent the equivalent resistances of the resistors 101 a and 101 b , Vdd represents the operating voltage of the input voltage Vin, V thp represents the threshold voltage of the switch 102 a , and V 1 represents the turn-on voltage of the switch 102 a . Noticeably, when the input voltage Vin is under the quick power on period Tr, since the input voltage Vin is rising very fast, the voltage difference of the capacitor 101 c will not vary instantaneously, one end of the capacitor 101 c is coupled to the ground potential and thus the voltage V n is close to zero. It should be noted that, after the quick power on period Tr, the effect of the capacitor 101 c starts and the voltages V p and V n are slowly rising, as shown in FIG. 2A .

Please refer to FIG. 2A . FIG. 2A shows a schematic diagram illustrating voltage simulation of the ESD protection circuit 100 under quick voltage rising during powering on the circuit according to one embodiment of the invention. From FIG. 2A , the relation of the voltages Vin, V p , and V n are shown.

The voltage-divider generating circuit 101 receives the input voltage Vin and outputs a voltage V p and a voltage V n according to the input voltage Vin. When the input voltage Vin is under quick power on period Tr (for example just powering on the circuit), the switch 102 a is under a turn-off state by designing the resistances Z 1 , Z 2 of the resistors 101 a , 101 b and the turn-on voltage V 1 formed by the transient voltage of the voltage V p and the operating voltage Vdd. It can be understood from FIG. 2A that during a transient period Tt, that is, the period from powering on (t=0) until a stable state including the quick power on period Tr, the turn-on voltage V 1 formed by the transient voltage of the voltage V p and the operating voltage Vdd makes the switch 102 a still under the turn-off state. Thus, from the above description, in the ESD protection circuit 100 , when the input voltage Vin is quickly rising and smaller than a preset value, the transient voltage of the voltage V p makes the switch 102 a still under the turn-off state. For example, in practice, the operating voltage is 3.3V and the preset value is set to 3.3V (or slightly higher than 3.3V). When the input voltage Vin is smaller than or equal to 3.3V, the transient voltage of the voltage V p outputted by the voltage-divider generating circuit 101 makes the switch 102 a still under the turn-off state.

Similarly, when the input voltage Vin is quickly rising and larger than another preset value, the transient voltage of the voltage V p makes the switch 102 a under the turn-on state. For example, in practice, the operating voltage is 3.3V and the preset value is set to 5V. When the input voltage Vin is larger than 5V, the transient voltage of the voltage V p outputted by the voltage-divider generating circuit 101 makes the switch 102 a under the turn-on state.

Besides, during the transient period Tt, the transient voltage of the voltage V p is different from that of the voltage V. In order to let the switching circuit 103 during the transient period Tt be turned off, the voltages V p , V n and the operating voltage Vdd have a preset relation, that is, the turn-on voltage V 1 formed by V p and Vdd makes the switch 102 a under the turn-off state.

It should be noted that, when the input voltage Vin is the operating voltage Vdd without interference of V ESD , the input voltage Vin of the ESD protection circuit 100 is under the quick power on period Tr and, from the above equation (2)

( V 1 = Z 1 Z 1 + Z 2 × Vdd < V thp )

and because of the divided voltage of the resistances Z 1 and Z 2 , the operating voltage Vdd makes the voltage level of the turn-on voltage V 1 smaller than the threshold voltage V thp of the switch 102 a . Certainly, because of the effect of the capacitor 101 c , after the quick power on period Tr and before the ESD protection circuit 100 is under a stable state, the voltage V p gradually rises and thus the voltage level of the turn-on voltage V 1 is still smaller than the threshold voltage V thp of the switch 102 a . Therefore, the switch 102 a is under the turn-off state to prevent the switching circuit 103 from having false operation to turn on the switch 102 a when the rising speed of the input voltage Vin is as fast as that of electrostatic discharge. As for the voltage level of the turn-on voltage V 2 of the node N 3 , since the input voltage Vin (Vdd) is quickly rising, the charge accumulation speed of the capacitor 101 c is slowed down and the voltage level of the turn-on voltage V 2 is still at a low voltage level (close to zero) to have the switch 102 b under the turn-off state. Since the switches 102 a and 102 b are both under the turn-off state, the node Nj is floating and the output voltage V 3 is unknown. Referring to FIG. 2B , the above mentioned output voltage V 3 is unknown and may cause the switching circuit 103 to be turned on and the ESD protection circuit 100 may generate an unexpected current flowing through the switching circuit 103 . However, since the voltage V n (that is, turn-on voltage V 2 ) after the quick power on period Tr is slowly rising, as soon as the voltage V n is larger than the threshold voltage V thn of the switch 102 b , the switch 102 b is under the turn-on state. At the time the output voltage V 3 is at a low voltage level to ensure the switching circuit 103 under the turn-off state. Compared to the unexpected maximum current value of a conventional ESD protection circuit being usually more than 400 mA, the unexpected maximum current value according to the embodiment is much smaller than 400 mA and thus the unexpected current is greatly reduced. After the ESD protection circuit 100 is under a stable state, from FIG. 2A , the voltage levels of V p and V n are separately equal to that of the operating voltage Vdd and the switching circuit 103 is still under the turn-off state.

When the input voltage Vin is the electrostatic voltage V ESD and the input voltage Vin is under the quick power on period Tr, the ESD protection circuit substantially satisfies the following equation:

V ESD - Vp = V 1 = Z 1 Z 1 + Z 2 × V ESD > V thp ( 3 )

where V ESD represents the voltage level generated at the time of electrostatic discharge.

Please refer to FIG. 3A . FIG. 3A shows a schematic diagram illustrating voltage simulation of the electrostatic discharge (ESD) protection circuit when the electrostatic voltage V ESD . is directed into the circuit according to one embodiment of the invention. From FIG. 3A , the relation of the voltages Vin, V p , and V n are shown.

When electrostatic discharge occurs and the input voltage Vin is the electrostatic voltage V ESD , from the above equation (3)

( V 1 = Z 1 Z 1 + Z 2 × V ESD < V thp ) ,

the voltage V ESD is still divided by the resistances Z 1 and Z 2 , the voltage level of the electrostatic voltage V ESD is far larger than the operating voltage Vdd even after voltage dividing and thus the voltage level of the turn-on voltage V 1 caused by the electrostatic voltage V ESD is larger than that of the threshold voltage V thp of the switch 102 a . Thus, the switch 102 a is under the turn-on state and the switching circuit 103 is turned on to release the current caused by the electrostatic voltage V ESD . Noticeably, after the period Tr of electrostatic voltage V ESD quickly rises, from FIG. 3A , it is found that the voltages V p and V n are still slowly rising and gradually close to the input voltage Vin. In FIG. 3A , the labeled time “t 2 ” indicates the time when the turn-on voltage V 2 formed by the voltage V p and the electrostatic voltage is smaller than the threshold voltage V thp of the switch 102 a . At the time, the switching circuit 103 is turned off.

The voltage level of the turn-on voltage V 2 of the node N 3 causes the charge accumulation speed of the capacitor 101 c to slow down because the electrostatic voltage V ESD is quickly rising. Thus, the voltage level of the turn-on voltage V 2 is still at a low level (close to zero) and the switch 102 b is still under the turn-off state. Noticeably, in this embodiment, the RC time constant composed of the resistors 101 a , 101 b and the capacitor 101 c is required to be larger than the period of electrostatic discharge to make the switch 102 b still under the turn-off state during the electrostatic discharge.

Please further refer to FIG. 3B . FIG. 3B shows a schematic diagram illustrating current simulation of the ESD protection circuit corresponding to FIG. 3A . In the period that the turn-on voltage V 1 is larger than the threshold voltage V thp of the switch 102 a , since the switching circuit 103 is turned on, an electrostatic discharge current (current shown in FIG. 3B ) is generated and flows through the switching circuit 103 to be released to the ground potential G via the switching circuit 103 to prevent permanent damage by the electrostatic voltage V ESD .

It should be noted that as shown in FIG. 3A , when the ESD protection circuit is under a stable state, the voltage levels of the electrostatic voltage V ESD , the voltage V p , and the voltage V n are almost the same.

Please refer to FIG. 4 . FIG. 4 shows a schematic diagram illustrating the voltage-divider generating circuit of an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention. As shown in FIG. 4 , the difference between the ESD protection circuit 200 and the ESD protection circuit 100 is that the resistors 201 a , 201 b are separately implemented by P type MOFETs. The gate electrodes of the resistors 201 a , 201 b are separately coupled to the ground potential G and the equivalent resistances of the resistors 201 a , 201 b are Z 1 and Z 2 , respectively. Till now, the rest of operating principle is the same as that of the protection circuit 100 . For clarity, the details will not be given hereinafter.

Please refer to FIG. 5 . FIG. 5 shows a schematic diagram illustrating the voltage-divider generating circuit of an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention. As shown in FIG. 5 , the difference between the ESD protection circuit 300 and the ESD protection circuit 100 is that the resistors 301 a , 301 b are separately implemented by N type MOFETs. The gate electrodes of the resistors 301 a , 301 b are separately coupled to operating voltage Vdd and the equivalent resistances of the resistors 301 a , 301 b are Z 1 and Z 2 , respectively. Till now, the rest of operating principle is the same as that of the protection circuit 100 . For clarity, the details will not be given hereinafter.

Please refer to FIG. 6 . FIG. 6 shows a schematic diagram illustrating an electrostatic discharge (ESD) protection circuit according to one embodiment of the invention. As shown in FIG. 6 , the difference between the ESD protection circuit 400 and the ESD protection circuit 100 is that the voltage-divider generating circuit 401 comprises resistors 401 a , 401 b , 401 c and a capacitor 401 d.

One end of the resistor 401 a is coupled to the node N 1 and the other end is coupled to the resistor 401 b in series. Two ends of the resistor 401 c are coupled in series to the resistor 401 b and the capacitor 401 d , respectively.

In addition, the decision circuit 402 is coupled to a node N 2 between the resistor 401 a and the resistor 401 b . The decision circuit 402 is also coupled to a node N 3 between the resistor 401 b and the resistor 401 c and the nodes N 2 and N 3 output the voltages V p and V n , respectively.

It should be noted that the resistors 401 a , 401 b , 401 c are coupled in series and thus the voltage level of the voltages V p and V n are determined by the resistances of the resistors 401 a , 401 b , 401 c and the capacitor 401 d according to the voltage divider theorem.

In one embodiment, as shown in FIG. 6 , the decision circuit 402 comprises switches 402 a and 402 b . One end of the switch 402 a is coupled to the node N 2 of the voltage-divider generating circuit 401 , another end is coupled to the input voltage Vin and the other end is coupled to the switch 402 b to form a node Nj. One end of the switch 402 b is coupled to the node N 3 of the voltage-divider generating circuit 401 , another end is coupled to the node Nj and the other end is coupled to ground potential G.

The switches 402 a and 402 b receive the voltages V p and V n , respectively. According to the voltages V p and V n , the voltage level of an output voltage V 3 is determined and thus the decision circuit 402 varies the voltage level of the output voltage V 3 with the change of the voltage level of the voltages V p and V n .

In one embodiment, the switch 402 a is implemented by a P type MOFET and the switch 402 b is implemented by an N type MOFET. Certainly, in another embodiment, the switches 402 a and 402 b are not limited to the above examples and can be implemented by any current or future semiconductor element.

As shown in FIG. 6 , the source electrode of the switch 402 a is coupled to the node N 1 and receives the input voltage Vin. The gate electrode of the switch 402 a determines to turn on or turn off or the current flowing through the switch 402 a according to the voltage level of the voltage V p .

Correspondingly, the drain electrode of the switch 402 b is coupled to the drain electrode of the switch 402 a . The source electrode of the switch 402 b is coupled to the ground potential G and the gate electrode of the switch 402 b determines to turn on or turn off or the current flowing through the switch 402 b according to the voltage level of the voltage V. Therefore, the voltage level of the output voltage V 3 of the decision circuit 402 can be adjusted by controlling the turn-on states of the switches 402 a and 402 b.

In one embodiment, the switching circuit 403 is coupled to the decision circuit 402 and the input voltage Vin and the turn-on or turn off state of the switching circuit 403 or the current flowing through the switching circuit 403 is determined according to the output voltage V 3 to thereby achieve the purpose of controlling the operation of the switching circuit 403 . For example, when the switching circuit 403 is turned on, the current is released to the ground potential G via the switching circuit 403 . In this embodiment, the switching circuit 403 can be implemented by an N type MOFET but is not limited to this example. In another embodiment, it can be implemented by any current or future semiconductor element.

The following illustrates the ESD protection circuit 400 determines the input voltage Vin received by the node N 1 to be either an operating voltage Vdd under quick start or an electrostatic voltage V ESD . Thus, please refer to FIG. 7A . In one embodiment of the invention, when the input voltage Vin is an operating voltage Vdd under quick start, the relation of the input voltage Vin during the quick power on period Tr (that is, the input voltage Vin is under quick rising, usually Tr is smaller than 10 μs), the voltages V p , V n and the resistors 401 a , 401 b , 401 c substantially satisfies the following equations:

where Z 1 , Z 2 , Z 3 represent the equivalent resistances of the resistors 401 a , 401 b , 401 c , respectively, Vdd represents the operating voltage of the input voltage Vin, V thp represents the threshold voltage of the switch 402 a , V thn represents the threshold voltage of the switch 402 b , V 1 represents the turn-on voltage of the switch 402 a , and V 2 represents the turn-on voltage of the switch 402 b . Besides, the turn-on voltage V 1 is the voltage difference between the input voltage Vin and the voltage V p , that is, V 1 =Vin−V p . The turn-on voltage V 2 is the voltage difference between the input voltage V n and the ground potential G, that is, V 2 =V n −0.

Noticeably, when the input voltage Vin is under the quick power on period Tr, since the input voltage Vin is rising very fast, the voltage difference of the capacitor 401 d will not vary instantaneously and thus in one embodiment the voltage V n outputted by the node N 3 is close to 1V according to the voltage divider theorem. It should be noted that, after the quick power on period Tr, the effect of the capacitor 401 d starts and the voltages V p and V n are slowly rising, as shown in FIG. 7A .

Please refer to FIG. 7A . FIG. 7A shows a schematic diagram illustrating voltage simulation of the ESD protection circuit 400 under quick voltage rising during powering on the circuit according to one embodiment of the invention. From FIG. 7A , the relation of the voltages Vin, V p , and V n are shown.

The voltage-divider generating circuit 401 receives the input voltage Vin and outputs a voltage V p and a voltage V n according to the input voltage Vin. When the input voltage Vin is under the quick power on period Tr (for example just powering on the circuit), the switch 402 a is under the turn-off state by designing the resistors 401 a , 401 b , 401 c , the corresponding resistances Z 1 , Z 2 , Z 3 and the turn-on voltage V 1 formed by the transient voltage of the voltage V p and the operating voltage Vdd. It can be understood from FIG. 7A that during a transient period Tt, that is, the period from powering on (t=0) until a stable state including the quick power on period Tr, the turn-on voltage V 1 formed by the transient voltage of the voltage V p and the operating voltage Vdd makes the switch 402 a still under the turn-off state. Besides, during the transient period Tt, the transient voltages of the voltages V p and V n are different. In order to let the switching circuit 403 during the transient period Tt be turned off, the voltages V p and V n are designed to have a preset relation, that is, the turn-on voltage V 1 formed by V p and Vdd makes the switch 402 a under the turn-off state.

It should be noted that, when the input voltage Vin is the operating voltage Vdd without interference of V ESD , the input voltage Vin of the ESD protection circuit 400 is under the quick power on period Tr and, from the above equation (7)

( Vdd - Vp = V 1 = Z 1 Z 1 + Z 2 + Z ⁢ ⁢ 3 × V dd < V thp )

and because of the divided voltage of the resistances Z 1 , Z 2 , Z 3 , the operating voltage Vdd makes the voltage level of the turn-on voltage V 1 smaller than the threshold voltage V thp of the switch 402 a . Certainly, because of the effect of the capacitor 401 d , after the quick power on period Tr and before the ESD protection circuit 400 is under a stable state, the voltage V p gradually rises and thus the voltage level of the turn-on voltage V 1 is still smaller than the threshold voltage V thp of the switch 402 a . Therefore, the switch 402 a is under the turn-off state to prevent the switching circuit 403 from having false operation to turn on the switch 402 a when the rising speed of the input voltage Vin is as fast as that of electrostatic discharge.

As for the voltage level of the turn-on voltage V 2 of the node N 3 , from the above equation (8)

( V n - 0 = V 2 = Z 3 Z 1 + Z 2 + Z ⁢ ⁢ 3 × V dd > V thn ) ,

it is found that the voltage level of the turn-on voltage V 2 is designed to be larger than the threshold voltage V thn of the switch 402 b . In this embodiment, the switch 402 b is under the turn-on state. In other words, regardless of being during the transient period Tt or after the ESD protection circuit 400 is under a stable state, the switch 402 b is always under the turn-on state. Thus, the output voltage V 3 of the node Nj is pulled to a low voltage level to ensure the switching circuit 403 not being activated to prevent the condition of the previous embodiment that the switches 102 a and 102 b are both under the turn-off state to make the node Nj under a floating state and the output voltage V 3 be unknown.

Please refer to FIG. 7B . FIG. 7B shows a schematic diagram illustrating current simulation of the ESD protection circuit corresponding to FIG. 7A . When the voltage is rising too fast (just powering on the circuit), the unexpected current is close to zero (current shown in FIG. 7B ). Compared to the unexpected maximum current value of the conventional ESD protection circuit being possibly more than 400 mA, the unexpected maximum current value of according to the embodiment is about 1.4 mA and thus the unexpected current is greatly reduced to thereby reduce the risk of short circuiting.

After the ESD protection circuit 400 is under a stable state, from FIG. 7A , the voltage levels of V p and V n are separately equal to that of the operating voltage Vdd and the switch 402 a is still under the turn-off state and the switch 402 b is under the turn-on state. The ESD protection circuit 400 is back to a power-off state.

When the input voltage Vin is the electrostatic voltage V ESD and the input voltage Vin is under the quick power on period Tr, the ESD protection circuit substantially satisfies the following equations:

V ESD - Vp = V 1 = Z 1 Z 1 + Z 2 + Z ⁢ ⁢ 3 × V ESD > V thp ( 9 ) V n - 0 = V 2 = Z 3 Z 1 + Z 2 + Z ⁢ ⁢ 3 × V ESD > V thn ( 10 )

where V ESD represents the voltage level generated at the time of electrostatic discharge.

From the equations (8) and (10), it can be understood that, regardless of being under normal operation or electrostatic discharge, the voltage level of the turn-on voltage V 2 is designed to be larger than the threshold voltage V thn of the switch 402 b.

Please refer to FIG. 8A . FIG. 8A shows a schematic diagram illustrating voltage simulation of the electrostatic discharge (ESD) protection circuit when the electrostatic voltage V ESD is directed into the circuit according to one embodiment of the invention. From FIG. 8A , the relation of the voltages Vin, V p , and V n are shown.

The switching circuit 403 is coupled to the decision circuit 402 and the input voltage Vin and the turn-on or turn off state of the switching circuit 403 is determined according to the output voltage V 3 . When the switching circuit 403 is turned on, the current is released to the ground (low) potential G via the switching circuit 403 . In this embodiment, the switching circuit 403 is implemented by an N type MOSFET but is not limited to this example.

When electrostatic discharge occurs and the input voltage Vin is the electrostatic voltage V ESD , from the above equation (9)

( V ESD - Vp = V 1 = Z 1 Z 1 + Z 2 + Z ⁢ ⁢ 3 × V ESD > V thp ) ,

the voltage V ESD is still divided by the resistances Z 1 , Z 2 and Z 3 , the voltage level of the electrostatic voltage V ESD is far larger than the operating voltage Vdd even after voltage dividing and thus the voltage level of the turn-on voltage V 1 caused by the electrostatic voltage V ESD is larger than that of the threshold voltage V thp of the switch 402 a . Thus, the switch 402 a is under the turn-on state and the switching circuit 403 is turned on to release the current caused by the electrostatic voltage V ESD . Noticeably, after the electrostatic voltage V ESD quickly rises (Tr), since some small current flows through the capacitor 401 d and the voltage of the capacitor 401 d rises slightly, from FIG. 8A , it is found that the voltages V p and V n are still slowly rising and gradually close to the input voltage Vin. In FIG. 8A , the labeled time “t 2 ” indicates the time when the turn-on voltage V 2 formed by the voltage V p and the electrostatic voltage is smaller than the threshold voltage V thp of the switch 402 a . At the time, the switching circuit 403 is turned off.

As for the turn-on voltage V 2 of the node N 3 , from the above equation (10), it is found that the voltage level of the turn-on voltage V 2 is larger than the threshold voltage V thn of the switch 402 b and the switch 402 b is under the turn-on state.

Please further refer to FIG. 8B . FIG. 8B shows a schematic diagram illustrating current simulation of the ESD protection circuit 400 corresponding to FIG. 8A . In the period that the turn-on voltage V 1 is larger than the threshold voltage V thp of the switch 402 a , since the switching circuit 403 is turned on, a current (current shown in FIG. 8B ) is generated and flows through the switching circuit 403 to be released to the ground potential G via the switching circuit 403 to prevent permanent damage by the electrostatic voltage V ESD .

Besides, a time constant corresponding to the resistors 401 a , 401 b , 401 c and the capacitor 401 d is required to be larger than the period of electrostatic discharge. In other words, the RC time constant composed of the resistors 401 a , 401 b , 401 c and the capacitor 401 d is required to be larger than the period of electrostatic discharge.

It should be noted that as shown in FIG. 8A , when the ESD protection circuit 400 is under a stable state, the voltage levels of the electrostatic voltage V ESD , the voltage V p , and the voltage V n are almost the same.

In practice, when electrostatic discharge occurs, the switches 402 a and 402 b are turned on simultaneously and the output voltage V 3 is determined by the turn-on resistances of the switches 402 a and 402 b . In other words, the turn-on resistances of the switches 402 a and 402 b should be properly designed to have the voltage level of the output voltage V 3 be able to turn on the switching circuit 403 . Since the equivalent resistance of the switching circuit 403 is smaller than that of the decision circuit 402 , the large current generated by electrostatic discharge can be released to the ground potential G via the switching circuit 403 to prevent the electronic elements from being damaged.

In conclusion, the ESD protection circuit according to the invention can recognize either electrostatic discharge or a normal operating voltage under a condition of quick voltage rising to prevent the ESD protection circuit from having false operation.

Although the present invention has been fully described by the above embodiments, the embodiments should not constitute the limitation of the scope of the invention. Various modifications or changes can be made by those who are skilled in the art without deviating from the spirit of the invention. Any embodiment or claim of the present invention does not need to reach all the disclosed objects, advantages, and uniqueness of the invention. Besides, the abstract and the title are only used for assisting the search of the patent documentation and should not be construed as any limitation on the implementation range of the invention.