Power circuit for data storage device to prevent data loss

1. Technical Field

The present disclosure relates to power circuits, and particularly to a power circuit for a data storage device.

2. Description of Related Art

At present, a solid state drive (SSD) is a data storage device that uses solid-state technology to store data with the intention of providing access in the same manner as a traditional block input or output hard disk drive (HDD). SSDs are distinguished from traditional HDDs, which are electromechanical devices containing spinning disks and movable read and write heads. SSDs, in contrast, use microchips which retain data in non-volatile memory chips and contain no moving parts. The SSD is characterized by factors such as high performance, low power consumption, small size, and other factors. However, if a sudden power failure occurs during writing of data to the SSD, the data will be lost. Therefore, there is room for improvement in the art.

Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram of a power circuit for a data storage device in accordance with an exemplary embodiment of the present disclosure, the power circuit includes a control circuit.

FIGS. 2 to 4 are circuit diagrams of the control circuit of FIG. 1 .

The disclosure, including the drawings, is illustrated by way of example and not by limitation. References to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to FIG. 1 , a power circuit 1 is arranged in a data storage device, such as a solid state drive (SSD) 2 . The SSD 2 is electrically connected to a motherboard 100 through an edge connector 70 arranged on an edge of the SSD 2 . The power circuit 1 in accordance with an exemplary embodiment includes a boost circuit 10 , an over-current protection circuit 20 , a control circuit 30 , a first buck circuit 40 , and a second buck circuit 50 .

The control circuit 30 includes a voltage detecting circuit 31 , a charging and discharging circuit 32 , a voltage selection circuit 33 , a charging capacitor 34 , and an indication circuit 35 . In one embodiment, the over-current protection circuit 20 is a fuse. The fuse operates when output current from the boost circuit 10 is greater than a preset current, to prevent the SSD 2 from being damaged. In one embodiment, the charging capacitor 34 is a supercapacitor.

The boost circuit 10 is configured to receive a first voltage, such as 1.5 volts (V), from the motherboard 100 and convert the first voltage to a second voltage, such as 5V. The boost circuit 10 outputs the second voltage to the voltage detecting circuit 31 , to the charging and discharging circuit 32 , and to the voltage selection circuit 33 through the over-current protection circuit 20 . The charging and discharging circuit 32 charges the charging capacitor 34 . The voltage detecting circuit 31 detects whether or not the over-current protection circuit 20 is outputting a voltage. When the motherboard 100 is powered on and the over-current protection circuit 20 is working normally, the voltage detecting circuit 31 detects the second voltage output from the over-current protection circuit 20 . The voltage detecting circuit 31 outputs a first select signal to the voltage selection circuit 33 and outputs a first indication signal to the indication circuit 35 , to indicate normal working for the motherboard 100 based on the over-current protection circuit 20 outputting the second voltage. The voltage selection circuit 33 outputs the second voltage to the first buck circuit 40 and the second buck circuit 50 according to the first selection signal. The first and second buck circuits 40 and 50 convert the second voltage to different voltages, such as 1.0V, 2.8V, 1.8V, and provide the converted voltage to a control chip 60 of the SSD 2 . When the motherboard 100 is subjected to a power failure or when the over-current protection circuit 20 is disconnected, the voltage detecting circuit 31 detects the non-output of a voltage by the over-current protection circuit 20 . The voltage detecting circuit 31 outputs a control signal to the charging and discharging circuit 32 , to cause that circuit to discharge the charging capacitor 34 and provide the stored electrical energy (the discharging voltage) to the voltage selection circuit 33 . At the same time, the voltage detecting circuit 31 outputs a second selection signal to the voltage selection circuit 33 , and also outputs a second indication signal to the indication circuit 35 to indicate a loss of normal power to the motherboard 100 . The voltage selection circuit 33 outputs the discharging voltage to the first and second buck circuits 40 and 50 according to the second selection signal. The first and second buck circuit 40 and 50 convert the discharging voltage to different voltages, such as 1.0V, 2.8V, 1.8V, and provide the converted voltages or one of them to the control chip 60 .

Referring to FIG. 2 , the charging and discharging circuit 32 includes a charging chip U 1 , an inductor L 1 , capacitors C 1 -C 5 , and resistors R 1 -R 5 . A first end of the inductor L 1 is connected to the boost circuit 10 through the over-current protection circuit 20 . An input pin VIN of the charging chip U 1 is connected to a second end of the inductor L 1 . The capacitor C 1 is connected between the first end of the inductor L 1 and ground. The capacitor C 2 is connected between the second end of the inductor L 1 and ground. The capacitor C 3 is connected between input and output (I/O) pins C+ and C− of the charging chip U 1 . The resistor R 1 is connected between an I/O pin SHDN of the charging chip U 1 and ground. An I/O pin VSEL of the charging chip U 1 is connected to the boost circuit 10 through the over-current protection circuit 20 and also grounded through the resistor R 2 . The resistors R 3 and R 4 are connected in parallel between an I/O pin PROG of the charging chip U 1 and ground. An I/O pin PGOOD of the charging chip U 1 is connected to an I/O pin COUT of the charging chip U 1 and the charging capacitor 34 through the resistor R 5 . The capacitors C 4 and C 5 are connected in parallel between the I/O pin COUT of the charging chip U 1 and ground. In one embodiment, a type of the charging chip U 1 may be LTC3225EDDB_TRMPBF.

Referring to FIG. 3 , the voltage detecting circuit 31 includes a voltage monitoring chip U 2 , diodes D 1 and D 2 , resistors R 6 -R 13 , and capacitors C 6 -C 10 . A sensing pin SENSE of the voltage monitoring chip U 2 is grounded through the capacitor C 8 and also connected to a first end of the resistor R 8 . A second end of the resistor R 8 is connected to an anode of the diode D 2 and also connected to the boost circuit 10 through the over-current protection circuit 20 . An I/O pin RESIN of the voltage monitoring chip U 2 is connected to the charging and discharging circuit 32 through the resistor R 9 . An I/O pin REF of the voltage monitoring chip U 2 is grounded through the capacitor C 9 . The resistor R 10 and the capacitor C 10 are connected in series and the other end of the resistor R 10 is connected to an I/O pin CT of the voltage monitoring chip U 2 to ground. An I/O pin RESET 1 of the voltage monitoring chip U 2 is connected to the voltage selection circuit 33 and the indication circuit 35 through the resistor R 11 . The I/O pin RESET 1 of the voltage monitoring chip U 2 is also connected to a voltage pin VCC of the voltage monitoring chip U 2 and the cathodes of the diodes D 1 and D 2 through the resistor R 11 and the resistor R 7 , connected in series. An I/O pin RESET 2 of the voltage monitoring chip U 2 is connected to a first end of the resistor R 12 . A second end of the resistor R 12 is connected to the voltage selection circuit 33 and is also grounded through the resistor R 13 . An anode of the diode D 1 is connected to the charging capacitor 34 through the resistor R 6 . The capacitors C 6 and C 7 are connected in parallel between the voltage pin VCC of the voltage monitoring chip U 2 and ground. In one embodiment, a type of the voltage monitoring chip U 2 may be TL7705BIDR.

Referring to FIG. 4 , the voltage selection circuit 33 includes a control chip U 3 , resistors R 14 -R 18 , and capacitors C 11 -C 15 . An input pin INA of the control chip U 3 is connected to the charging capacitor 34 and also grounded through the capacitor C 11 and the resistor R 14 connected in series. I/O pins ENBA and ENBB of the control chip U 3 are respectively connected to the I/O pins RESET 1 and RESET 2 of the voltage monitoring chip U 2 . An input pin INB of the control chip U 3 is connected to the boost circuit 10 through the over-current protection circuit 20 and also grounded through the capacitor C 12 and the resistor R 15 which are connected in series. Output pins OUTA and OUTB of the control chip U 3 are both connected to the indication circuit 35 and also connected to the first ends of the resistors R 16 , R 17 , and R 18 . The second ends of the resistors R 16 , R 17 , and R 18 are connected to the first and second buck circuits 40 and 50 . The capacitor C 13 is connected between the output pin OUTA of the control chip U 3 and ground. The capacitors C 14 and C 15 are connected in parallel between the second ends of the resistors R 16 , R 17 , and R 18 and ground. In one embodiment, a type of the control chip U 3 may be LTC4413EDD-1_TRPBF.

The indication circuit 35 includes a field effect transistor (FET) Q 1 , a light emitting diode (LED) D 10 , and resistors R 19 and R 20 . A gate of the FET Q 1 is connected to the I/O pin RESET 1 of the voltage monitoring chip U 2 through the resistor R 20 . A source of the FET Q 1 is grounded. A drain of the FET Q 1 is connected to a cathode of the LED D 10 . An anode of the LED D 10 is connected to the output pin OUTA of the control chip U 3 , through the resistor R 19 .

In use, the SSD 2 is inserted into a memory slot of the motherboard 100 by means of the edge connector 70 . The motherboard 100 is powered on and the over-current protection circuit 20 begins working normally, the boost circuit 10 receives 1.5V from the motherboard 100 and converts the 1.5V to 5V and provides the 5V to the charging chip U 1 , the voltage monitoring chip U 2 , and the control chip U 3 . The charging chip U 1 charges the charging capacitor 34 . The voltage monitoring chip U 2 detects the presence of the 5V through the sensing pin SENSE, and outputs a low level signal through the I/O pin RESET 1 to the I/O pin ENBA of the control chip U 3 and the gate of the FET Q 1 accordingly. The I/O pin RESET 2 of the voltage monitoring chip U 2 outputs a high level signal to the I/O pin ENBB of the control chip U 3 . The control chip U 3 outputs the 5V received by the input pin INB to the first and second buck circuits 40 and 50 through the output pins OUTA and OUTB. The first and second buck circuits 40 and 50 convert the 5V to different voltages and provide the converted voltages to the control chip 60 . The control chip 60 controls reading and writing of the SSD 2 . At the same time, the FET Q 1 is receiving a low level signal from the I/O pin RESET 1 of the voltage monitoring chip U 2 and is turned off. The LED D 10 is unlit, indicating that the motherboard 100 is working normally.

When a power failure does take place, or the over-current protection circuit 20 is disconnected, the sensing pin SENSE of the voltage monitoring chip U 2 stops experiencing the 5V, and therefore outputs a signal through the I/O pin RESIN to the charging and discharging circuit 32 , to cause the charging capacitor 34 to discharge and release the discharging voltage (which may be 4.5V for example) to the voltage selection circuit 33 . Simultaneously, the voltage monitoring chip U 2 outputs a high level signal through the I/O pin RESET 1 to the I/O pin ENBA of the control chip U 3 and the gate of the FET Q 1 . The I/O pin RESET 2 of the voltage monitoring chip U 2 outputs a low level signal to the I/O pin ENBB of the control chip U 3 . The control chip U 3 outputs the discharging voltage received from the input pin INA to the first and second buck circuits 40 and 50 through the output pins OUTA and OUTB. The first and second buck circuits 40 and 50 convert the discharging voltage they receive into different voltages and provide the converted voltages to the control chip 60 . The control chip 60 controls the storage of data in the SSD 2 . At the same time, the FET Q 1 receives the high level signal from the I/O pin RESET 1 of the voltage monitoring chip U 2 and is turned on. The LED D 10 lights up, to indicate that the motherboard 100 has lost normal power. The SSD 2 has sufficient time to complete the storage of data notwithstanding the loss of normal power to the motherboard 100 .

It is to be understood, however, that even though numerous characteristics and advantages of the disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and the arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.