Signal synchronizing systems

Conventional signal synchronizing systems change the synchronizing signals, e.g., internal clock signals, in response to any variation of the synchronized signals, e.g., external clock signals. Disadvantageously, the signal synchronizing system is sensitive to any change in the external clock signal, and the internal clock signal of the system is relatively unstable.

In one embodiment, a signal synchronizing system includes comparison circuitry and control circuitry coupled to the comparison circuitry. The comparison circuitry can compare a synchronizing signal with an input signal to generate a comparison result. The control circuitry can adjust the synchronizing signal into a range that is determined by the input signal, and control the range according to the comparison result.

Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, wherein like numerals depict like parts, and in which:

FIG. 1 illustrates a block diagram of an example of a signal synchronizing system, in accordance with one embodiment of the present invention.

FIG. 2 illustrates a circuit diagram of an example of the control circuitry in FIG. 1 , in accordance with one embodiment of the present invention.

FIG. 3 illustrates a timing diagram of examples of signals associated with the signal synchronizing system in FIG. 1 , in accordance with one embodiment of the present invention.

FIG. 4 illustrates a relation diagram of examples of a synchronizing signal and a lock range for the synchronizing signal, in accordance with one embodiment of the present invention.

FIG. 5 illustrates a flowchart of examples of operations performed by a signal synchronizing system, in accordance with one embodiment of the present invention.

FIG. 6 illustrates a flowchart of examples of operations performed by a signal synchronizing system, in accordance with one embodiment of the present invention.

Reference will now be made in detail to the embodiments of the present invention. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.

Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

In one embodiment, the present invention provides a system to synchronize a synchronizing signal, e.g., an internal clock or oscillating signal, with an input signal, e.g., an external clock or oscillating signal. The system can synchronize the synchronizing signal with the input signal by adjusting the frequency of the synchronizing signal into a range. The range can be, but is not necessarily, centered at the frequency of the input signal. The system can further control, e.g., widen or narrow, the range, such that the synchronizing signal can be synchronized with the input signal relatively accurately and have enhanced stability.

FIG. 1 illustrates a block diagram of an example of a signal synchronizing system 100 , in accordance with one embodiment of the present invention. The signal synchronizing system 100 , e.g., a frequency synchronizing system, is operable for synchronizing a synchronizing signal 108 , e.g., an internal clock/oscillating signal, with an input signal 110 , e.g., an external clock/oscillating signal. For example, the signal synchronizing system 100 generates a synchronizing signal 108 , and controls the synchronizing signal 108 so that is has substantially the same frequency as the input signal 110 .

The signal synchronizing system 100 includes control circuitry 150 and signal generator circuitry 152 . In one embodiment, the control circuitry 150 includes frequency comparator circuitry 102 and digital controller circuitry 104 . The digital controller circuitry 104 includes lock circuitry 116 and counter circuitry 118 . The signal generator circuitry 152 includes oscillator circuitry 106 .

The signal generator circuitry 152 generates the synchronizing signal 108 . The control circuitry 150 receives the synchronizing signal 108 and the input signal 110 , and adjusts a synchronizing frequency f OSC of the synchronizing signal 108 into a lock range that is determined by an input frequency f IN of the input signal 110 . The lock range can be, but may not be, centered at the input frequency f IN . If the synchronizing frequency f OSC is within the lock range, then the synchronizing frequency f OSC is considered to be equal to or substantially equal to the input frequency f IN . In other words, if the synchronizing frequency f OSC is within the lock range, then the synchronizing signal 108 is considered to be synchronized with the input signal 110 . In one embodiment, when the synchronizing frequency f OSC is within the lock range, the synchronizing frequency f OSC can remain unchanged as long as the variation of the input frequency f IN does not cause the synchronizing frequency f OSC to be outside the lock range. Moreover, in one embodiment, when the synchronizing frequency f OSC is adjusted into the lock range, the lock range is widened by the control circuitry 150 . Thus, advantageously, the stability of the signal synchronizing system 100 and the synchronizing signal 108 is enhanced.

More specifically, in one embodiment, the frequency comparator circuitry 102 compares the synchronizing frequency f OSC of the synchronizing signal 108 with the input frequency f IN of the input signal 110 to generate a comparison result 112 . The comparison result 112 indicates a status of the difference between the synchronizing frequency f OSC and the input frequency f IN . The comparison result 112 can include one of three situations: the synchronizing frequency f OSC is less than the input frequency f IN ; the synchronizing frequency f OSC is greater than the input frequency f IN ; or the synchronizing frequency f OSC is substantially equal to the input frequency f IN . The digital controller circuitry 104 generates a control signal 114 to the oscillator circuitry 106 according to the comparison result 112 . The oscillator circuitry 106 adjusts the synchronizing frequency f OSC according to the control signal 114 . By way of example, if the synchronizing frequency f OSC is less than the input frequency f IN , e.g., the synchronizing frequency f OSC is less than the input frequency f IN minus a first frequency offset f OSC , then the control signal 114 increases the synchronizing frequency f OSC . In other words, if the difference f OSC −f IN is less than a first frequency offset −f OSC , the signal generator circuitry 152 increases the synchronizing frequency f OSC . If the synchronizing frequency f OSC is greater than the input frequency f IN , e.g., the synchronizing frequency f OSC is greater than the input frequency f IN plus a second frequency offset f OS2 , then the control signal 114 decreases the synchronizing frequency f OSC . In other words, if the difference f OSC −f IN is greater than the frequency offset f OS2 , the signal generator circuitry 152 decreases the synchronizing frequency f OSC . Thus, the synchronizing frequency f OSC can be adjusted into a range of f IN −f OS1 to f IN +f OS2 (hereinafter, range (f IN −f OS1 , f IN +f OS2 )). The range (f IN −f OS1 , f IN +f OS2 ) can be referred to as a lock range. The first frequency offset f OSC and the second frequency offset f OS2 can be, but may not be, the same. When the synchronizing frequency f OSC is within the lock range, the synchronizing frequency f OSC is considered to be equal to or substantially equal to the input frequency f IN .

In other words, the signal generator circuitry 152 can generate the synchronizing signal 108 according to the comparison result 112 , e.g., the difference between the synchronizing signal 108 and the input signal 110 . The control circuitry 150 can generate the comparison result 112 by comparing the synchronizing signal 108 and the input signal 110 , such that the synchronizing signal 108 is adjusted into a lock range, e.g., range (f IN −f OS1 , f IN +f OS2 ).

Furthermore, the digital controller circuitry 104 controls the lock range according to the comparison result 112 , e.g., the difference between the synchronizing frequency f osc and the input frequency f IN . By way of example, if the comparison result 112 indicates that the synchronizing signal 108 is outside the lock range (f IN −f OS1 , f IN +f OS2 ), e.g., f OSC −f IN <−f OS1 or f OSC −f IN >f OS2 , the digital controller circuitry 104 controls the lock range to have a first width, e.g., f OS1 +f OS2 . If the comparison result 112 indicates that the synchronizing signal 108 is within the lock range (f IN −f OS1 , f IN +f OS2 ), e.g., −f OS1 <f OSC −f IN <f OS2 , the lock circuitry 116 generates a lock/unlock signal 120 to lock the synchronizing signal 108 , e.g., by controlling the lock range to have a second width that is greater than the first width. For instance, the digital controller circuitry 104 can adjust the first frequency offset from f′ OS1 to f′ OS1 (f OS1 <f′ OS1 ) and adjust the second frequency offset from f OS2 to f′ OS2 (f OS2 <f′ OS2 ), and therefore the lock range is from f IN −f′ OS1 to f IN +f′ OS2 . In this instance, the second width of the lock range is f′ OS1 +f′ OS2 and is greater than the first width f OS1 +f OS2 .

In operation, in one embodiment, when the signal synchronizing system 100 is enabled, the lock range for the synchronizing signal 108 is preset to the range (f IN −f OS1 , f IN +f OS2 ), and the lock range has the first width f OS1 +f OS2 . If the synchronizing signal 108 is outside the range (f IN −f OS1 , f IN +f OS2 ), the control circuitry 150 adjusts the synchronizing frequency f OSC toward the input frequency f IN . When the synchronizing frequency f OSC is adjusted to be substantially equal to the input frequency f IN , e.g., the synchronizing frequency f OSC is within the range (f IN −f OS1 , f IN +f OS2 ), the lock circuitry 116 generates a lock/unlock signal 120 to lock the synchronizing signal 108 , e.g., by increasing the lock range to the second width f′ OS1 +f′ OS2 . The synchronizing frequency f OSC can remain unchanged as long as the synchronizing frequency f OSC is within the range (f IN −f′ OS1 , f IN +f′ OS2 ). In other words, the synchronizing frequency f OSC can remain unchanged if the variation of the input frequency f IN does not cause the synchronizing frequency f OSC to be outside the range (f IN −f′ OS1 , f IN +f′ OS2 ). Additionally, if a change in the input frequency f IN causes the synchronizing frequency f OSC to be outside the range (f IN −f′ OS1 , f IN +f′ OS2 ), the lock circuitry 116 generates a lock/unlock signal 120 to unlock the synchronizing signal 108 , e.g., by decreasing the lock range to the first width f OS1 +f OS2 . The control circuitry 150 can adjust the synchronizing signal 108 into the range (f IN −f OS1 , f IN +f OS2 ) again.

In one embodiment, compared with the input frequency f IN , the first width f OS1 +f OS2 is relatively small. In addition, the second width f′ OS1 +f′ OS2 can be set according to a normal variation amplitude of the input frequency f IN . For example, the second width f′ OS1 +f′ OS2 can be greater than the normal variation amplitude of the input frequency f IN . As a result, the synchronizing signal 108 can be synchronized with the input signal 110 relatively accurately, and the stability of the synchronizing signal 108 can be enhanced.

FIG. 2 illustrates a circuit diagram of an example of the control circuitry 150 , in accordance with one embodiment of the present invention. FIG. 2 is described in combination with FIG. 1 . The control circuitry 150 includes the frequency comparator circuitry 102 , the lock circuitry 116 , and the counter circuitry 118 .

As shown in FIG. 2 , the frequency comparator circuitry 102 includes a frequency divider 220 , a pulse generator 224 , a power source 230 , a charging switch 240 , a discharging switch 242 , capacitive circuitry 226 , and comparators 236 and 238 . In the example of FIG. 2 , the power source 230 includes a frequency-controlled current source, and the capacitive circuitry 226 includes a capacitor.

In one embodiment, the frequency divider 220 receives the input signal 110 and generates a clock signal DIV_IN (hereinafter, DIV_IN signal) having a frequency that is ½ n times of the input frequency f IN (n=0, 1, 2, . . . ). The cycle of the DIV_IN signal therefore is equal to 2 n /f IN . Additionally, the duty cycle of the DIV_IN signal is controlled to be ½ g . Thus, the time when the DIV_IN signal is logic high in each cycle is equal to the time of 1/f IN . The charging switch 240 is turned on when the DIV_IN signal is logic high, and is turned off when the DIV_IN signal is logic low. In other words, the charging switch 240 can be controlled by the input signal 110 . The pulse generator 224 can generate a pulse signal PULSE (hereinafter, PULSE signal) at each rising edge of the DIV_IN signal to turn on the discharging switch 242 . In one embodiment, the power source 230 generates a charging current I OSC , according to the synchronizing frequency f OSC and a preset reference V REF , to charge the capacitive circuitry 226 via the charging switch 240 . The charging current I OSC can be given by:

I OSC =C OSC *V REF *f OSC ,  (1)

where C OSC represents a capacitance parameter in the oscillator circuitry 106 . In one such embodiment, during a cycle of the DIV_IN signal, the charging switch 240 is turned on for the time of 1/f IN . Therefore, the capacitive circuitry 226 is charged to have a top voltage level V OSC that is given by:

V OSC =I OSC /( C RAMP *f IN ),  (2)

where C RAMP represents capacitance of the capacitive circuitry 226 . According to equations (1) and (2), the following equation is obtained:

f OSC /f IN =( V OSC /V REF )*( C RAMP /C OSC ).  (3)

Equation (3) can also be written as:

f OSC −f IN =[( V OSC /V REF )*( C RAMP /C OSC )−1 ]*f IN .  (4)

The capacitances C OSC and C RAMP can be chosen such that the ratio C OSC /C RAMP is equal to one. As such, equations (3) and (4) can be rewritten as:

f OSC /f IN =V OSC /V REF , and  (5)

f OSC −f IN =( V OSC /V REF −1)* f IN .  (6)

Accordingly, if the top voltage level V OSC is equal to the preset reference V REF , the synchronizing frequency f OSC is equal to the input frequency f IN . Additionally, if the top voltage level V OSC is greater than the preset reference V REF , the synchronizing frequency f OSC is greater than the input frequency f IN . If the top voltage level V OSC is less than the preset reference V REF , the synchronizing frequency f OSC is less than the input frequency f IN .

In one such embodiment, at each rising edge of the DIV_IN signal, the PULSE signal turns on the discharging switch 242 to discharge the capacitive circuitry 226 , and a ramp voltage V RAMP on the capacitive circuitry 226 can drop to zero volts. In addition, during each cycle of the DIV_IN signal, the DIV_IN signal turns on the charging switch 240 for the time of 1/f IN , and turns off the charging switch 240 during the rest of the cycle. Accordingly, in each cycle of the DIV_IN signal, the ramp voltage V RAMP can increase from zero volts to the top voltage level V OSC , and then remain unchanged until the cycle expires, e.g., the discharging switch 242 is turned on.

A timing diagram of examples of the input signal 110 , the DIV_IN signal, the PULSE signal, the ramp voltage V RAMP , and a clock signal CLK (hereinafter, CLK signal) is illustrated in FIG. 3 , in accordance with one embodiment of the present invention. FIG. 3 is described in combination with FIG. 1 and FIG. 2 . In the example of FIG. 3 , the frequency of the DIV_IN signal is ¼ times of the input frequency f IN . Since the duty cycle of the DIV_IN signal is controlled to be ¼, the time when the DIV_IN signal is logic high in a cycle of the DIV_IN signal is equal to the time of 1/f IN .

As shown in FIG. 3 , during time t 0 to time t 1 , the DIV_IN signal is logic high and the PULSE signal is logic low. Thus, the charging switch 240 is on and the discharging switch 242 is off. The ramp voltage V RAMP increases due to the charging of the capacitive circuitry 226 . At time t 1 , the ramp voltage V RAMP increases to the top voltage level V OSC , e.g., given by equation (2). During time t 1 to time t 2 , the DIV_IN and PULSE signals are logic low and the switches 240 and 242 are off. Therefore, the ramp voltage V RAMP remains at the top voltage level V OSC . At time t 2 , in response to a rising edge of the DIV_IN signal, the PULSE signal becomes logic high to turn on the discharging switch 242 . The ramp voltage V RAMP can drop to zero volts due to the discharging of the capacitive circuitry 226 . In the cycle from time t 2 to time t 4 , the DIV_IN signal, the PULSE signal, and the ramp voltage V RAMP can be similar to those in the cycle from time t 0 to time t 2 .

Returning to FIG. 2 , the comparators 236 and 238 compare the top voltage level V OSC with a low boundary reference V L and a high boundary reference V H (V H >V L ) to generate digital signals D UP and D DOWN . In one embodiment, the comparison result 112 in FIG. 1 includes the digital signals D UP and D DOWN . In one embodiment, the boundary references V L and V H are determined by the preset reference V REF in equation (1). For example, the low boundary reference V L is equal to the preset reference V REF minus a voltage offset V OS1 , and the high boundary reference V H is equal to the preset reference V REF plus a voltage offset V OS2 . If the top voltage level V OSC is less than the low boundary reference V L , e.g., V REF −V OS1 , then the digital signal D UP is logic high and the digital signal D DOWN is logic low, i.e., D UP =1 and D DOWN =0. If the top voltage level V OSC is greater than high boundary reference V H , e.g., V REF +V OS2 , then the digital signal D UP is logic low and the digital signal D DOWN is logic high, i.e., D UP =0 and D DOWN =1. If the top voltage level V OSC is in the range from V L to V H , e.g., in the range V REF −V OS1 to V REF +V OS2 , then the digital signals D UP and D DOWN are logic low, i.e., D UP =0 and D DOWN =0. In one embodiment, when the top voltage level V OSC is in the range from V REF −V OS1 to V REF +V OS2 , the synchronizing frequency f OSC is in the range from f IN −f OS1 to f IN +f OS2 . According to equation (6), the first frequency offset f OS1 and the second frequency offset f OS2 can be given by:

f OS1 =( V OS1 /V REF )* f IN ; and  (7a)

f OS2 =( V OS2 /V REF ) f IN .  (7b)

As shown in FIG. 2 , the control circuitry 150 further includes a delayer 222 to generate a CLK signal to trigger the counter circuitry 118 . The counter circuitry 118 can receive the digital signals D UP and D DOWN at each rising edge (or falling edge) of the CLK signal. The CLK signal is a delayed signal of the DIV_IN signal. The CLK signal can be delayed the amount of time it takes for the DIV_IN signal to be logic high in a cycle. For the example of FIG. 3 , in the cycle from time t 0 to time t 2 , the CLK signal is delayed to the time t 1 . However, the invention is not so limited. The CLK signal can also be delayed any time that is longer than the time during which the DIV_IN signal is logic high in a cycle and shorter than the time of the cycle. By way of example, in the cycle from time t 0 to time t 2 of FIG. 3 , the CLK signal can be delayed to any time between times t 1 and t 2 . As such, when the counter circuitry 118 is triggered by the CLK signal, the counter circuitry 118 receives the digital signals D UP and D DOWN that indicate the comparison result between the top voltage level V OSC and the boundary references V L and V H .

In one embodiment, the counter circuitry 118 generates a control signal 114 , e.g., a digital signal having a value D CTL , by accumulating/counting the comparison result 112 , e.g., the digital signals D UP and D DOWN . By way of example, in response to each rising edge (or falling edge) of the CLK signal, the counter circuitry 118 increases the value D CTL by a predetermined amount ΔD if the digital signal D UP is “1”, or decreases the value D CTL by the predetermined amount ΔD if the digital signal D DOWN is “1”, or maintains the value D CTL unchanged if both the digital signals D UP and D DOWN are “0”. In addition, the oscillator circuitry 106 in FIG. 1 can increase the synchronizing frequency f OSC if the value D CTL increases, and decrease the synchronizing frequency f OSC if the value D CTL decreases. Thus, if the synchronizing frequency f OSC is less than the frequency f IN −f OS1 , e.g., D UP =1 and D DOWN =0, the counter circuitry 118 can increase the value D CTL incrementally by accumulating the digital signal D UP . The synchronizing frequency f OSC can increase accordingly. If the synchronizing frequency f OSC is greater than the frequency f IN +f OS2 , e.g., D UP =0 and D DOWN =1, the counter circuitry 118 can decrease the value D CTL incrementally by accumulating the digital signal D DOWN . The synchronizing frequency f OSC can decrease accordingly. If the synchronizing frequency f OSC is in the range (f IN −f OS1 , f IN +f OS2 ), e.g., D UP =0 and D DOWN =0, the value D CTL remains unchanged to maintain the synchronizing frequency f OSC unchanged.

In one embodiment, the lock circuitry 116 controls the lock range of the synchronizing signal 108 by controlling the boundary references provided to the comparators 236 and 238 . By way of example, the lock circuitry 116 includes voltage sources 228 , 232 and 234 , and a control unit 244 . The voltage source 228 provides a preset reference V REF , e.g., that determines the charging current I OSC according to equation (1). The voltage sources 232 and 234 can provide the voltage offset V OS1 and the voltage offset V OS2 , respectively. Therefore, the lock circuitry 116 can provide the low boundary reference V L , e.g., V REF −V OS1 , and the high boundary reference V H , e.g., V REF +V OS2 , to the comparators 236 and 238 . The voltage sources 232 and 234 can also provide a voltage offset V′ OS1 , e.g., V′ OS1 >V OS1 , and a voltage offset V′ OS2 , e.g., V′ OS2 >V OS2 , respectively. Therefore, the lock circuitry 116 can provide a low boundary reference V′ L , e.g., V REF −V′ OS1 , and a high boundary reference V′ H , e.g., V REF +V′ OS2 , to the comparators 236 and 238 . More specifically, the control unit 244 generates control signals 246 and 248 to control the voltage sources 232 and 234 . In one embodiment, the lock/unlock signal 120 in FIG. 1 includes the control signals 246 and 248 . The control signals 246 and 248 control the voltage sources 232 and 234 to provide the voltage offsets V OS1 and V OS2 , or V′ OS1 and V′ OS2 , according to the digital signals D UP and D DOWN . On one hand, if the digital signals D UP and D DOWN indicate that the synchronizing signal 108 is outside the lock range, e.g., D UP =1 or D DOWN =1, the voltage sources 232 and 234 provide the voltage offsets V OS1 and V OS2 , and therefore the lock circuitry 116 provides the boundary references V L and V H to the comparators 236 and 238 . The lock range of the synchronizing signal 108 can be from f IN −f OS1 to f IN +f OS2 (e.g., from f IN *(1−V OS1 /V REF ) to f IN *(1+V OS2 /V REF ), and have a first width f OS1 +f OS2 (e.g., f IN *(V OS1 +V OS2 )/V REF ). On the other hand, if the digital signals D UP and D DOWN indicate that the synchronizing signal 108 is within the lock range, e.g., D UP =0 and D DOWN =0, the voltage sources 232 and 234 provide the voltage offsets V′ OS1 and V′ OS2 , and therefore the lock circuitry 116 provides the boundary references V′ L and V′ H to the comparators 236 and 238 . The lock range of the synchronizing signal 108 can be from f IN −f′ OS1 to f IN +f′ OS2 (e.g., from f IN *(1−V′ OS1 /V REF ) to f IN *(1+V OS2 /V REF ), and have a second width f′ OS1 +f′ OS2 (e.g., f IN *(V′ OS1 +V′ OS2 )/V REF ) that is greater than the first width f OS1 +f OS2 .

A relation diagram of examples of the synchronizing signal 108 and the lock range for the synchronizing signal 108 is illustrated in FIG. 4 , in accordance with one embodiment of the present invention. FIG. 4 is described in combination with FIG. 1 and FIG. 2 . In the example of FIG. 4 , during time t 0 to time t b , the top voltage level V OSC of the ramp voltage V RAMP is less than the low boundary reference V L , e.g., the synchronizing frequency f OSC is less than the frequency f IN −f OS1 . During time t 0 to time t f , the top voltage level V OSC of the ramp voltage V RAMP is greater than the high boundary reference V H , e.g., the synchronizing frequency f OSC is greater than the frequency f IN +f OS2 . During time t c to time t d , the top voltage level V OSC of the ramp voltage V RAMP is within the range of V′ L to V′ H , e.g., the synchronizing frequency f OSC is within the range (f IN −f′ OS1 , f IN +f′ OS2 ).

In one embodiment, when the signal synchronizing system 100 is enabled, the lock circuitry 116 provides the boundary references V L and V H to the frequency comparator circuitry 102 , such that the lock range for the synchronizing signal 108 is preset to be from f IN −f OS1 to f IN +f OS2 . If the synchronizing frequency f OSC is outside the range (f IN −f OS1 , f IN +f OS2 ), e.g., during time t 0 to t b or during time t 0 to time t f , the signal synchronizing system 100 adjusts the synchronizing frequency f OSC toward the input frequency f IN . When the synchronizing frequency f OSC is adjusted into the range (f IN −f OS1 , f IN +f OS2 ), the lock circuitry 116 provides the boundary references V′ L and V′ H to the frequency comparator circuitry 102 , e.g., during time t c to time t d , such that the lock range for the synchronizing signal 108 becomes to be from f IN −f′ OS1 to f IN +f′ OS2 . As shown in FIG. 4 , the range (f IN −f′ OS1 , f IN +f′ OS2 ) represented by the parameter ΔV 2 is wider than the range (f IN −f OS1 , f IN +f OS2 ) represented by the parameter ΔV 1 . Additionally, if a change in the input frequency f IN causes the synchronizing frequency f OSC to be outside the range (f IN −f′ OS1 , f IN +f′ OS2 ), the lock range for the synchronizing signal 108 can become to be from f IN −f OS1 to f IN +f OS2 again.

FIG. 5 illustrates a flowchart 500 of examples of operations performed by the signal synchronizing system 100 , in accordance with one embodiment of the present invention. Although specific steps are disclosed in FIG. 5 , such steps are examples for illustrative purposes. That is, the present invention is well suited to performing various other steps or variations of the steps recited in FIG. 5 . FIG. 5 is described in combination with FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 .

When the signal synchronizing system 100 is enabled, the lock range for the synchronizing signal 108 is set to be from f IN −f OS1 to f IN +f OS2 . By way of example, the lock circuitry 116 provides the boundary references V L and V H to the comparators 236 and 238 . At step 502 , the frequency comparator circuitry 102 generates the digital signals D UP and D DOWN by comparing the synchronizing frequency f OSC with the input frequency f IN based on the range (f IN −f OS1 , f IN +f OS2 ). If the synchronizing frequency f OSC is less than the frequency f IN −f OS1 , then D UP =1 and D DOWN =0. If the synchronizing frequency f OSC is greater than the frequency f IN +f OS2 , then D UP =0 and D DOWN =1. If the synchronizing frequency f OSC is substantially equal to the input frequency f IN , e.g., the synchronizing frequency f OSC is greater than the frequency f IN −f OS1 and less than the frequency f IN +f OS2 , then D UP =0 and D DOWN =0.

At step 504 , the counter circuitry 118 controls a value D CTL of the control signal 114 according to the digital signals D UP and D DOWN . By way of example, if D UP =1 and D DOWN =0, the flowchart 500 goes to step 506 to increase the value D CTL . If D UP =0 and D DOWN =1, the flowchart 500 goes to step 508 to decrease the value D CTL . If D UP =0 and D DOWN =0, the flowchart 500 goes to step 512 to maintain the value D CTL unchanged and lock the synchronizing frequency f OSC .

At step 506 , the counter circuitry 118 increases the value D CTL by counting/accumulating the digital signal D UP . For example, the counter circuitry 118 increases the value D CTL by a predetermined amount AD when receiving the digital signal D UP that is “1”. At step 508 , the counter circuitry 118 decreases the value D CTL by counting/accumulating the digital signal D DOWN . For example, the counter circuitry 118 decreases the value D CTL by a predetermined amount AD when receiving the digital signal D DOWN that is “1”. At step 510 , the oscillator circuitry 106 increases the synchronizing frequency f OSC if the value D CTL increases, and decreases the synchronizing frequency f OSC if the value D CTL decreases. Following step 510 , the flowchart 500 can return to step 502 .

At step 512 , the lock circuitry 116 locks the synchronizing frequency f OSC by increasing the lock range from the first width f OS1 +f OS2 to the second width f′ OS1 +f′ OS2 . The lock range for the synchronizing frequency f OSC becomes to be from f IN −f′ OS1 to f IN +f′ OS2 . By way of example, the lock circuitry 116 provides the boundary references V′ L and V′ H to the comparators 236 and 238 .

At step 514 , the frequency comparator circuitry 102 generates the digital signals D UP and D DOWN by comparing the synchronizing frequency f OSC with the input frequency f IN based on the range (f IN −f′ OS1 , f IN +f′ OS2 ). If the synchronizing frequency f OSC is less than the frequency f IN −f′ OS1 , then D UP =1 and D DOWN =0. If the synchronizing frequency f OSC is greater than the frequency f IN +f′ OS2 , then D UP =0 and D DOWN =1. If the synchronizing frequency f OSC is greater than the frequency f IN −f′ OS1 and less than the frequency f IN +f′ OS2 , then D UP =0 and D DOWN =0.

At step 516 , if the synchronizing frequency f OSC is in the range (f IN −f′ OS1 , f IN +f′ OS2 ), e.g., D UP =0 and D DOWN =0, the flowchart 500 goes to step 512 . If the synchronizing frequency f OSs is outside the range (f IN −f′ OS1 , f IN +f′ OS2 ), e.g., D UP =1 or D DOWN =1, the flowchart 500 goes to step 518 . At step 518 , the lock circuitry 116 unlocks the synchronizing frequency f OSC by decreasing the lock range from the second width f′ OS1 +f′ OS2 to the first width f OS1 +f OS2 . The lock circuitry 116 can provide the boundary references V L and V H to the comparators 236 and 238 , such that the lock range for the synchronizing frequency f OSC becomes to be from f IN −f OSC to f IN +f OS2 . Following step 518 , the flowchart 500 can return to step 502 .

By performing the operations of the flowchart 500 , the signal synchronizing system 100 can synchronize the synchronizing signal 108 with the input signal 110 relatively accurately, and enhance the stability of the synchronizing signal 108 .

FIG. 6 illustrates a flowchart 600 of examples of operations performed by the signal synchronizing system 100 , in accordance with one embodiment of the present invention. FIG. 6 is described in combination with FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 and FIG. 5 .

In block 602 , the frequency comparator circuitry 102 compares the synchronizing frequency f OSC of the synchronizing signal 108 with the input frequency f IN of the input signal 110 to generate the comparison result 112 , e.g., the digital signals D UP and D DOWN , based on a lock range, e.g., the range (f IN −f OS1 , f IN +f OS2 ).

In block 604 , the counter circuitry 118 adjusts the synchronizing signal 108 into the lock range, e.g., the range (f IN −f OS1 , f IN +f OS2 ), that is determined by the input frequency f IN of the input signal 110 .

In block 606 , the lock circuitry 116 controls the lock range according to the comparison result 112 . By way of example, if the comparison result 112 indicates the synchronizing frequency f OSC is outside the range (f IN −f OS1 , f IN +f OS2 ), the counter circuitry 118 adjusts the synchronizing frequency f OSC toward the input frequency f IN . When the synchronizing signal 108 is adjusted into the range (f IN −f OS1 , f IN +f OS2 ), the lock circuitry 116 changes the lock range to the range (f IN −f′ OS1 , f IN +f′ OS2 ). If a change occurs in the input frequency f IN such that the synchronizing frequency f OSC is outside the range (f IN −f′ OS1 , f IN +f′ OS2 ), the lock circuitry 116 changes the lock range to the range (f IN −f OS1 , f IN +f OS2 ) again.

Accordingly, embodiments according to the present invention provide signal synchronizing systems. The system can synchronize a synchronizing frequency with an input frequency by adjusting the synchronizing frequency into a lock range. The lock range can have a smaller width when the synchronizing frequency is outside the lock range, such that the synchronizing frequency is synchronized with the input frequency more accurately. In addition, the lock range can have a larger width when the synchronizing frequency is in the lock range, such that the synchronizing frequency is more stable. The signal synchronizing system can be used in many applications such as direct-current to direct-current (DC to DC) controllers in vehicle electronic systems.

While the foregoing description and drawings represent embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the principles of the present invention as defined in the accompanying claims. One skilled in the art will appreciate that the invention may be used with many modifications of form, structure, arrangement, proportions, materials, elements, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and their legal equivalents, and not limited to the foregoing description.