Cell interface

1. The Field of the Invention

The present invention relates a cell interface, comprises: anode of the first diode D 1 connected together cathode of the third diode D 3 form a first terminal, the anode of the fourth diode D 4 connected together cathode of the second diode D 2 form a second terminal, and the external positive voltage terminal VP connected between cathode of the first diode D 1 and anode of the third diode D 2 , and connected between anode of the third diode D 3 and cathode of the fourth diode D 4 form a third terminal, the first terminal connected to a positive voltage terminal of first cell E 1 , the second terminal connected to a positive voltage terminal of second cell E 2 , the third terminal is external positive voltage terminal VP, can be not occur loop current in cells parallel circuit.

2. Description of Related Art

FIG. 1 shows a schematic diagram of a prior art circuit. The first cell EA and second cell EB uses conventional parallel circuit. Such scheme comes with the following drawbacks:

1. When operation of charge of the first cell E 1 and second cell E 2 , can be occur loop current between the first cell E 1 and second cell E 2 , form a power consumption. 2. When operation of discharge of the first cell E 1 and second cell E 2 , can be occur loop current between the first cell E 1 and second cell E 2 , form a power consumption. 3. When operation of no load of the first cell E 1 and second cell E 2 , can be occur loop current between the first cell E 1 and second cell E 2 , form a power consumption.

In order to provide cell interface that may in charge or discharge can be not occur loop current in cells parallel circuit, the present invention is proposed the following:

The first object of the invention is to provide four diodes for a cell interface.

The second object of the invention is utilizing forward voltage of the diode to balance cells parallel circuit.

The third object of the invention is use a diode, comprises PN junction diode, or Schottky diode, or Zener diode, or Varactor diode, or Tunnel diode.

The fourth object of the invention is use for secondary cells.

FIG. 1 shows a schematic diagram of a prior art circuit.

FIG. 2 shows a schematic diagram of a cell interface to a first preferred embodiment of the present invention.

FIG. 3 shows a schematic diagram of a cell interface to a second preferred embodiment of the present invention.

FIG. 2 shows a schematic diagram of a cell interface 10 a first preferred embodiment of the present invention. The cell interface 10 includes four diodes. The diodes are a first diode D 1 , a second diode D 2 , a third diode D 3 , and a fourth diode D 4 . The first diode D 1 has an anode and a cathode, and the third diode D 3 has an anode and a cathode. The anode of the first diode D 1 is connected to the cathode of the third diode D 3 , and the cathode of the first diode D 1 is connected to the anode of the third diode D 3 . Wherein the anode of the first diode D 1 and the cathode of the third diode D 3 defined as a first terminal FT. Moreover, the second diode D 2 has an anode and a cathode, and the fourth diode D 4 has an anode and a cathode. The anode of the second diode D 2 is connected to the anode of the third diode and the cathode of the first diode and the fourth diode, and the anode of the fourth diode is connected to the cathode of the second diode D 2 . Wherein the anode of the fourth diode D 4 and the cathode of the second diode D 2 defined as a second terminal ST, and the cathode of the fourth diode D 4 , the anode of the second diode D 2 , the anode of the third diode D 3 , and the cathode of first diode D 1 defined as a third terminal TT. In the embodiment, a positive voltage terminal PVTE 1 of a first cell E 1 can connected to an electrode of a first diode D 1 and an electrode of a third diode D 3 , and a positive voltage terminal PVTE 2 of a second cell E 2 connected to an electrode of a fourth diode D 4 and an electrode of a second diode D 2 . Wherein the electrode of a first diode D 1 can be defined as an anode or a cathode, other diodes D 2 -D 4 are also same definition. In FIG. 2 , positive voltage terminal PVTE 1 of the first cell E 1 connected to an anode of the first diode D 1 and a cathode of the third diode D 3 , positive voltage terminal PVTE 2 of the second cell E 2 connected to anode of the fourth diode D 4 and cathode of the second diode D 2 ; the external positive voltage terminal VP connected between a cathode of the first diode D 1 and an anode of the second diode D 2 , and connected between an anode of the third diode D 3 and a cathode of the fourth diode D 4 form a third terminal TT of present invention; the anode of the first diode D 1 connected together a cathode of the third diode D 3 form a first terminal FT of present invention, and the first terminal FT is also connected with the voltage terminal of the first cell; the anode of the fourth diode D 4 connected together the cathode of the second diode D 2 form a second terminal ST of present invention, and the second terminal ST is also connected with voltage terminal of the seconds cell.

In FIG. 2 , the operation theorem of cell charge of present invention, while the positive voltage at external positive voltage terminal VP of charge device CD, the current of positive voltage passes through the third diode D 3 and first cell E 1 , and back to external negative voltage terminal VN, another current of positive voltage passes through the second diode D 2 and second cell E 2 , and back to external negative voltage terminal VN.

In FIG. 2 , the operation theorem of cell discharge of present invention, while a load LD connected between external positive voltage terminal VP and external negative voltage terminal VN, the current of first cell E 1 passes through the first diode D 1 , external positive voltage terminal VP, load LD and back to external negative voltage terminal VN, another current of second cell E 2 passes through the fourth diode D 4 , external positive voltage terminal VP, load LD and back to external negative voltage terminal VN.

In FIG. 2 , the anode of the first diode D 1 connected to positive voltage terminal PVTE 1 of first cell E 1 , cathode of the first diode D 1 connected to anode of the second diode D 2 , cathode of second diode D 2 connected to positive voltage terminal PVTE 2 of second cell E 2 , utilizing forward voltage of first diode D 1 and second diode D 2 , can be not occur loop current between the first cell E 1 and the second cell E 2 parallel circuit. In operation theorem: when the voltage of first cell E 1 under second cell E 2 or the voltage of first cell E 1 over second cell E 2 ; can be occur loop current between the first cell E 1 and the second cell E 2 parallel circuit, if the voltage of first cell E 1 over second cell E 2 is 1.4 volt, utilizing 0.7 volt forward voltage of first diode D 1 and 0.7 volt forward voltage of second diode D 2 is 1.4 volt to balance the voltage of first cell E 1 over second cell E 2 , can be not occur loop current between the first cell E 1 and the second cell E 2 parallel circuit; when the voltage of first cell E 1 under second cell E 2 or the voltage of first cell E 1 over second cell E 2 , can be occur loop current between the first cell E 1 and the second cell E 2 parallel circuit, if the voltage of second cell E 2 over first cell E 1 is 1.4 volt, utilizing 0.7 volt forward voltage of fourth diode D 4 and 0.7 volt forward voltage of third diode D 3 is 1.4 volt to balance the voltage of second cell E 2 over first cell E 1 , can be not occur loop current between the second cell E 2 and the first cell E 1 parallel circuit; when the voltage of second cell E 2 over first cell E 1 more 1.4 volt, least one of the third diode D 3 or least one of the fourth diode D 4 to balance the voltage of second cell E 2 ; when the voltage of first cell E 1 over second cell E 2 more 1.4 volt, least one of the first diode D 1 or least one of the second diode D 2 to balance the voltage of first cell E 1 ; when the voltage of first cell E 1 over second cell E 2 less than 1.4 volt, the first diode D 1 or the second diode D 2 may be use schottky diode to balance the voltage of first cell E 1 ; when the voltage of second cell E 2 over first cell E 1 less than 1.4 volt, the third diode D 3 or the fourth diode D 4 may be use schottky diode to balance the voltage of second cell E 2 ; the third terminal TT of present invention, can be connected to external electric circuit such as sense voltage input of voltage protection IC, and other protection circuit.

FIG. 3 shows a schematic diagram of a cell interface 10 to a second preferred embodiment of the present invention. In FIG. 3 , the negative voltage terminal NVTE 1 of the first cell E 1 connected to an anode of a first diode D 1 and a cathode of a third diode D 3 , negative voltage terminal NVTE 2 of the second cell E 2 connected to an anode of a fourth diode D 4 and a cathode of a second diode D 2 ; the external negative voltage terminal VN connected between a cathode of the first diode D 1 and an anode of the second diode D 2 , and connected between an anode of the third diode D 3 and a cathode of the fourth diode D 4 form a third terminal TT of present invention; the anode of the first diode D 1 connected together the cathode of the third diode D 3 form a first terminal FT of present invention, and a first terminal FT is also connected with the voltage terminal of the first cell; the anode of the fourth diode D 4 connected together cathode of the second diode D 2 form a second terminal ST of present invention.

In FIG. 3 , the operation theorem of cell charge of present invention, while the positive voltage at external positive voltage terminal VP of charge device CD, the current of positive voltage passes through the first cell E 1 and first diode D 1 , and back to external negative voltage terminal VN, another current of positive voltage passes through the second cell E 2 and fourth diode D 4 , and back to external negative voltage terminal VN.

In FIG. 3 , the operation theorem of cell discharge of present invention, while a load LD connected between external positive voltage terminal VP and external negative voltage terminal VN, the current of first cell E 1 passes through external positive voltage terminal VP, load LD, external negative voltage terminal VN, third diode D 3 and back to the first cell E 1 , another current of second cell E 2 passes through external positive voltage terminal VP, load LD, external negative voltage terminal VN and the second diode D 2 , and back to the second cell E 2 .

In FIG. 3 , the anode of the first diode D 1 connected to negative voltage terminal NVTE 1 of first cell E 1 , cathode of the first diode D 1 connected to anode of the second diode D 2 , cathode of second diode D 2 connected to negative voltage terminal NVTE 2 of second cell E 2 , utilizing forward voltage of first diode D 1 and second diode D 2 , can be not occur loop current between the first cell E 1 and the second cell E 2 parallel circuit. In operation theorem: when the voltage of first cell E 1 under second cell E 2 or the voltage of first cell E 1 over second cell E 2 , can be occur loop current between the first cell E 1 and the second cell E 2 parallel circuit, if the voltage of second cell E 2 over first cell E 1 is 1.4 volt, utilizing 0.7 volt forward voltage of first diode D 1 and 0.7 volt forward voltage of second diode D 2 is 1.4 volt to balance the voltage of second cell E 2 over first cell E 1 , can be not occur loop current between the first cell E 1 and the second cell E 2 parallel circuit; when the voltage of second cell E 2 under first cell E 1 or the voltage of second cell E 2 over first cell E 1 , can be occur loop current between the second cell E 2 and the first cell E 1 parallel circuit, if the voltage of first cell E 1 over second cell E 2 is 1.4 volt, utilizing 0.7 volt forward voltage of fourth diode D 4 and 0.7 volt forward voltage of third diode D 3 is 1.4 volt to balance the voltage of first cell E 1 over second cell E 2 , can be not occur loop current between the first cell E 1 and the second cell E 2 parallel circuit; when the voltage of first cell E 1 over second cell E 2 more 1.4 volt, least one of the third diode D 3 or least one of the fourth diode D 4 to balance the voltage of first cell E 1 ; when the voltage of second cell E 2 over first cell E 1 more 1.4 volt, least one of the first diode D 1 or least one of the second diode D 2 to balance the voltage of second cell E 2 ; when the voltage of second cell E 2 over first cell E 1 less than 1.4 volt, the first diode D 1 or the second diode D 2 may be use schottky diode to balance the voltage of second cell E 2 ; when the voltage of first cell E 1 over second cell E 2 less than 1.4 volt, the third diode D 3 or the fourth diode D 4 may be use schottky diode to balance the voltage of first cell E 1 ; the third terminal TT of present invention, can be connected to, external electric circuit such as sense voltage input of voltage protection IC, and other protection circuit.