Comparator and method with adjustable speed and power consumption

The present invention relates generally to integrated circuit comparators, and more particularly to ways of reducing average power consumption of high-speed comparators, and still more particularly to comparators including circuitry for adjusting comparator speed/propagation delay and comparator power consumption according to external system needs.

High speed (i.e., low signal propagation delay) of a comparator in a system may need to be adjusted according to the present operation requirements of the system. For example, the error comparator of a current mode DC-to-DC converter needs to be fast (e.g., with a propagation delay of 10-20 nanoseconds) when a power switch is ON, but the propagation delay may be 10-1000 times greater when the power switch is OFF. Reducing the power consumption of the comparator during time intervals when high speed (i.e., low propagation delay) is not needed may provide a substantial decrease in overall power consumption of a system containing comparators.

“Prior Art” FIG. 1 shows a comparator 1 that includes a differential input stage including N-channel input transistors M 0 and M 1 having their sources connected by conductor 2 to one terminal of a tail current source I TAIL , the other terminal of which is connected to V SS . The gates of transistors M 0 and M 1 are coupled to input signals V IN − and V IN + , respectively. The drain of input transistor M 0 is connected by conductor 3 to the drain and gate of a P-channel load transistor M 2 , the gate of a P-channel “hysteresis” transistor M 6 , the drain of a P-channel “hysteresis” transistor M 7 , and the gate of a P-channel current mirror output transistor M 4 . The sources of transistors M 2 , M 6 , M 7 , and M 4 are connected to V DD . Similarly, the drain of input transistor M 1 is connected by conductor 4 to the drain and gate of a P-channel load transistor M 3 , the gate of P-channel “hysteresis” transistor M 7 , the drain of P-channel “hysteresis” transistor M 6 , and the gate of a P-channel current mirror output transistor M 5 . The source of transistor M 5 is connected to V DD .

Diode-connected load transistor M 2 functions as the input transistor of a first current mirror that also includes output transistor M 4 , and diode-connected load transistor M 3 functions as the input transistor of a second current mirror that also includes output transistor M 5 . These two current mirrors form a second stage of comparator 1 . The drain of current mirror output transistor M 4 is connected by conductor 6 to the input of an output inverter or buffer 7 , the drain of a N-channel transistor M 8 , and the gate of a N-channel transistor M 9 . The sources of transistors M 8 and M 9 are connected to V SS . Similarly, the drain of current mirror output transistor M 5 is connected by conductor 5 to the drain of N-channel transistor M 9 and the gate of N-channel transistor M 8 . Current mirror output transistors M 4 and M 5 and transistors M 8 and M 9 form a latch circuit that operates to latch the desired state of comparator 1 . The circuitry including transistors M 8 and M 9 may be thought of as a third stage of comparator 1 .

Transistors M 6 and M 7 provide hysteresis for comparator 1 in response to local positive feedback for hysteresis provided by latch transistors M 8 and M 9 . For low current consumption, the third stage including latch transistors M 8 and M 9 latches the desired state of comparator 1 . As a result, the quiescent current (Iq) of comparator 1 is equal to the tail current I TAIL of the input differential input stage including input transistors M 0 and M 1 . (Comparator 1 in Prior Art FIG. 1 alternatively is sometimes implemented with transistors M 8 and M 9 functioning as a conventional current mirror utilized as a pair of load devices rather than as a latch circuit. The current mirror could include transistor M 9 connected as a current mirror input transistor and transistor M 8 connected as a current mirror output transistor. However, such a current mirror consumes twice as much current as the above described latch circuit M 8 /M 9 because the current mirror input transistor and current mirror output transistor each conducts an amount of current equal to the tail current I TAIL .)

The above-mentioned hysteresis may be provided to avoid multiple parasitic switching of comparator 1 . The input-referred hysteresis of comparator 1 is equal to 2V th ln(N), where V th =kT/q and N is the “area ratio” M 2 /M 6 =M 3 /M 7 , where M 2 /M 6 represents the ratio of the W/L ratio of transistor M 2 divided by the W/L ratio of transistor M 6 (where “W” and “L” are the channel-width and channel-length, respectively, of the field effect transistor). Differentially coupled MOS input transistors M 0 and M 1 may be operated in their weak inversion regions to improve the power-speed ratio of the differential input stage.

The speed of comparator 1 is directly proportional to its tail current I TAIL , or, stated differently, the propagation delay of comparator 1 is inversely proportional to I TAIL . Comparator 1 in FIG. 1 typically has a high power-to-speed ratio, and its propagation delay is dominated by the amount of time required to charge the parasitic input capacitance of the second stage with the current produced by differential input stage M 0 /M 1 , and therefore is inversely proportional to I TAIL . The parasitic input capacitance of the second stage mainly includes the gate capacitances of current mirror output transistors M 4 and M 5 .

The value of tail current I TAIL needs to be sufficiently high to ensure that the currents of current mirrors M 2 /M 4 and M 3 /M 5 are capable of switching the latch including transistors M 8 and M 9 . Consequently, the minimum value of I TAIL is undesirably large for some applications, and therefore the variable range of the quiescent current (Iq) of comparator 1 is undesirably small. I TAIL needs to be sufficiently large to cause current mirror input transistors M 2 or M 3 to mirror enough current through current mirror output transistor M 4 or M 5 , respectively, to overpower whichever of transistors M 8 and M 9 is presently turned on in order to cause the above mentioned latch circuit to switch to its opposite state. Transistors M 4 and M 5 therefore must be very large transistors in order to deliver that much current, and therefore must have large gate capacitances. The required large gate capacitances of current mirror output transistors M 4 and M 5 undesirably limit the achievable speed/propagation delay of comparator 1 of Prior Art FIG. 1 .

A certain amount of hysteresis usually is desirable in a comparator. One way to obtain hysteresis in comparator 1 is by means of above-mentioned transistors M 6 and M 7 . The amount of hysteresis is determined by the area ratio of transistors M 3 and M 7 , which is the same as the area ratio of transistors M 2 and M 6 . The amount of hysteresis is determined by positive feedback, so latch circuit M 8 /M 9 will not switch from its present state to its opposite state until the drain current of one of input transistors M 0 and M 1 increases sufficiently and the drain current of the other input transistor decreases sufficiently. Because of the positive feedback, latch circuit M 8 /M 9 can not switch its state until the ratio of the drain currents in transistors M 3 and M 7 is such that they can “overpower” the current mismatch caused by the positive feedback that is determined by the area ratio of transistors M 3 and M 7 . (The two foregoing ratios need to be kept nearly constant in order to prevent latch circuit M 8 /M 9 from switching states.)

For example, if V IN + increases relative to V IN − so that there is a particular amount of current in input transistor M 1 and the same amount of current flows in current mirror output transistor M 3 , it means that input transistor M 0 provides less current than hysteresis transistor M 7 (assuming hysteresis transistor M 7 is matched to current mirror reference transistor M 3 ). Comparator 1 will not able to switch to its opposite state because transistor M 7 in effect short-circuits the gate of current mirror input transistor M 2 to V DD . Therefore, there is no current in transistor M 6 , the current flow being through transistors M 3 and M 7 . Consequently, latch circuit M 8 /M 9 can switch state only if the amount of current in transistor M 0 exceeds the current in transistor M 7 . Transistors M 3 and M 7 may be ratioed so as to cause more current to flow through input transistor M 0 , thereby turning on current mirror reference transistor M 2 by increasing the ratio of the current in transistor M 0 to the current in transistor M 1 . This is because the ratio of the current in current mirror reference transistor M 3 to the current in hysteresis transistor M 7 , which also is the ratio of the current in current mirror reference transistor M 2 to the current in hysteresis transistor M 6 , determines the ratio of the currents in input transistors M 0 and M 1 at the times at which switching of latch M 8 /M 9 occurs, thereby resulting in input-related voltage hysteresis in comparator 1 .

It would be highly desirable to keep current mirror output transistors M 4 and M 5 small to minimize the amount of capacitance that must be charged proportionately to tail current I TAIL and thereby achieve a low comparator propagation delay while also maintaining a low power consumption of the comparator, but unfortunately comparator 1 of Prior Art FIG. 1 does not permit this to be accomplished. Comparator 1 of Prior Art FIG. 1 inherently requires that current mirror output transistors M 4 and M 5 be able to generate relatively large currents in order to switch the state of latch M 4 ,M 5 . Consequently, a relatively large minimum value of I TAIL is required, and therefore comparator 1 consumes a relatively large amount of current and power.

Thus, there is an unmet need for a comparator capable of “on the fly” adjustment of both comparator speed/propagation delay and comparator power consumption according to system needs.

There also is an unmet need for a comparator capable of switching and latching its state without requiring a large tail current source in a differential input stage of the comparator.

There also is an unmet need for a comparator which is capable of “on the fly” adjustment of both comparator speed/propagation delay and comparator power consumption according to system needs and which also is capable of switching and latching the state of the comparator without requiring a large tail current source in a differential input stage of the comparator.

There also is an unmet need for a comparator configuration that is optimal or near-optimal for a wide range of applications.

There also is an unmet need for a comparator configuration which requires very little design effort to adapt it for a wide range of applications.

It is an object of the invention to provide a comparator that is capable of high-speed operation when needed and which also consumes very little power when high-speed operation is not required.

It is another object of the invention to provide a comparator and method capable of “on the fly” adjustment of both comparator speed/propagation delay and comparator power consumption according to system needs during normal operation.

It is another object of the invention to provide a comparator capable of switching and latching its state without requiring a large tail current source in a differential input stage of the comparator.

It is another object of the invention to provide a comparator which is capable of “on the fly” adjustment of both comparator speed/propagation delay and comparator power consumption according to system needs and which also is capable of switching the state of the comparator without requiring a large tail current source in a differential input stage of the comparator.

It is another object of the invention to provide a comparator configuration that is optimal or near-optimal for a wide range of applications.

It is another object of the invention to provide a comparator configuration which requires very little design effort to adapt it for a wide range of applications.

Briefly described, and in accordance with one embodiment, the present invention provides a comparator ( 10 ) including a first input transistor (M 0 ) having a drain coupled to a gate and drain of a first diode-connected transistor (M 2 ) and a gate of a first current mirror output transistor (M 4 ), and a second input transistor (M 1 ) having a drain coupled to a gate and drain of a second diode-connected transistor (M 3 ) and a gate of a second current mirror output transistor (M 5 ). Sources of the first and second current mirror output transistors are connected to a supply voltage (V DD ). Gates of the first and second input transistors are coupled to first (V IN − ) and second (V IN + ) input signals, respectively. The sources of the first and second diode-connected transistors are coupled to the drains of the first and second current mirror output transistors, respectively. A latch circuit (M 8 ,M 9 ) is coupled to the drains of the first and second current mirror output transistors.

In one embodiment, the invention provides a comparator ( 10 ) including an input stage (M 0 /M 1 ) including first (M 0 ) and second (M 1 ) input transistors, a first current mirror (M 2 /M 4 ) coupled to the first input transistor (M 0 ), and a second current mirror (M 3 /M 5 ) coupled to the second input transistor (M 1 ). The first current mirror (M 2 /M 4 ) includes a first diode-connected transistor (M 2 ) and a first current mirror output transistor (M 4 ), and the second current mirror (M 3 ,M 5 ) includes a second diode-connected transistor (M 3 ) and a second current mirror output transistor (M 5 ). Each of the first (M 0 ) and second (M 1 ) input transistors, the first (M 2 ) and second (M 3 ) diode-connected transistors, and the first (M 4 ) and second (M 5 ) current mirror output transistors has a source, a drain, and a gate. The sources of the first (M 0 ) and second (M 1 ) input transistors are coupled to a first reference voltage (V SS ). The gates of the first (M 0 ) and second (M 1 ) input transistors are coupled to first (V IN − ) and second (V IN +) input signals, respectively. The drain of the first input transistor (M 0 ) is coupled to the drain and the gate of the first diode-connected transistor (M 2 ) and the gate of the first current mirror output transistor (M 4 ), and the drain of the second input transistor (M 1 ) is coupled to the drain and the gate of the second diode-connected transistor (M 3 ) and the gate of the second current mirror output transistor (M 5 ). The sources of the first (M 4 ) and second (M 5 ) current mirror output transistors are coupled to a second reference voltage (V DD ). The sources of the first (M 2 ) and second (M 3 ) diode-connected transistors are coupled to the drains of the first (M 4 ) and second (M 5 ) current mirror output transistors, respectively. A latch circuit (M 8 ,M 9 ) is coupled to the drains of the first (M 4 ) and second (M 5 ) current mirror output transistors.

In a described embodiment, the input stage (M 0 ,M 1 ) is a differential input stage including a current source (I TAIL ). The latch circuit includes a first latch transistor (M 8 ) having a drain coupled to the drain of the first current mirror output transistor (M 4 ), a source coupled to the first reference voltage (V SS ), and a gate coupled to the drain of the second current mirror output transistor (M 5 ). The latch circuit also includes a second latch transistor (M 9 ) having a drain coupled to the drain of the second current mirror output transistor (M 5 ), a source coupled to the first reference voltage (V SS ), and a gate coupled to the drain of the first current mirror output transistor (M 4 ).

In one embodiment, the comparator ( 10 ) includes a first hysteresis transistor (M 6 ) having a source coupled to the second reference voltage (V DD ), a gate coupled to the gate of the first diode-connected transistor (M 2 ), and a drain coupled to the drain of the second input transistor (M 1 ), and also includes a second hysteresis transistor (M 7 ) having a source coupled to the second reference voltage (V DD ), a gate coupled to the gate of the second diode-connected transistor (M 3 ), and a drain coupled to the drain of the first input transistor (M 0 ).

In a described embodiment, the current source (I TAIL ) has a value which results in a predetermined delay of the comparator ( 10 ). The first (M 4 ) and second (M 5 ) current mirror output transistors have a channel-width-to-channel-length ratio that is substantially less than a channel-width-to-channel-length ratio of the first (M 0 ) and second (M 1 ) input transistors. The first (M 0 ) and second (M 1 ) input transistors, the first (M 2 ) and second (M 3 ) diode-connected transistors, and the first (M 4 ) and second (M 5 ) current mirror output transistors have channel-width-to-channel-length ratios selected to ensure switching of the latch circuit when the current source (I TAIL ) has a predetermined low value.

In a described embodiment, the first diode-connected transistor (M 2 ) becomes reverse biased during a part of a comparator switching cycle so as to prevent it from limiting the gate-to-source voltage of the first current mirror output transistor (M 4 ), and the second diode-connected transistor (M 3 ) becomes reverse biased during a part of another comparator switching cycle so as to prevent it from limiting the gate-to-source voltage of the second current mirror output transistor (M 5 ).

In a described embodiment, first (M 0 ) and second (M 1 ) input transistors are N-channel transistors, wherein the first (M 2 ) and second (M 3 ) diode-connected transistors, the first (M 4 ) and second (M 5 ) current mirror output transistors, and the first (M 6 ) and second (M 7 ) hysteresis transistors are P-channel transistors. The first (M 8 ) and second (M 9 ) latch transistors are N-channel transistors.

In a described embodiment, the drain of the first input transistor (M 0 ) is directly coupled to the drain of the first diode-connected transistor (M 2 ), and the drain of the second input transistor (M 1 ) is directly coupled to the drain of the second diode-connected transistor (M 3 ).

In one embodiment, the invention provides a method for reducing power consumption in a comparator ( 10 ) including an input stage (M 0 /M 1 ) having first (M 0 ) and second (M 1 ) input transistors, the method including coupling sources of the first (M 0 ) and second (M 1 ) input transistors to a first reference voltage (V SS ); coupling a gate of each of the first (M 0 ) and second (M 1 ) input transistors to first (V IN − ) and second (V IN + ) input signals, respectively; coupling a drain of the first input transistor (M 0 ) to a drain and a gate of a first diode-connected transistor (M 2 ) and to a gate of a first current mirror output transistor (M 4 ), and coupling a drain of the second input transistor (M 1 ) to a drain and a gate of a second diode-connected transistor (M 3 ) and to a gate of a second current mirror output transistor (M 5 ); coupling sources of the first (M 4 ) and second (M 5 ) current mirror output transistors to a second reference voltage (V DD ); coupling sources of the first (M 2 ) and second (M 3 ) diode-connected transistors to drains of the first (M 4 ) and second (M 5 ) current mirror output transistors, respectively; and coupling the drains of the first (M 4 ) and second (M 5 ) current mirror output transistors to a latch circuit (M 8 ,M 9 ).

In one embodiment, the method includes reverse biasing the first (M 2 ) or second (M 3 ) diode-connected transistor during part of a comparator switching cycle so as to prevent that diode-connected transistor from limiting a gate-to-source voltage of the first (M 4 ) or second (M 5 ) current mirror output transistor, respectively.

In one embodiment, the method includes coupling a drain of a first latch transistor (M 8 ) in the latch circuit (M 8 ,M 9 ) to the drain of the first current mirror output transistor (M 4 ), coupling a source of the first latch transistor (M 8 ) to the first reference voltage (V SS ), and coupling a gate of the first latch transistor (M 8 ) to the drain of the second current mirror output transistor (M 5 ), the method also including coupling a drain of a second latch transistor (M 9 ) in the latch circuit (M 8 ,M 9 ) to the drain of the second current mirror output transistor (M 5 ), coupling a source of the second latch transistor (M 9 ) to the first reference voltage (V SS ), and coupling a gate of the second latch transistor (M 9 ) to the drain of the first current mirror output transistor (M 4 ).

In one embodiment, the method includes providing channel-width-to-channel-length ratios of the first (M 0 ) and second (M 1 ) input transistors, the first (M 2 ) and second (M 3 ) diode-connected transistors, and the first (M 4 ) and second (M 5 ) current mirror output transistors so as to ensure switching of the first (M 8 ) and second (M 9 ) latch transistors when the current source (I TAIL ) has a predetermined low value.

In one embodiment, the comparator ( 10 ) includes a first hysteresis transistor (M 6 ) having a source coupled to a second reference voltage (V DD ), a gate coupled to the gate of the first diode-connected transistor (M 2 ), and a drain coupled to the drain of the second input transistor (M 1 ), and also includes a second hysteresis transistor (M 7 ) having a source coupled to the second reference voltage (V DD ), a gate coupled to the gate of the second diode-connected transistor (M 3 ), and a drain coupled to the drain of the first input transistor (M 0 ), wherein the method includes providing a channel-width-to-channel-length ratio of the first (M 6 ) and second (M 7 ) hysteresis transistors so as to provide a predetermined amount of hysteresis for the comparator ( 10 ).

In one embodiment, the method includes coupling the drain of the first input transistor (M 0 ) directly to the drain and the gate of the first diode-connected transistor (M 2 ) and to the gate of the first current mirror output transistor (M 4 ), and coupling the drain of the second input transistor (M 1 ) directly to the drain and the gate of the second diode-connected transistor (M 3 ) and to the gate of the second current mirror output transistor (M 5 ).

In one embodiment, the invention provides a comparator ( 10 ) including circuitry for reducing power consumption, including a differential input stage (M 0 /M 1 ) having first (M 0 ) and second (M 1 ) input transistors and a current source (I TAIL ), a gate of each of the first (M 0 ) and second (M 1 ) input transistors being coupled to first (V IN − ) and second (V IN + ) input signals, respectively; means ( 2 ) for coupling sources of the first (M 0 ) and second (M 1 ) input transistors to the current source (I TAIL ); means ( 3 ) for coupling a drain of the first input transistor (M 0 ) to a drain and a gate of a first diode-connected transistor (M 2 ) and to a gate of a first current mirror output transistor (M 4 ); means ( 4 ) for coupling a drain of the second input transistor (M 1 ) to a drain and a gate of a second diode-connected transistor (M 3 ) and to a gate of a second current mirror output transistor (M 5 ); means for coupling sources of the first (M 4 ) and second (M 5 ) current mirror output transistors to a first reference voltage (V DD ); means ( 3 , 4 ) for coupling sources of the first (M 2 ) and second (M 3 ) diode-connected transistors to the drains of the first (M 4 ) and second (M 5 ) current mirror output transistors, respectively; and means ( 5 , 6 ) for coupling the drains of the first (M 4 ) and second (M 5 ) current mirror output transistors to a latch circuit ( 15 ).

FIG. 1 is a schematic diagram of a conventional high-speed integrated circuit comparator.

FIG. 2 is a schematic diagram of a high speed comparator in accordance with the present invention.

FIG. 2A is a replica of FIG. 2 including notations to indicate the comparator circuit operating configuration during waveform segments A 1 of the V IN − waveform and B 1 of the V IN + waveform in FIG. 3 .

FIG. 2B is a replica of FIG. 2 including notations to indicate the comparator circuit operating configuration during waveform segments A 3 of the V IN − waveform and B 3 of the V IN + waveform in FIG. 3 .

FIG. 3 is a timing diagram showing several simulated waveforms of the comparator of FIG. 2 .

FIG. 2 shows a high speed comparator 10 including an input stage with N-channel input transistors M 0 and M 1 having their sources connected by conductor 2 to one terminal of a current source I TAIL , the other terminal of which is connected to V SS . The gates of transistors M 0 and M 1 are coupled to input signals V In − and V IN + , respectively. The drain of input transistor M 0 is connected by conductor 3 to the drain and gate of a diode-connected P-channel “current mirror reference transistor” M 2 , the gate of a P-channel “hysteresis” transistor M 6 , the drain of a P-channel “hysteresis” transistor M 7 , and the gate of a P-channel current mirror output transistor M 4 . The source of diode-connected current mirror reference transistor M 2 is connected to a conductor 6 (instead of to V DD as in Prior Art FIG. 1 ). The sources of transistors M 6 and M 7 are connected to V DD . Similarly, the drain of input transistor M 1 is connected by conductor 4 to the drain and gate of a diode-connected P-channel current mirror reference transistor M 3 , the gate of P-channel “hysteresis” transistor M 7 , the drain of P-channel “hysteresis” transistor M 6 , and the gate of a P-channel current mirror output transistor M 5 . The source of current mirror reference transistor M 3 is connected to a conductor 5 (instead of to V DD as in Prior Art FIG. 1 ). The source of transistor M 5 is connected to V DD . The voltages V 3 , V 4 , V 5 , and V 6 appear on conductors 3 , 4 , 5 , and 6 , respectively.

Current mirror output transistors M 4 and M 5 may be very small, with sizes almost as small as minimum-size transistors for the integrated circuit manufacturing process being utilized. The small sizes of current mirror output transistors M 4 and M 5 result in them having low gate capacitances which can be driven at high speed with very small values of tail current I TAIL , so as to provide very low signal propagation delay of comparator 10 .

Current mirror reference transistor M 2 functions part of the time as the input transistor of a current mirror that also includes output transistor M 4 , and diode-connected current mirror reference transistor M 3 functions part of the time as the input transistor of another current mirror that also includes output transistor M 5 . At other times, diode-connected current mirror reference transistors M 2 and M 3 are reverse biased, and therefore are functionally disconnected from conductors 6 and 5 , respectively. The drain of current mirror output transistor M 4 is connected by conductor 6 to the input of an output inverter or buffer 7 , the drain of a N-channel latch transistor M 8 , and the gate of a N-channel latch transistor M 9 . The sources of latch transistors M 8 and M 9 are connected to V SS . Similarly, the drain of current mirror output transistor M 5 is connected by conductor 5 to the drain of latch transistor M 9 and the gate of latch transistor M 8 . Current mirror output transistors M 4 and M 5 , along with latch transistors M 8 and M 9 , form a latch circuit M 8 /M 9 .

Although input transistors M 0 and M 1 and tail current source I TAIL are illustrated as a differential input stage, a different kind of input stage could be used. For example, the sources of the input transistors could be connected to V SS . However, in this case the range of the input voltages V IN + and V IN − would be quite limited. It should be understood that different kinds of coupling of input transistors M 0 and M 1 to diode-connected transistors M 2 and M 3 , respectively, could be used, for example to provide more voltage “headroom”.

Hysteresis transistor M 6 creates positive feedback, the amount of which depends on the ratio of the effective W/L ratio of diode-connected transistor M 2 in series with current mirror output transistor M 4 to the W/L ratio of hysteresis transistor M 6 . The larger the W/L ratio of hysteresis transistor M 6 , the larger the percentage of hysteresis of comparator circuit 10 will be. The W/L ratio of hysteresis transistor M 6 may be less than, equal to, or greater than that of diode-connected M 2 . Similarly, hysteresis transistor M 7 creates positive feedback, the amount of which depends on the ratio of the effective W/L ratio of diode-connected transistor M 3 in series with current mirror output transistor M 5 to the W/L ratio of hysteresis transistor M 7 .

The unacceptably large minimum current consumption limitation of comparator 1 in Prior Art FIG. 1 is avoided by comparator circuit 10 in FIG. 2 . This is achieved by the connecting of the sources of current mirror reference transistors M 2 and M 3 to the outputs of the two current mirrors M 2 /M 4 and M 3 /M 5 , respectively. This prevents negative feedback around each current mirror from occurring until latch circuit M 8 /M 9 switches state and current mirror output transistor M 4 or M 5 starts operating in its triode region, in which case current mirror reference transistor M 2 and current mirror output transistor M 4 in effect form a diode-connected, long-channel transistor.

Consequently, the gate-source voltages of current mirror output transistors M 4 and M 5 during a comparator switching operation are not limited by the diode-connected current mirror reference transistors, as is the case for comparator 1 of Prior Art FIG. 1 . Instead, in comparator 10 of FIG. 2 the gate-source voltages of current mirror output transistors M 4 and M 5 can be as high as needed to provide suitably large currents in current mirror output transistors M 4 and M 5 to switch the state of latch circuit M 8 /M 9 . In one case, if transistors M 8 and M 9 initially are on and off, respectively, input transistor M 0 can pull the voltage V 3 on conductor 3 low enough to turn current mirror output transistor M 4 fully on. Then transistor M 4 can deliver a sufficiently large current to overcome or exceed the current in latch transistor M 8 during its “on” condition and also turn latch transistor M 9 on, thereby switching comparator 10 to its opposite state. Similarly, if comparator 10 initially is in its opposite state in which transistors M 8 and M 9 initially are off and on, respectively, input transistor M 1 can pull the voltage V 4 on conductor 4 low enough to turn current mirror output transistor M 5 fully on. Then transistor M 5 can deliver a sufficiently large current to overcome or exceed the “on” condition of latch transistor M 9 and turn latch transistor M 8 on, thereby switching comparator 10 to its opposite state.

Following is an example of the operation of latch circuit 10 in FIG. 2 . If latch transistor M 8 is on and latch transistor M 9 is off, and if V IN − suddenly becomes less than V IN + and transistor M 4 is in its triode region of operation (so that it functions as a resistor), then diode-connected transistor M 2 and current mirror output transistor M 4 are connected in series (because the drain of transistor M 4 is connected to the source of current mirror reference transistor M 2 and their gates are connected together). The current in input transistor M 0 flows through the drain and source of diode-connected transistor M 2 and through the drain and source of current mirror output transistor M 4 . Diode-connected transistor M 2 initially functions as a current mirror reference transistor and substantially limits the gate-to-source voltage of current mirror output transistor M 4 . However, at the instant the drain voltage V 6 of current mirror output transistor M 4 becomes significantly less than V DD , diode-connected transistor M 2 becomes functionally disconnected from the gate of current mirror output transistor M 4 and consequently no longer limits the gate-to-source voltage of transistor M 4 . Therefore, input transistor M 0 causes V 3 to go to a sufficiently low level to fully turn on current mirror output transistor M 4 so it can deliver a current substantially larger than the current in latch transistor M 8 , which presently is turned on. This causes the voltage V 6 on conductor 6 to rapidly rise and turn on latch transistor M 9 , thereby switching latch circuit M 8 /M 9 , and hence comparator 10 , to its opposite state.

FIG. 2A provides additional notations to FIG. 2 to indicate the operation of comparator circuit 10 during waveform segment A 1 of the V IN − waveform and segment B 1 of the V IN + waveform in FIG. 3 if latch transistor M 8 is initially ON and latch transistor M 9 is initially OFF. Referring to FIGS. 2A and 3 , during segments A 1 and B 1 , V IN − is at a high level and input transistor M 0 is ON. V IN + is at a low level and input transistor M 1 is OFF or nearly OFF. Therefore, tail current I TAIL flows in input transistor M 0 , causing V 3 to be one MOS threshold voltage V TH below V 6 . V 3 is at a sufficiently low level to keep P-channel diode-connected transistor M 2 , hysteresis transistor M 6 , and current mirror output transistor M 4 in their ON conditions. V IN + is at a relatively low level, so very little, if any, current flows through input transistor M 1 . Hysteresis transistor M 6 is ON and maintains its drain voltage V 4 at a sufficiently high level to keep current mirror output transistor M 5 sufficiently ON to cause V 5 to be at a sufficiently high level to keep latch transistor M 8 ON. This keeps V 6 at a sufficiently low level to keep latch transistor M 9 OFF. Current mirror output transistor M 4 is sufficiently ON to cause V 6 to be at a sufficiently high level to keep diode-connected transistor M 2 in its ON condition.

When segment A 2 of the V IN − waveform and segment B 2 of the V IN + waveform in FIG. 3 occur, latch transistor M 8 is switched from its initial ON state to its OFF state, and latch transistor M 9 is switched from its initial OFF state to its ON state. V IN − going high as mentioned above causes V 3 to go low. This turns current mirror output transistor M 4 ON harder, causing V 6 to increase enough to turn latch transistor M 9 ON. That causes V 5 to go sufficiently low to turn latch transistor M 8 OFF. It should be noted that during this switching operation, diode-connected transistor M 2 goes into its OFF condition and therefore does not limit the gate-to-source voltage of current mirror output transistor M 4 . That is what allows current mirror output transistor M 4 to be able to deliver enough current to increase V 6 sufficiently to turn on latch transistor M 9 .

Similarly, FIG. 2B provides appropriate additional notations to FIG. 2 to indicate the operation of comparator circuit 10 during waveform segment A 3 of the V IN − waveform and segment B 3 of the V IN + waveform in FIG. 3 if latch transistor M 8 is initially OFF and latch transistor M 9 is initially ON. Referring to FIGS. 2B and 3 , during segments A 3 and B 3 , V IN − is at a low level and transistor M 0 is OFF or nearly OFF. V IN + is at a high level and input transistor M 1 is ON. Therefore, tail current I TAIL flows in input transistor M 1 , causing V 4 to be a threshold voltage V TH lower than V 5 . V 4 is at a sufficiently low level to keep diode-connected transistor M 3 , hysteresis transistor M 7 , and current mirror output transistor M 4 ON. V IN − is at a relatively low level, so very little, if any, current flows through input transistor M 0 . Hysteresis transistor M 7 is ON and maintains its drain voltage V 3 at a sufficiently high level to keep current mirror output transistor M 4 sufficiently ON to cause V 4 to be at a sufficiently high level to keep latch transistor M 9 ON. This keeps V 5 at a sufficiently low level to keep latch transistor M 8 OFF. Current mirror output transistor M 5 is sufficiently ON to cause V 5 to be at a sufficiently high level to keep diode-connected transistor M 3 in its ON condition.

When segment A 4 of the V IN − waveform and segment B 4 of the V IN + waveform in FIG. 3 occur, latch transistor M 9 is switched from its initial ON state to its OFF state, and latch transistor M 8 is switched from its initial OFF state to its ON state. V IN + going high causes V 4 to go low. This turns current mirror output transistor M 5 ON harder, causing V 5 to increase enough to turn latch transistor M 8 ON. That causes V 6 to go sufficiently low to turn latch transistor M 9 OFF. It should be noted that during this switching operation, diode-connected transistor M 3 goes into its OFF condition and therefore does not limit the gate-to-source voltage of current mirror output transistor M 5 . That is what allows current mirror output transistor M 5 to be able to deliver enough current to increase V 5 sufficiently to turn on latch transistor M 8 .

Thus, the times at which diode-connected transistors M 2 and M 3 are turned on and off depend on the states of latch transistors M 8 and M 9 , that is, on whether V 5 or V 6 is higher. During any switching of the states of latch transistors M 8 and M 9 to their opposite states, one or the other of diode-connected transistors M 2 or M 3 becomes reverse biased.

The hysteresis of comparator 10 in FIG. 2 is determined in accordance with the previously mentioned formula 2V TH ln(N) for comparator 1 in Prior Art FIG. 1 . For comparator 10 of FIG. 2 , however, N is the area ratio of the W/L of current mirror reference transistor M 2 divided by an effective W/L ratio of the series connection of transistors M 6 and M 4 . Also, N is the area ratio of the W/L of current mirror reference transistor M 3 divided by an effective W/L ratio of the series connection of transistors M 7 and M 5 .

The value of tail current I TAIL mainly affects the speed or propagation delay of comparator 10 , and is not important with respect to its functionality. Comparator 10 of FIG. 2 allows the value of tail current I TAIL to be increased by as much as a factor of roughly 1000 times greater than its minimum value in order to decrease the comparator propagation delay. In one implementation, the value of tail current I TAIL can be from 2 nanoamperes to 5 microamperes.

Latch circuit M 8 /M 9 can always switch its stored state reliably, and the value of I TAIL nevertheless can be adjusted whenever needed to provide very fast, short propagation delays, and also can be adjusted whenever needed to provide very low power consumption during time intervals in which large comparator propagation delays are acceptable. Comparator 10 of FIG. 2 requires large amounts of power only when a system in which comparator 10 is included requires very short comparator propagation delay. During other time intervals in which high-speed comparator performance is not required, comparator 10 consumes much less power. For example, if the error amplifier output in a buck converter is small, a comparator 10 therein could have a very long propagation delay during which a tail current I TAIL of 2 or 3 nanoamperes may be adequate voltage may be adequate. However, a very short time later the error amplifier output might be much larger and the same comparator may need to have a much shorter propagation delay, e.g. 5 to 10 nanoseconds, which would require a much larger value of tail current I TAIL .

While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention.