Printed circuit board

1. Technical Field

The present disclosure relates to a printed circuit board (PCB).

2. Description of Related Art

Referring to FIG. 3 , a conventional PCB is shown. The PCB includes first to fourth layers, and dielectric materials 1 respectively sandwiched between every two adjacent layers. The layers comprise conductive copper pathways that remain after etching copper foils and the conductive copper pathways are called transmission lines or traces. The dielectric material 1 insulates two adjacent etched copper layers from each other. A power supply 5 and a trace 6 are arranged on the first layer. A trace 7 is arranged in the third layer. An electronic component 8 is arranged on the fourth layer. Four vertical interconnection accesses (vias) 2 a , 2 b , 3 a , and 3 b extend through the PCB. The vias 2 a and 2 b are close to the power supply 5 . The vias 3 a and 3 b are arranged on a side of the via 2 a away from the power supply 5 . The trace 6 is electrically connected to the power supply 5 , and the vias 2 a , 2 b , 3 a , and 3 b . The trace 7 is electrically connected to the vias 2 a , 2 b , 3 a , and 3 b.

As arrows show in FIG. 3 , when the power supply 5 supplies power to the electronic component 8 , a first part of the current flows to the electronic component 8 through the trace 6 , and the vias 3 a and 3 b , and a second part of the current flows to the electronic component 8 through the vias 2 a , 2 b , and the trace 7 .

According to PCB manufacturing procedures, impedance of the traces arranged on the top layer (the first layer of the PCB) or the bottom layer (the fourth layer of the PCB) is greater than impedance of the traces arranged on an inner layer (the second layer or the third layer of the PCB). As a result, the impedance of a transmission path for the part of the current flowing through the vias 2 a and 3 a is least. Because the current flows to the electronic component 8 through a path with the least resistance, the current passing through the via 2 a is too high, as indicate in the following table 1:

The resulting high temperature created may make the PCB unstable or may even damage the PCB.

Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a sectional view of a first embodiment of a printed circuit board.

FIG. 2 is a top plan view of a second embodiment of a printed circuit board.

FIG. 3 is a sectional view of a conventional printed circuit board.

The disclosure, including the accompanying drawings, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to FIG. 1 , an exemplary embodiment of a printed circuit board (PCB) includes first to fourth layers 10 , 20 , 30 , and 40 . Dielectric materials 11 respectively sandwiched between adjacent first to fourth layers 10 , 20 , 30 , and 40 . The layers include conductive copper pathways that remain after etching copper foils and the conductive copper pathways are called transmission lines or traces. The dielectric material 11 insulates two adjacent etched copper layers from each other.

A power supply 50 and a trace 100 electrically connected to the power supply 50 are arranged on the first layer 10 . An electronic component 80 is arranged on the fourth layer 40 . A via 60 extends through the first to fourth layers 10 , 20 , 30 , and 40 , and is electrically connected to the first layer 10 and the fourth layer 40 . The via 60 is insulated from the second layer 20 and the third layer 30 . The via 60 is further electrically connected to the trace 100 .

Two vias 62 and 63 extend through the first to fourth layers 10 , 20 , 30 , and 40 , and are electrically connected to the electronic component 80 arranged on the fourth layer 40 . The trace 100 is electrically connected to the vias 62 and 63 .

A via 64 extends through the first layer 10 and the second layer 20 . The via 64 is electrically connected to the trace 100 . A via 65 extends through the second layer 20 , the third layer 30 , and the fourth layer 40 , and is insulated from the third layer 30 . Two vias 66 and 67 extend through the third layer 30 and the fourth layer 40 .

A trace 200 is arranged on the second layer 20 , and electrically connects the vias 64 and 65 together. Two traces 300 and 310 are arranged on the third layer 30 . The trace 300 is electrically connected to the vias 67 , 62 , and 63 . The trace 310 electrically connects the trace 300 and the via 66 together. Two traces 400 and 410 are arranged on the fourth layer 40 . The trace 400 electrically connects the vias 60 and 67 together. The trace 410 electrically connects the vias 65 and 66 together.

In the embodiment, the via 60 is close to the power supply 50 . The via 64 is arranged between the via 60 and the power supply 50 . The via 66 is arranged below the via 64 . The via 65 is arranged between the via 64 and the power supply 50 . The via 67 is arranged at a side of the via 60 away from the power supply 50 . The vias 62 and 63 are arranged on a side of the via 67 away from the via 60 .

Following the arrows shown in FIG. 1 , when the power supply 50 supplies power to the electronic component 80 , a first part of the current of the power supply 50 flows to the electronic component 80 through the trace 100 , and the vias 62 and 63 . A second part of the current of the power supply 50 flows to the electronic component 80 through the via 60 , the trace 400 , the via 67 , and the trace 300 in that order. A third part of the current of the power supply 50 flows to the electronic component 80 through the via 64 , the trace 200 , the via 65 , the trace 410 , the via 66 , and the traces 310 and 300 in that order.

According to manufacture procedure of the PCB, impedance of the traces arranged on the top layer (the first layer 10 in the embodiment) or the bottom layer (the fourth layer 40 in the embodiment) is greater than impedance of the traces arranged on the inner layer (the second layer 20 or the third layer 30 in the embodiment). As a result, a difference between the impedance of a transmission path for the second part of the current and the impedance of a transmission path for the third part of the current of the power supply 50 is decreased. As a result, the currents passing through the two transmission paths are almost the same, thus avoiding too much of an imbalance in current through the vias.

Referring to Table 2, current values through the vias 60 and 64 in FIG. 1 are shown.

As shown in Table 2, a difference between current values through the vias 64 and 60 in FIG. 1 is decreased when compared with table 1.

Referring to FIG. 2 , in another exemplary embodiment of a PCB, a first row of vias replace the via 60 in FIG. 1 , a second row of vias replace the via 64 , a third row of vias replace the via 65 , a fourth row of vias replace the via 66 , and a fifth row of vias replace the via 67 . In the embodiment, the first row of vias include five vias 60 a - 60 e as shown in FIG. 2 . The second row of vias include five vias 64 a - 64 e , the third row of vias include five vias, the fourth row of vias include five vias, and the fifth row of vias include five vias. Five vias in each row of vias are arranged as the five vias 60 a - 60 e . In other embodiments, a distance between the via 60 a and the power supply 50 equals to a distance between the via 60 b and the power supply 50 . A distance between the via 64 a and the power supply 50 equals to a distance between the via 64 b and the power supply 50 . As a result, the difference between the current flows each via is decreased.

Each of the first row of vias 60 a - 60 e extends through the first to fourth layers 10 , 20 , 30 , and 40 , and are electrically connected to the first layer 10 and the fourth layer 40 . Each of the second row of vias 64 a - 64 e extends through the first layer 10 and the second layer 20 . Each of the third row of vias extends through the second layer 20 , the third layer 30 , and the fourth layer 40 , and is insulated from the third layer 30 . Each of the fourth and fifth rows of vias extends through the third layer 30 and the fourth layer 40 .

A first row of traces electrically connect the power supply 50 and the first row of vias 60 a - 60 e , and the second row of vias 64 a - 64 e . In other words, a first trace in the first row of traces is connected to the power supply 50 , the vias 60 a , 64 a , 62 , and 63 . A second trace in the first row of traces is connected to the power supply 50 , the vias 60 b , 64 b , 62 , and 63 . A third trace in the first row of traces is connected to the power supply 50 , the vias 60 c , 64 c , 62 , and 63 . A fourth trace in the first row of traces is connected to the power supply 50 , the vias 60 d , 64 d , 62 , and 63 . A fifth trace in the row of traces is connected to the power supply 50 , the vias 60 e , 64 e , 62 , and 63 . A second row of traces electrically connect the second row of vias 64 a - 64 e and the third row of vias respectively. A third row of traces are electrically connected to the fourth and fifth rows of vias respectively, and the vias 62 and 63 . A fourth row of traces are electrically connected to the fourth row of vias and the third row of traces respectively. A fifth row of traces electrically connect the first row of vias 60 a - 60 e and the fifth row of vias respectively. A sixth row of traces electrically connect the third row of vias and the fourth row of vias respectively.

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above everything. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.