Method and semiconductor device for monitoring battery voltages

1. Field of the Invention

The present invention relates to a method and semiconductor device for monitoring battery voltages.

2. Description of the Related Art

Semiconductor devices for monitoring a plurality of unit batteries or battery cells connected in series are already available. Well known examples include battery monitoring integrated circuits (ICs) for vehicles. For example, in Japanese Patent Application Publication No. 2003-070179, Miyazaki et al. disclose an electrical storage device including a plurality of high-energy cells connected in series in a hybrid electric vehicle, and a method of controlling the electrical storage device. The disclosed method employs a battery monitoring IC with the configuration shown in simplified form in FIG. 1 .

The battery monitoring IC 100 in FIG. 1 is connected through a low-pass filter circuit (LPF) 116 to a battery 114 including five battery cells Vc 5 to Vc 1 coupled in series. The positive terminal of battery cell Vc 5 is connected to the VCC power supply terminal of the battery monitoring IC 100 . The negative terminal of battery cell Vc 1 is connected to ground (GND). The two terminals of each of the battery cells Vc 5 to Vc 1 in the battery 114 are connected through the low-pass filter circuit 116 to corresponding inputs of a cell selector switch 118 in the battery monitoring IC 100 . The low-pass filter circuit 116 includes resistors Rf 5 to Rf 0 and capacitors Cf 5 to Cf 1 . The cell selector switch 118 includes switching elements SW 5 , SW 4 _ 1 , SW 4 _ 2 , . . . , SW 1 _ 1 , SW 1 _ 2 , SW 0 , which receive voltages V 05 , V 04 , . . . , V 02 , V 01 . The outputs Vx, Vy of the cell selector switch 118 are connected to an analog level shifter 122 that includes current sensing resistors R 4 to R 1 , an amplifier 136 , and dummy switches SWA and SWB. The dummy switches SWA and SWB are similar to the switching elements in the cell selector switch 118 except that they are permanently switched on. External resistors RD 2 and RD 1 , having the same resistance value as resistors Rf 5 to Rf 0 in the low-pass filter circuit 116 , are connected to the analog level shifter 122 at terminals Vout 2 and Vout 1 to provide symmetrical paths from the input terminals of the amplifier 136 to the battery 114 , the output terminal of the amplifier 136 , and ground.

To measure the voltage of battery cell Vc 5 , for example, switching elements SW 5 and SW 4 _ 1 are turned on and the other switching elements in the cell selector switch 118 are turned off. Since the voltage-sensing resistors R 1 -R 4 have mutual identical resistance values and switching elements SW 5 , SW 4 _ 1 , SWA, and SWB have mutual identical on-resistance values, the voltage (V 5 −V 4 ) across battery cell Vc 5 is converted by the analog level shifter 122 to an equal output voltage Vout with respect to ground (Vout=V 5 −V 4 ).

The voltages across battery cells Vc 4 to Vc 1 are measured similarly, with switching elements SW 4 _ 2 and SW 3 _ 1 , SW 3 _ 2 and SW 2 _ 1 , SW 2 _ 2 and SW 2 _ 1 , and SW 1 _ 2 and SW 0 turned on, respectively.

Referring to FIG. 2 , the switching elements in the cell selector switch 118 are metal-oxide-semiconductor (MOS) transistors having respective parasitic capacitances C 5 , C 41 , C 42 , . . . , C 11 , C 12 , C 0 with respect to ground. The dummy switching elements SWA, SWB and the wiring connecting them to the cell selector switch 118 , amplifier 136 , and ground also have parasitic capacitances. When the switching elements in the cell selector switch are all turned off, these parasitic capacitances discharge to ground level.

When switching elements SW 5 and SW 4 _ 1 are switched on to measure the voltage across battery cell Vc 5 , for example, there is sudden transfer of charge on the paths indicated by the thick black lines in FIG. 2 . The voltage V 51 received by switching element SW 5 plunges as charge moves from capacitor Cf 5 in the low-pass filter circuit 116 toward ground through terminal Vout 1 , and into the parasitic capacitances en route. This plunge is followed by a gradual recovery as capacitor Cf 5 is recharged from the positive terminal of battery cell Vc 5 .

In addition, when switching element SW 5 is switched on, the voltage at the non-inverting input terminal of amplifier 136 rises. The output voltage Vout rises abruptly in response and is fed back through terminal Vout 2 , pulling up the voltage V 41 input to switching element SW 4 _ 1 . Due to the reduced difference between voltages V 51 and V 41 , however, the initial abrupt rise in the output voltage Vout is followed by a droop that persists for some time until the correct output value (V 5 −V 4 ) is attained. These changes in V 51 , V 41 , and Vout are illustrated schematically in FIG. 3 .

The time T taken to recover from the output voltage droop depends on the time constant of the low-pass filter circuit 116 , which increases with the resistance values of resistors Rf 5 to Rf 0 and the capacitance values of capacitors Cf 5 to Cf 1 . If the time constant is large enough to provide the filtering effect needed for accurate measurement, the recovery period T can be fairly long.

During the recovery period T and until the measurement ends, there is a continuing flow of current from the battery 114 to ground and to the output terminal of the amplifier 136 on the paths indicated in FIG. 2 . For accurate measurement, the transistors in the cell selector switch 118 must be large enough to carry these currents. With the conventional battery monitoring IC 100 , accordingly, it can take significant time for the output of the analog level shifter 122 to stabilize and the correct measurement to be obtained, and large switching elements are necessary.

An object of the present invention is to shorten battery voltage measurement time.

The invention provides a semiconductor device for monitoring a plurality of unit batteries connected in series. The semiconductor device includes a selector switch that selects one of the unit batteries and outputs a first voltage obtained from the positive terminal of the selected unit battery and a second voltage obtained from the negative terminal of the selected unit battery.

A first buffer amplifier receives the first voltage from the selector switch and outputs a corresponding voltage. A second buffer amplifier receives the second voltage from the selector switch and outputs a corresponding voltage. The first and second buffer amplifiers have high-impedance input terminals that block current flow from the selector switch.

A level shifter receives the voltage outputs of the first and second buffer amplifiers and produces a shifted voltage corresponding to the difference between the first voltage and the second voltage as the output of the semiconductor device.

Since the buffer amplifiers block input current flow, even if the semiconductor device is connected to the unit batteries through a low-pass filter circuit with a comparatively large time constant, output voltage droop is reduced to a small amount and the recovery time is shortened accordingly.

In the attached drawings:

FIG. 1 is a circuit diagram showing an exemplary schematic structure of a conventional semiconductor device;

FIG. 2 indicates current paths when the voltage of battery cell Vc 5 is measured by the conventional semiconductor device;

FIG. 3 is a waveform diagram showing exemplary waveforms pertaining to the voltage measurement in FIG. 2 ;

FIG. 4 is a circuit diagram showing an exemplary schematic structure of a semiconductor device according to a first embodiment of the invention;

FIG. 5 is a circuit diagram showing an exemplary schematic structure of the switching elements in FIG. 4 ;

FIG. 6 is a circuit diagram showing an exemplary schematic structure of the buffer amplifiers in FIG. 4 ;

FIG. 7 indicates current paths when the voltage of battery cell Vc 5 is measured by the semiconductor device in FIG. 4 ;

FIG. 8 is a waveform diagram showing exemplary waveforms pertaining to the voltage measurement in FIG. 7 ;

FIG. 9 is a circuit diagram showing an exemplary schematic structure of a semiconductor device according to a second embodiment of the invention;

FIG. 10 is a circuit diagram showing an exemplary schematic structure of a semiconductor device according to a third embodiment; and

FIG. 11 is a circuit diagram showing an exemplary schematic structure of a semiconductor device according to a fourth embodiment.

Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. The unit batteries will be referred to as battery cells.

First Embodiment

Referring to FIG. 4 , the battery monitoring IC 10 in the first embodiment measures the voltage of a battery 14 to which the battery monitoring IC 10 is connected through a low-pass filter circuit (LPF) 16 . The battery monitoring IC 10 includes a cell selector switch 18 , a buffer amplifier (amp) circuit 20 , and an analog level shifter 22 . The buffer amplifier circuit 20 includes a pair of buffer amplifiers 30 , 32 . The analog level shifter 22 includes voltage-sensing resistors R 4 to R 1 and an amplifier 36 .

The battery 14 includes, for example, five battery cells Vc 5 to Vc 1 connected in series. The positive terminal of battery cell Vc 5 is connected to the VCC power supply terminal of the battery monitoring IC 10 . The negative terminal of battery cell Vc 1 is connected to ground. The voltages V 5 to V 0 at the terminals of the battery cells Vc 5 to Vc 1 are supplied to the cell selector switch 18 through the low-pass filter circuit 16 , which includes resistors Rf 5 to RF 0 and capacitors Cf 5 to Cf 1 .

The cell selector switch 18 in this embodiment includes high-voltage MOS transistors connected to operate as mutually identical switching elements SW 5 , SW 4 _ 1 , SW 4 _ 2 , . . . , SW 1 _ 1 , SW 1 _ 2 , SW 0 . Each of these switching elements has, for example, the configuration shown in FIG. 5 , including an re-channel metal-oxide-semiconductor (NMOS) transistor 70 , a p-channel metal-oxide-semiconductor (PMOS) transistor 72 , and an inverter 74 . When the control signal input to the inverter 74 is at the high logic level, the NMOS transistor 70 and PMOS transistor 72 are switched on and pass a voltage from the low-pass filter circuit 16 to the buffer amplifier circuit 20 . When the control signal input to the inverter 74 is at the low logic level, the NMOS transistor 70 and PMOS transistor 72 are switched off and the switching element is in the high-impedance state.

Other configurations for the switching elements in the cell selector switch 18 are also possible, provided high-voltage transistors are used.

The outputs of the cell selector switch 18 are connected to the non-inverting terminals of the buffer amplifiers in the buffer amplifier circuit 20 . Specifically, switching elements SW 5 , SW 4 _ 2 , SW 3 _ 2 , SW 2 _ 2 , and SW 1 _ 2 are connected to the non-inverting terminal of buffer amplifier 30 , while switching elements SW 4 _ 1 , SW 3 _ 1 , SW 2 _ 1 , SW 1 _ 1 , and SW 0 are connected to the non-inverting terminal of buffer amplifier 32 . The output of each buffer amplifier is connected as negative feedback to the inverting terminal of the same buffer amplifier, so that the buffer amplifiers 30 , 32 operate as voltage followers.

Both buffer amplifiers 30 , 32 are identically configured. Referring to FIG. 6 , each of the buffer amplifiers 30 , 32 includes high-voltage PMOS transistors 80 , 82 , 84 , 86 , a capacitor 88 , and high-voltage NMOS transistors 90 , 92 , 94 . PMOS transistor 80 is biased at a voltage that permits saturation operation. The input impedance of the buffer amplifiers 30 , 32 is low because the only input current flow is a small transient flow into or out of the gate capacitances of transistors 82 and 84 when the input voltages change. The buffer amplifiers 30 , 32 output respective voltages Vx 1 and Vy 1 equal to the voltages Vx and Vy input at their non-inverting terminals.

Other configurations of the buffer amplifiers 30 , 32 are also possible provided high-voltage transistors are used.

The outputs of the buffer amplifier circuit 20 are connected to the analog level shifter 22 . The output Vx 1 of buffer amplifier 30 is connected through voltage-sensing resistor R 1 to the non-inverting terminal of the amplifier 36 ; the output Vy 1 of buffer amplifier 32 is connected through voltage-sensing resistor R 3 to the inverting terminal of the amplifier 36 .

The analog level shifter 22 outputs the difference Vout between the voltages at the two terminals of the battery cell selected by the cell selector switch 18 as the output of the battery monitoring IC 10 . An exemplary configuration of the analog level shifter 22 in this embodiment includes a amplifier 36 having the same configuration as the buffer amplifiers 30 , 32 shown in FIG. 6 and voltage-sensing resistors R 4 to R 1 having mutually identical resistance values (R 4 =R 3 =R 2 =R 1 ). Resistor R 2 is coupled to ground at an external terminal VSS.

How the battery voltages of the battery cells Vc 5 to Vc 1 are measured by the battery monitoring IC 10 in this embodiment will be described with reference to FIGS. 7 and 8 . When the voltage (V 5 −V 4 ) of battery cell Vc 5 is measured, switching elements SW 5 and SW 4 _ 1 in the cell selector switch 18 are switched on and the other switching elements are switched off. Because of the high input impedance of the buffer amplifiers 30 , 32 , there is no current flow through resistors Rf 5 and Rf 4 and no corresponding voltage drop (V 51 =V 5 , V 41 =V 4 ). The outputs Vx, Vy of the cell selector switch 18 (via switching elements SW 5 and SW 4 _ 1 ) and the outputs of the buffer amplifiers 30 , 32 are therefore equal to the voltages at the terminals of battery cell Vc 5 (Vx 1 =Vx=V 5 , Vy 1 =Vy=V 4 ). Accordingly, a voltage equal to the voltage across battery cell Vc 5 (V 5 −V 4 ) but referenced to ground is output from the analog level shifter 22 as the external output Vout.

Similarly, to measure the voltage of battery cell Vc 4 , switching elements SW 4 _ 2 and SW 3 _ 1 are switched on, the other switching elements in the cell selector switch 18 are switched off, and the analog level shifter 22 outputs a voltage Vout equal to V 4 −V 3 . To measure the voltage of battery cell Vc 3 , switching elements SW 3 _ 2 and SW 2 _ 1 are switched on, the other switching elements are switched off, and the analog level shifter 22 outputs a voltage Vout equal to V 3 −V 2 . To measure the voltage of battery cell Vc 2 , switching elements SW 2 _ 2 and SW 1 _ 1 are switched on, the other switching elements are switched off, and the analog level shifter 22 outputs a voltage Vout equal to V 2 −V 1 . To measure the voltage of battery cell Vc 1 , switching elements SW 1 _ 2 and SW 0 are switched on, the other switching elements are switched off, and the analog level shifter 22 outputs a voltage Vout equal to V 1 −V 0 .

The voltages of the constituent cells Vc 5 to Vc 1 of the battery 14 can therefore be read from the output Vout of the battery monitoring IC 10 . The battery monitoring IC 10 can be used to measure the voltages of the batteries in electric vehicles, hybrid vehicles, and other types of vehicles.

Because of the high input impedance of the buffer amplifiers 30 , 32 , during these voltage measurements, although current flows on the paths indicated by the thick black lines in FIG. 7 , there is substantially no current flow through the low-pass filter circuit 16 and cell selector switch 18 . Since the switching elements in the cell selector switch 18 have very little current to switch, they can be small in size. Specifically, the gate lengths and especially the gate widths of the switching elements in the cell selector switch 18 can be small, which reduces their parasitic capacitances C 5 , C 41 , C 42 , . . . , C 11 , C 12 , C 0 .

Due to the very high input impedance of the buffer amplifiers 30 , 32 and the small parasitic capacitances in the cell selector switch 18 , when a pair of switching elements in the cell selector switch 18 is switched on, there is only a small transfer of charge between the low-pass filter circuit 16 and the battery monitoring IC 10 . For example, when switching elements SW 5 and SW 4 _ 1 are switched on, there is only a slight flow of charge among capacitor Cf 5 in the low-pass filter circuit 16 , parasitic capacitances C 5 and C 4 _ 1 in the cell selector switch 18 , and the gate capacitances of the input transistors in the buffer amplifiers 30 , 32 . Consequently, a small and brief flow of current through resistors Rf 5 and Rf 4 suffices to recharge capacitor Cf 5 , and in contrast to the conventional battery monitoring IC 100 in FIG. 2 , there is no flow of current through resistors Rf 5 and Rf 4 to ground, or to the amplifier 36 in the analog level shifter 22 .

When switching elements SW 5 and SW 4 _ 1 are switched on, therefore, there is only a brief and slight change in the voltages V 51 and V 41 at the corresponding input terminals of the battery monitoring IC 10 , and the output voltage Vout stabilizes quickly. Referring to FIG. 8 , if the on and off voltage levels of switching elements SW 5 and SW 4 _ 1 are, for example, 60 V and 0 V, respectively, then given typical resistance and capacitance values, the shift of charge between the low-pass filter 16 and the battery monitoring IC 10 produces only a 3-mV drop in voltage V 51 and a 3-mV rise in voltage V 41 , and both voltages recover their normal levels within 500 μs. As a result, there is an initial droop of only 6 mV in the output voltage Vout, and the battery cell voltage can be measured accurately in 500 μs.

Similar effects of reduced output droop and shortened measurement time are obtained when the voltages of the other battery cells Vc 4 to Vc 0 are measured.

The buffer amplifiers 30 , 32 replace the dummy switches SWA, SWB and dummy resistors RD 1 , RD 2 in the conventional battery monitoring IC 100 in FIG. 1 , which are not needed because there is essentially no current flow between the low-pass filter circuit 16 and the battery monitoring IC 10 . The absence of these dummy switches and dummy resistors and the reduced size of the switching elements in the cell selector switch 18 compensate for the additional presence of the buffer amplifier circuit 20 , so that adding the buffer amplifier circuit 20 does not greatly increase the size and cost of the battery monitoring IC 10 . Another factor is that the buffer amplifier circuit 20 receives its power supply VCC from the positive terminal of battery cell Vc 5 in the battery 14 , so that no additional power source is required.

Second Embodiment

Referring to FIG. 9 , the second embodiment is identical to the first embodiment except that the battery monitoring IC 40 in the second embodiment has an additional voltage boosting circuit 42 , which supplies power to the buffer amplifier circuit 20 at a voltage VCC 1 higher than the power supply voltage VCC the battery monitoring IC 40 receives from the battery 14 . The amplifier 36 in the analog level shifter 22 operates on VCC as in the first embodiment.

In the first embodiment, since the buffer amplifiers 30 , 32 receive the voltage at the positive terminal of battery cell Vc 5 as their power supply voltage, when the voltage of battery cell Vc 5 is measured, the input voltage Vx of buffer amplifier 30 is the same as its power supply voltage VCC. This leads to a high-end offset in the output voltage Vx 1 of buffer amplifier 30 , and affects the accuracy of the output voltage Vout. The offset continues until Vx becomes low enough for the transistors in buffer amplifier 30 to conduct saturation current.

In the second embodiment, the voltage boosting circuit 42 boosts the power supply voltage of the buffer amplifiers 30 , 32 to a level such that their constituent transistors can conduct saturation current over the full range of possible input voltages Vx and Vy. The outputs Vx 1 and Vy 1 of buffer amplifiers 30 and 31 are accordingly free of high-end offset, and the accuracy of the measurement of the battery cell voltages by the output voltage Vout is improved.

The level to which the voltage boosting circuit 42 boosts the power supply voltage is a design choice that depends on the characteristics of the MOS transistors in the buffer amplifiers 30 , 32 . As one example, if VCC is 60 V, a voltage VCC 1 of 65 V may be adequate to permit the MOS transistors operate in their saturation region.

In a variation of the second embodiment, the boosted supply voltage VC 1 is supplied from an external source, instead from a voltage boosting circuit in the battery monitoring IC 40 .

In another variation of the second embodiment, the battery voltage VCC and the boosted voltage VCC 1 are supplied selectively to the buffer amplifiers 30 , 32 , depending on the VCC level and the state of the cell selector switch 18 , for example.

Third Embodiment

Referring to FIG. 10 , the third embodiment is identical to the second embodiment except that the battery monitoring IC 50 has an additional bypass switching element SWK that can bypass the buffer amplifier circuit 20 and analog level shifter 22 . Switching element SWK selects either the Vx output of the cell selector switch 18 or the output of the analog level shifter 22 as the output voltage Vout of the battery monitoring IC 50 .

In the first and second embodiments, when the voltage of battery cell Vc 1 is measured, buffer amplifier 32 receives the ground voltage at the negative terminal of battery cell Vc 1 as its input voltage Vy. Since this voltage is identical to the ground voltage of buffer amplifier 32 itself, MOS transistors in buffer amplifier 32 fail to conduct saturation current, producing a low-end offset in the output voltage Vy 1 of buffer amplifier 32 . This offset also affects the accuracy of the output voltage Vout.

In the third embodiment, when the voltage of battery cell Vc 1 is measured, switching elements SW 0 and SW 1 _ 2 in the cell selector switch 18 are switched on, and switching element SWK is set to select voltage Vx as the output Vout of the battery monitoring IC 50 , bypassing the buffer amplifier circuit 20 and analog level shifter 22 . The problem of non-saturated operation of buffer amplifier 32 is therefore also bypassed, improving the accuracy of the measurement of the voltage of battery cell Vc 1 . The analog level shifter 22 is unnecessary for this measurement because with switching elements SW 0 and SW 1 _ 2 in the cell selector switch 18 switched on, Vx itself is the voltage across battery cell Vc 1 with respect to ground.

Although the positive terminal of battery cell Vc 1 is now connected directly to the output terminal of the battery monitoring IC 50 , this output terminal is normally connected to a next-stage circuit (not shown) with high input impedance. Accordingly, there is still no significant flow of current on this current path and no significant voltage drop in resistor Rf 1 in the low-pass filter circuit 16 .

When the voltages of the other battery voltage cells Vc 2 to Vc 5 are measured, switching element SWK is set to select the output voltage of the analog level shifter 22 as the output voltage Vout of the battery monitoring IC 50 .

Fourth Embodiment

Referring to FIG. 11 , the fourth embodiment adds a pair of test switching elements SWP and SWN to the configuration shown in the third embodiment. When switched on, switching element SWP bypasses buffer amplifier 30 by connecting its non-inverting input terminal directly to its output terminal, and switching element SWN bypasses buffer amplifier 32 in a similar fashion. When switching elements SWP and SWN are switched off, the battery monitoring IC 60 in the fourth embodiment operates in the same way as the battery monitoring IC 50 in the third embodiment.

Switching elements SWP and SWN are used to test the buffer amplifiers 30 , 32 . The voltages of battery cells Vc 5 to Vc 1 are measured first with switching elements SWP and SWN switched off and then with switching elements SWP and SWN switched on, and the two sets of measurement results are compared. If both results agree to within a predetermined tolerance, the test passes and the buffer amplifiers 30 , 32 are regarded as operating normally. If the results disagree, the test fails, indicating that one or both of the buffer amplifiers 30 , 32 is defective.

In the fourth embodiment, the battery monitoring IC 60 accordingly has a self-test capability that can be used to detect voltage measurement accuracy problems caused by malfunctions of the buffer amplifiers 30 , 32 and take corrective action.

The five-cell battery 14 shown in the drawings is purely exemplary. The invention may be used to monitor the voltages of a battery consisting of any number of cells connected in series, or the voltages of multiple batteries connected in series. In the latter case each battery unit may be a battery including multiple cells.

The capacitors Cf 5 to Cf 1 in the low-pass filter circuit 16 may be connected between the positive terminals of the battery cells Vc 5 to Vc 1 and ground, for example, instead of being connected between the positive and negative terminals of these battery cells as shown in the drawings.

Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.