Circuit and method for generating the stochastic signal

1. Field of Invention

The present invention relates to a signal generation circuit and method, and more particularly to a circuit and method for generating the stochastic signal.

2. Description of Related Arts

Stochastic signals, as serial numbers, are widely used in various electronic products and play a very important role in the information security of the electronic products. At present, the serial numbers of the electronic products are generated by two methods. In the first method, the serial numbers are generated by the software. The serial numbers are provided by some randomized algorithms of the software. Therefore, the first method is adapted for the electronic products having the software operation, and it is prone to be cracked. In the second method, the serial numbers are generated by the hardware, namely, the internal integrated circuits. In generally, after finishing the integrated circuit manufacturing process, some branches of the internal circuits of the integrated circuits are fused at the high temperature or one-time programmable circuit programming is made for generating various serial numbers of the integrated circuits. The second method is performed after finishing the integrated circuit manufacturing process, so the cost of the integrated circuit is increased. Furthermore, it cannot ensure the uniqueness of the serial number among different integrated circuits. Also, the information security of the electronic products using the integrated circuits is decreased.

An object of the present invention is to provide a circuit and method for generating the stochastic signal, which are capable of directly generating the stochastic signal during the integrated circuit manufacturing process.

Another object of the present invention is to provide a circuit and method for generating the stochastic signal, which are capable of better ensuring the uniqueness of the serial number among different integrated circuits.

Accordingly, in order to accomplish the above objects, the present invention provides a stochastic signal generation circuit, comprising:

a signal output circuit comprising two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal; and

a signal processing circuit connected with the signal output circuit, wherein the signal processing circuit converts the analog voltage signal into a stochastic digital signal.

Furthermore, the present invention provides a method for generating a stochastic signal, comprising the steps of:

(1) detecting a slight mismatch between two matching semiconductor components by a signal output circuit, and converting the detected slight mismatch into a corresponding electric signal;

(2) generating an analog voltage signal by amplifying the electric signal through the signal output circuit; and

(3) outputting a stochastic digital signal by making a digitalized treatment to the analog voltage signal through a signal processing circuit.

Compared with the prior art, the stochastic signal of the present invention is directly generated during the integrated circuit manufacturing process. After finishing the integrated circuit manufacturing process, the stochastic signal will be generated, and only needs to be read out. Therefore, no follow-up work is needed, thereby greatly decreasing the cost of the integrated circuit. Furthermore, no artificially operation exists, the probability of the uniqueness of the serial number among different integrated circuits can be improved, thereby better ensuring the information security of the electronic products.

These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

FIG. 1 is a circuit diagram of a signal output circuit of a stochastic signal generation circuit according to a preferred embodiment of the present invention.

FIG. 2 is a circuit diagram of a signal processing circuit of a stochastic signal generation circuit according to the preferred embodiment of the present invention.

FIG. 3 is a flow chart of a method for generating the stochastic signals according to the preferred embodiment of the present invention.

A stochastic signal generation circuit according to a preferred embodiment of the present invention is illustrated, which comprises a signal output circuit and a signal processing circuit.

As shown in FIG. 1 , the signal output circuit according to the preferred embodiment of the present invention is illustrated, which comprises a power supply AVD, a ground AVS, an output end Vout and a plurality of field effect transistors (FETs) consisting of MP 21 , MP 22 , MP 23 , MP 24 , MP 25 , MP 26 , MN 21 , MN 22 , MN 23 , MN 24 and MN 25 . The FETs MN 23 , MN 24 and MN 25 form an amplifying sub circuit. The

FETs MP 21 , MP 22 , MN 21 , MN 22 , MP 25 and MP 26 form a bias sub circuit to provide the stable current for the amplifying sub circuit. In the preferred embodiment of the present invention, the FETs MP 21 , MP 22 , MP 23 , MP 24 , MP 25 and MP 26 are P-type field effect transistors (PMOS), and the FETs MN 21 , MN 22 , MN 23 , MN 24 and MN 25 are N-type field effect transistors (NMOS). In other embodiments, the FETs can be replaced by the switching components or circuits which are capable of achieving the same function as required.

The connection relations of the signal output circuit are described as follows. The gates of the FETs MP 21 , MP 22 , MN 21 and MN 22 are connected with each other. The drain of the FET MP 21 is connected with the source of the FET MP 22 . The drain of the FET MP 22 is connected with the drain of the FET MN 21 . The source of the FET MN 21 is connected with the drain of the FET MN 22 . The sources of the FETs MP 21 , MP 25 and MP 26 are connected with the power supply AVD. The gates of the FETs MP 26 and MP 25 are connected with the drain of the FET MP 21 . The sources of the FETs MP 23 and MP 24 are connected with the drain of the FET MP 26 . The gate of the FET MP 23 is connected with the drain of the FET MP 22 . The gate of the FET MP 24 is connected with the drain of the FET MP 22 . The drain of the FET MP 25 and the drain of the FET MN 25 are connected with the output end Vout. The source of the FET MN 22 , the source of the FET MN 23 , the source of the FET MN 24 and the source of the FET MN 25 are connected with the ground AVS. The drain of the FET MP 23 , the drain of the FET MN 23 , the gate of the FET MN 23 are connected with the gate of the FET MN 24 . The drain of the FET MN 24 and the drain of the FET MP 24 are connected with the gate of the FET MN 25 . The gate of the FET MP 22 is connected with the drain of the FET MP 22 .

The working principle of the signal output circuit is described as follows. During the integrated circuit manufacturing process, owing to the edge effect, the ion implantation gradient effect, the surface state effect, the change of the carrier mobility and other undesirable factors, the stochastic slight mismatch will be generated between the FETs MP 23 and MP 24 as two matching semiconductor components which match in the theoretical design, such as the mismatch of the length and width, the mismatch of the threshold voltage or the mismatch of the saturation current between the FETs MP 23 and MP 24 . Accordingly, the drains of the FETs MP 23 and MP 24 respectively output two electric signals with different sizes, the two electric signals respectively pass through the FETs MN 23 and MN 24 , so that the drain of the FET MN 24 outputs a weak voltage signal to the gate of the FET MN 25 . The drain of the FET MN 25 outputs an amplified analog voltage signal to the output end Vout.

As shown in FIG. 2 , the signal processing circuit according to the preferred embodiment of the present invention is illustrated, which comprises a power supply AVD, a ground AVS, an input end Vin for receiving the analog voltage signal which is output from the output end Vout of the signal output circuit, an output end Vout, and a plurality of FETs consisting of FETs MP 31 , MP 32 , MP 33 , MN 31 , MN 32 and MN 33 . In the preferred embodiment of the present invention, the FETs MP 31 , MP 32 and MP 33 are P-type field effect transistors (PMOS), the FETs MN 31 , MN 32 and MN 33 are N-type field effect transistors (NMOS). In other embodiments, the FETs can be replaced by the switching components or circuits which are capable of achieving the same function as required.

The connection relations of the signal processing circuit are described as follows. The source of the FET MP 31 , the source of the FET MP 32 and the source of the FET MP 33 are connected with the power supply AVD. The gate of the FET MP 31 and the gate of the FET MN 31 are connected with the input end Vin, thus acting as the input end of the signal processing circuit. The drain of the FET MP 31 , the drain of the FET MN 31 , the gate of the FET MP 32 , the gate of the FET MN 32 , the drain of the FET MP 33 and the drain of the FET MN 33 are connected with each other. The drain of the FET MP 32 , the drain of the FET MN 32 , the gate of the FET MP 33 and the gate of the FET MN 33 are connected with the output end Vout, thus acting as the output end of the signal processing circuit. The source of the FET MN 31 , the source of the FET MN 32 and the source of the FET MN 33 are connected with the ground AVS.

The working principle of the signal processing circuit is described as follows. The FETs MP 31 and MN 31 form an inverter circuit. The amplified analog voltage signal, which is output by the output end Vout of the signal output signal, is converted into the digital signal having the high and low levels. The FETs MP 32 , MN 32 , MP 33 and MN 33 form a latch circuit to output the digital signal which is output by the inverter circuit in the latching manner.

Referring to FIG. 3 , a method for generating the stochastic signals according to the preferred embodiment of the present invention is illustrated, wherein the method comprises the steps as below.

(1) Detect the slight mismatch between two matching semiconductor components by the signal output circuit, and convert the detected slight mismatch into the corresponding weak electric signal.

(2) Amplify the weak electric signal by the amplifying sub circuit to generate an amplified analog voltage signal which is related with the slight mismatch.

(3) Make the digitalized treatment to the amplified analog voltage signal by the signal processing circuit and output a stochastic digital signal.

(4) Take the stochastic signal generation circuit as a standard cell circuit, place a plurality of the standard cell circuits at various regions of the integrated circuit layout to generate a plurality of irrelevant stochastic signals.

The matching semiconductor components comprise the resistors, capacitors, inductors, FETs, triodes, diodes and so on. The slight mismatch comprises the mismatch of the size of the semiconductor components, the mismatch of the electrical parameters and so on.

In the preferred embodiment of the present invention, the matching semiconductor components are FETs MP 23 and MP 24 . During the integrated circuit manufacturing process, owing to the edge effect, the ion implantation gradient effect, the surface state effect, the change of the carrier mobility and other undesirable factors, the stochastic slight mismatch will be generated between the FETs MP 23 and MP 24 . Accordingly, the drains of the FETs MP 23 and MP 24 respectively output two electric signals with different sizes, the two electric signals respectively pass through the FETs MN 23 and MN 24 , so that the drain of the FET MN 24 outputs a weak voltage signal to the gate of the FET MN 25 . The drain of the FET MN 25 outputs an amplified analog voltage signal to the output end Vout, and inputs the amplified analog voltage signal to the signal processing circuit through the input end Vin of the signal processing circuit. The output end Vout of the signal processing circuit outputs a stochastic digital signal.

Owing to the unpredictability of the slight mismatch between the semiconductor components, the present invention makes use of the slight mismatch which is generated in the integrated circuit manufacturing process, converts the slight mismatch of the matching semiconductor components into the electric signal by the signal output circuit, and then amplifies and makes the digitalized treatment to the electric signal, and finally obtains a needed stochastic signal. The stochastic signal generation circuit is regarded as a standard cell circuit. Place a plurality of standard cell circuits at various regions of the integrated circuit layout to generate a plurality of irrelevant stochastic signals. The stochastic signals are directly generated during the integrated circuit manufacturing process. After finishing the integrated circuit manufacturing process, the stochastic signals will be generated, and only needs to be read out. Therefore, no follow-up work is needed, thereby greatly decreasing the cost of the integrated circuit. Furthermore, no artificially operation exists, the probability of the uniqueness of the serial number among different integrated circuits can be improved, thereby better ensuring the information security of the electronic products.

One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.

It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.