Frequency setting circuit and method for an integrated circuit

The present invention is related generally to a circuit and method for frequency setting of integrated circuits and, more particularly, to a frequency setting circuit and method implemented by digital circuits.

For integrated circuits (ICs), traditional design needs external frequency setting with dedicated pin to continuous setting. Therefore, the pin count is more and more critical, especially in low pin count ICs. For example, referring to FIG. 1 , an IC 10 has a pin RT to be connected with an external resistor R RT , a frequency setting circuit 12 to determine a frequency setting signal Iosc depending on the resistance of the resistor R RT , and an oscillator 14 , according to the frequency setting signal Iosc, to generate a clock CLK with the frequency

Fclk=k 1 ×Iosc,   [Eq-1]

where k 1 is a proportionality coefficient. The frequency setting circuit 12 includes an operational amplifier 16 , a transistor M 1 and a current mirror 18 established by transistors M 2 and M 3 . The operational amplifier 16 , the transistor M 1 and the resistor R RT establish a voltage-to-current converter to convert a voltage Vref into a current

I RT =Vref/R RT ,  [Eq-2]

which is mirrored by the current mirror 18 to generate the frequency setting signal

Iosc=N×I RT ,  [Eq-3]

where N is the size ratio between the transistors M 2 and M 3 . By applying the equations Eq-2 and Eq-3 to the equation Eq-1, it is derived

Fclk=k 1 ×N×Vref/R RT ,  [Eq-4]

which depicts that the frequency Fclk is inversely proportional to the resistance R RT , or as the curve shown in FIG. 2 .

In such designs as that shown in FIG. 1 , it needs a pin RT for frequency setting from outside of the IC 10 . Moreover, to maintain the set frequency Fclk, the pin RT has to be continuously used. With integrated functions increasing, the pins of an IC will be not enough to support, especially in low pin count ICs. Hence, there have been more and more solutions directed to the technique of multi-function pin. For example, U.S. Pat. No. 7,196,589 uses a single pin to implement the functions of frequency setting and frequency synchronization.

An objective of the present invention is to provide a frequency setting circuit and method to share a common pin with other functions.

Another objective of the present invention is to provide a frequency setting circuit and method implemented by digital circuits for an IC.

According to the present invention, a frequency setting circuit for an integrated circuit includes an analog-to-digital converter to detect the voltage at a pin of the integrated circuit to generate a first digital signal, a storage element to determine a second digital signal according to the first digital signal and store the second digital signal, and a digital-to-analog converter to generate a frequency setting signal according to the second digital signal to set the frequency of a clock provided by an oscillator in the integrated circuit.

According to the present invention, a frequency setting method for an integrated circuit includes detecting the value of a frequency setting device to generate a first digital signal, determining a second digital signal according to the first digital signal, storing the second digital signal, and determining a frequency setting signal according to the second digital signal to set the frequency of a clock provided by an oscillator in the integrated circuit.

The frequency setting circuit according to the present invention is constructed from digital circuits and thus is capable of storing the frequency setting signal. After setting the frequency, the frequency setting circuit can maintain the frequency of the clock according to the frequency setting signal it stores, without keeping detecting the voltage at the pin. In other words, after the frequency setting, the pin can be used to implement other functions.

These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a conventional frequency setting circuit;

FIG. 2 is a graph showing the relationship between the clock frequency and the resistance in the circuit of FIG. 1 ;

FIG. 3 is an embodiment according to the present invention;

FIG. 4 is a diagram showing an operation of the frequency setting circuit of FIG. 3 ;

FIG. 5 is a first embodiment for the ADC, the storage element and the DAC of FIG. 3 ;

FIG. 6 is a graph showing the relationship between the clock frequency and the resistance in the circuit of FIG. 5 ; and

FIG. 7 is a second embodiment for the ADC, the storage element and the DAC of FIG. 3 .

As shown in FIG. 3 , a power IC 20 has a pin RT to be connected with a resistor R RT that functions as a frequency setting device, a frequency setting circuit 22 to detect the resistance of the resistor R RT by detecting the voltage at the pin RT and accordingly, to generate a frequency setting signal Iosc, and an oscillator 14 to generate a clock CLK having a frequency Fclk depending on the frequency setting signal Iosc. The frequency setting circuit 22 includes an analog-to-digital converter (ADC) 24 , a storage element 26 and a digital-to-analog converter (DAC) 28 . The ADC 24 detects the voltage V RT at the pin RT during a frequency setting period which may be a power soft-start period of the power IC 20 , as shown in FIG. 4 for example, from time t 1 to time t 2 . When the power-on reset signal POR turns to high at time t 1 , the power IC 20 starts up and enters a soft-start process and the frequency setting status. At this time, the ADC 24 in the frequency setting circuit 22 is enabled to detect the voltage V RT at the pin RT to generate a first digital signal Sd 1 . The storage element 26 generates a second digital signal Sd 2 according to the first digital signal Sd 1 , and stores the second digital signal Sd 2 for the DAC 28 to determine the frequency setting signal Iosc. The DAC 28 may use a lookup table to determine the frequency setting signal Iosc. When the soft-start end signal PORD turns to high at time t 2 , the power IC 20 finishes the soft start and the frequency setting status, and enters its normal operation state while the ADC 24 is disabled. However, since the storage element 26 stores the second digital signal Sd 2 , the DAC 28 is able to maintain the frequency setting signal Iosc, so that the frequency setting circuit 22 has not to keep detecting voltage at the pin RT. As a result, once the power IC 20 accomplishes frequency setting, the pin RT becomes free and can be used to implement other functions. For instance, the pin RT may be designed to output a control signal for switching a low side power switch. Thereby, the number of the pins required by the power IC 20 is reduced.

In other embodiments, the resistor R RT on the pin RT may be replaced by a capacitor or diodes. For example, various numbers of diodes connected in series may be used to change the voltage V RT at the pin RT.

FIG. 5 is a first embodiment for the ADC 24 , the storage element 26 and the DAC 28 of FIG. 3 . In the ADC 24 , a current source 30 provides a constant current I RT to the pin RT, so as to generate a constant voltage

V RT =I RT ×R RT ,  [Eq-5]

and a comparator 32 compares the voltage V RT with a threshold Vth to generate the first digital signal Sd 1 . The storage element 26 has a counter 34 to adjust the second digital signal Sd 2 by counting the first digital signal Sd 1 , and to store the second digital signal Sd 2 in response to a sampling signal SH. The soft-start end signal PORD of FIG. 4 may be used as the sampling signal SH and thus, when the soft-start end signal PORD turns to high from low at time t 2 , the counter 34 will store the second digital signal Sd 2 . The DAC 28 generates the frequency setting signal Iosc and the threshold Vth according to the second digital signal Sd 2 . The counter 34 adjusts the second digital signal Sd 2 according to the first digital signal Sd 1 , so as to make the threshold Vth vary toward the voltage V RT . Assuming that the frequency setting signal

Iosc=k 2 ×Vth,   [Eq-6]

where k 2 is a proportionality coefficient, and the threshold Vth is equal to the voltage V RT , by substituting the equations Eq-5 and Eq-6 to the equation Eq-1, it is derived that the clock CLK has the frequency

Fclk=k 1 ×k 2 ×I RT ×R RT ,  [Eq-7]

which shows that the frequency Fclk is proportional to the resistance R RT . As long as the counter 34 and the DAC 28 have enough bits N, the frequency setting circuit 22 is able to realize stepless frequency setting as a traditional analog circuit, as the curve shown in FIG. 6 .

FIG. 7 is a second embodiment for the ADC 24 , the storage element 26 and the DAC 28 of FIG. 3 , in which the ADC 24 has the comparator 32 , the storage element 26 has the counter 34 , and the DAC 28 generates a current I RT and the frequency setting signal Iosc according to the second digital signal Sd 2 . The current I RT flows to the resistor R RT through the pin RT, so as to generate the voltage V RT as shown in the equation Eq-5. In this embodiment, the current I RT varies with the second digital signal Sd 2 , so the voltage V RT also varies with the second digital signal Sd 2 . In the ADC 24 , the comparator 32 compares the voltage V RT with a reference voltage Vref to generate the first digital signal Sd 1 . The counter 34 of the storage element 26 adjusts the second digital signal Sd 2 according to the first digital signal Sd 1 , so as to make the voltage V RT vary toward the reference voltage Vref. Assuming that the frequency setting signal Iosc is equal to the current I RT , and the voltage V RT is equal to the reference voltage Vref, it is derived that

Iosc=I RT =Vref/R RT .  [Eq-8]

By substituting the equation Eq-8 to the equation Eq-1, it is derived that the clock CLK will have the frequency

Fclk=k 1 ×Vref/R RT ,  [Eq-9]

which shows that the frequency Fclk is inversely proportional to the resistance R RT . As long as the counter 34 and the DAC 28 have enough bits N, the frequency setting circuit 22 is able to realize stepless frequency setting as a traditional analog circuit, as the curve shown in FIG. 2 .

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.