Wafer-bump structure

1. Field of Invention

The present invention relates to a wafer-bump structure and, more particularly, to a wafer-bump structure made in a process including the steps of zincating and electroless nickel/immersion gold (“ENIG”) instead of the step of under-bump metallization (“UBM”) and including the step of forming a pillar bump by printing conductive metal paste instead of electroplating gold, thus improving soldering thereof to other devices and reducing the cost thereof.

2. Related Prior Art

Referring to FIG. 2 , there is shown a conventional wafer-bump structure 5 made in a conventional under-bump metallization process. The wafer-bump structure 5 includes a semiconductor die 50 , an under-bump metal layer 60 and a pillar bump 70 . The semiconductor die 50 is formed with a surface 501 . At least one die pad 51 is embedded in the semiconductor die 50 . A passivation layer 52 is formed on the surface 501 of the semiconductor die 50 and a surface of the die pad 51 . The passivation layer 52 includes at least one aperture for allowing access to a portion of the surface of the die pad 51 .

In the making of the conventional wafer-bump structure 5 , the under-bump metallization process is executed to provide the die pad 51 . The cost of the conventional under-bump metallization process is high while the yield of the conventional under-bump metallization process is low. Moreover, in the making of the conventional wafer-bump structure 5 , a gold-electroplating process is used to form the pillar bump 70 . The gold-electroplating process is however expensive, and the resultant pillar bump 70 is expensive for being made of gold entirely. This problem is getting worse since the price of gold is skyrocketing.

The present invention is therefore intended to obviate or at least alleviate the problems encountered in prior art.

It is the primary objective of the present invention to provide an inexpensive wafer-bump structure.

To achieve the foregoing objective, the wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first electrodeless nickel/immersion gold laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the portion of the die pad not covered by the passivation layer. The first electrodeless nickel/immersion gold laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second electrodeless nickel/immersion gold laminate. The conductive metal layer is formed on the first electrodeless nickel/immersion gold laminate and another annular portion of the passivation layer around the first electrodeless nickel/immersion gold laminate. The second electrodeless nickel/immersion gold laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.

Other objectives, advantages and features of the present invention will be apparent from the following description referring to the attached drawings.

The present invention will be described via detailed illustration of the preferred embodiment versus the prior art referring to the drawings wherein:

FIG. 1 is a cross-sectional view of a wafer-bump structure according to the preferred embodiment of the present invention; and

FIG. 2 is a cross-sectional view of a conventional wafer-bump structure.

Referring to FIG. 1 , there is shown a wafer-bump structure 1 according to the preferred embodiment of the present invention. The wafer-bump structure 1 includes a wafer-state semiconductor die 10 , a pre-treatment layer 20 , a first electrodeless nickel/immersion gold laminate 30 and at least one pillar bump 40 .

The wafer-state semiconductor die 10 is formed with a surface 101 . At least one die pad 11 is embedded in the semiconductor die 10 . A passivation layer 12 is formed on the surface 101 of the semiconductor die 10 and a surface 111 of the die pad 11 . The passivation layer 12 includes at least one aperture for allowing access to a portion of the surface 111 of the die pad 11 .

The pre-treatment layer 20 is formed on the portion of the surface 111 of the die pad 11 that is not covered by the aperture defined in the passivation layer 12 . The pre-treatment layer 20 is an anti-erosion layer made in a zincating process.

The first electrodeless nickel/immersion gold laminate 30 is formed on the pre-treatment layer 20 and an annular region of a surface 121 of the passivation layer 12 around the aperture defined in the passivation layer 12 . The first electrodeless nickel/immersion gold laminate 30 is an anti-erosion layer made by an electroless nickel/immersion gold (“ENIG”) process. The first electrodeless nickel/immersion gold laminate 30 includes a nickel layer 31 and a gold layer 32 extending on the nickel layer 31 .

The pillar bump 40 includes a conductive metal layer 41 and a second electrodeless nickel/immersion gold laminate 42 . The pillar bump 40 improves soldering thereof to another electronic device.

The conductive metal layer 41 extends on the first electrodeless nickel/immersion gold laminate 30 and another annular portion of the surface 121 of the passivation layer 12 around the nickel/immersion gold laminate 30 . The conductive metal layer 41 is made of conductive silver paste or any other proper conductive metal paste by printing. The conductive metal layer 41 avoids deterioration of adhesion.

The second electrodeless nickel/immersion gold laminate 42 is used as an anti-erosion layer. The second electrodeless nickel/immersion gold laminate 42 is also made in an ENIG process. Therefore, the second electrodeless nickel/immersion gold laminate 42 includes a nickel layer 43 and a gold layer 44 . The nickel layer 43 extends on the conductive metal layer 41 and another annular portion of the surface 121 of the passivation layer 12 around the conductive metal layer 41 . The gold layer 44 extends on the nickel layer 43 and another annular portion of the surface 121 of the passivation layer 12 around the nickel layer 43 . The second electrodeless nickel/immersion gold laminate 42 may include any other materials that improve the wetting of solder that is used to connect the wafer-state semiconductor die 10 to another electronic device.

In making the wafer-bump structure 1 , based on whether the surface 101 of the semiconductor die 10 is provided with the passivation layer 12 or not, the passivation layer 12 is provided. If the surface 101 of the semiconductor die 10 is provided with the passivation layer 12 , the passivation layer 12 will not be provided.

As discussed above, according to the present invention, the pre-treatment layer 20 is made in the zicating process and the first electrodeless nickel/immersion gold laminate 30 is made in the ENIG process instead of an under-bump metallization process of which the yield is low but the cost is high. An under-bump metallization process may however be executed. Moreover, the conductive metal layer 41 is made of conductive metal paste by in the printing process and the second electrodeless nickel/immersion gold laminate 42 is made by the ENIG process instead of a gold layer made by a gold-coating process of which the yield is low but the cost is high.

The present invention has been described via the detailed illustration of the preferred embodiment. Those skilled in the art can derive variations from the preferred embodiment without departing from the scope of the present invention. Therefore, the preferred embodiment shall not limit the scope of the present invention defined in the claims.