Current driver, electronic device and current driving method

1. Field of the Invention

The present invention relates to current driving technique, and more particularly, to a current driver and a driving method capable of quickly generating driving current to drive a current driven device.

2. Description of the Prior Art

A current driver is utilized for generating a driving current to drive a current driven device, such as a laser diode, an LED, and other devices that are driven by current. In general, a current driver often utilizes a voltage buffer to control a gate voltage of a driving transistor, such that the driving transistor conducts and generates a driving current to drive a current driven device. In such a situation, when the current driver is switched from an off state to an activation state, the voltage buffer has to charge or discharge a gate of the driving transistor, to increase or decrease the gate voltage to be greater than or less than a source voltage by a threshold voltage, such that the driving transistor starts conducting and generating the driving current for enabling the driving current driven device to operate normally.

Please refer to FIG. 1A , which is a schematic diagram of a conventional current driver 10 . The current driver 10 is utilized for generating a driving current Id to drive a current driven device 12 . The current driver 10 , for example, can include a voltage buffer 102 , for receiving an input voltage Vin to generate an output voltage Vout, and further includes a bias current source 104 , for receiving control of the output voltage Vout to generate the driving current Id 1 .

Specifically, the voltage buffer 102 includes an input terminal for receiving the input voltage Vin, another input terminal coupled to the bias current source 104 , and an output terminal for providing the output voltage Vout. On the other hand, the bias current source 104 can, for example, include a driving switch Sd and one or more resistance elements, e.g. a resistor R. The driving switch Sd is disposed on a driving current path Pd, utilized for receiving the control of the output voltage Vout to conduct or cut off the driving current path Pd. The driving switch Sd can be realized by a driving transistor M 1 , e.g. an NMOSFET transistor, with a gate receiving the output voltage Vout of the voltage buffer 102 , i.e. a gate voltage Vg 1 =the output voltage Vout, a drain coupled to the current driven device 12 , and a source coupled to the resistor R and one of input terminals of the voltage buffer 102 . The resistor R can be coupled between the source of the driving transistor M 1 and a reference voltage level, e.g. a ground voltage level.

Please refer to FIG. 1B , which is a schematic diagram of waveforms of an activation signal Ena, the gate voltage Vg 1 and the driving current Id of the current driver 10 shown in FIG. 1A , utilized for illustrating operating principles of the current driver 10 . As shown in FIG. 1B , when the activation signal Ena is at a low voltage level, the voltage buffer 102 is not activated, causing the output voltage Vout, i.e. the gate voltage Vg 1 of the driving transistor M 1 , to remain at a low voltage level. As a result, the driving transistor M 1 cuts off and does not generate the driving current Id.

Conversely, after the activation signal Ena switches to a high voltage level to activate the voltage buffer 102 , the output voltage Vout starts rising to charge the gate of the driving transistor M 1 . When the gate voltage Vg 1 rises to be greater than the source voltage by a threshold voltage Vth 1 , the driving transistor M 1 starts conducting and generating the driving current Id to drive the current driven device 12 . Then, the voltage buffer 102 continues charging the gate of the driving transistor M 1 . Simultaneously, a negative feedback fixes the voltage Vr at a voltage level of the input voltage Vin maintaining a level of the driving current Id at Vin/R.

In such a situation, as shown in FIG. 1B , there exists a delay time Tdelay 1 from the time when the level of the activation signal Ena is switched to the time when the driving transistor M 1 starts conducting. In other words, the delay time Tdelay 1 is a charging time required for increasing the gate voltage Vg 1 by the threshold voltage Vth 1 . Additionally, some more time is required for the output voltage Vout of the voltage buffer 102 to rise. More disadvantageously, the driving transistor M 1 is often realized by a power MOS with a greater size and hence a greater capacitance, the delay time Tdelay 1 can actually be much longer. As a result, after the current driver 10 is activated, a lot of time is wasted before the current driven device 12 starts operating.

Similarly, operations of other conventional current drivers applying P-type driving transistors, which can be analogized by referring to the above operations, require a lot of discharging delay time as well. As a result, for applications that require repetitive switching on and off of the current driven device, high frequency operations can not be realized due to the excessively long delay time. Since the long delay time can not meet requirement of high frequency operations, there is a need for improvement of the prior art.

It is therefore an objective of the disclosure to provide a current driver, an electronic device utilizing the same and a driving method that are capable of quickly generating a driving current to drive a current driven device.

An embodiment discloses a current driver for driving a current driven device. The current driver includes a driving circuit, configured to generate a driving current to drive the current driven device, and conduct or cut off a driving current path through which the driving current flows according to a voltage level of a driving control node; and an accelerating circuit, coupled to the driving control node of the driving circuit, configured to provide an accelerating current flowing through the driving control node to accelerate a voltage level transition of the driving control node during an activation period of the driving circuit, and automatically cutoff the accelerating current when the voltage level of the driving control node reaches a preset level.

Another embodiment further discloses an electronic device. The electronic device includes a current driven device, for receiving driving of a driving current; and the above current driver, for providing the driving current.

A further embodiment further discloses a current driving method for driving a current driven device. The current driving method includes steps of generating a driving current flowing through a driving current path to drive the current driven device, and conducting or cutting off the driving current path according to a voltage level of a driving control node; and providing an accelerating current flowing through the driving control node to accelerate a voltage level transition of the driving control node during an activation period of starting generating the driving current, and automatically cutting off the accelerating current when a voltage of the driving control node reaches a preset level.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1A is a schematic diagram of a conventional current driver.

FIG. 1B is a schematic diagram of waveforms of an activation signal, a gate voltage and a driving current of the current driver shown in FIG. 1A .

FIG. 2A is a block structure diagram of a current driver according to another embodiment.

FIG. 2B is another embodiment a current driver of block structure diagram.

FIG. 3A is a detailed circuit diagram of the current driver shown in FIG. 2A according to an embodiment.

FIG. 3B is a schematic diagram of waveforms of an activation signal, a gate voltage, a driving current and an accelerating current of the current driver shown in FIG. 3A .

FIG. 4A is a detailed circuit diagram of the current driver shown in FIG. 2B according to an embodiment.

FIG. 4B is a schematic diagram of waveforms of an activation signal, a gate voltage, a driving current and an accelerating current of the current driver shown in FIG. 4A .

FIG. 5A and FIG. 5B are detailed circuit diagrams of the current drivers shown in FIGS. 2A and 2B according to other embodiments, respectively.

FIG. 6 is a schematic diagram a current driving process according to an embodiment.

Please refer to FIG. 2A , which is a block structure diagram of a current driver 20 according to an embodiment. The current driver 20 includes a driving circuit 204 and an accelerating circuit 202 . The driving circuit 204 is configured to generate a driving current Id to drive a current driven device 12 . Detailed structures and operations of the driving circuit 204 , for example, can be configured to be similar to those of the current driver 10 shown in FIG. 1 , including the buffer amplifier 102 and the bias current source 104 . Additionally, the driving circuit 204 and the current driven device 12 can be disposed in any electronic device.

On the other hand, a main difference between the current driver 10 and 20 is that the current driver 20 further includes the accelerating circuit 202 . During an activation period of the driving circuit 204 , the accelerating circuit 202 can be simultaneously activated to provide an accelerating current Ic flowing through a driving control node Nc of the driving circuit 204 , so as to facilitate the rising of a voltage level of the driving control node Nc, thereby accelerating the generation of the driving current Id.

Preferably, the driving control node Nc can be selected from any nodes of the driving circuit 204 that can control conducting or cutting off a driving current path Pd through which the driving current Id flows. In the driving circuit 204 of this embodiment, the gate of the driving transistor M 1 can be selected as the driving control node Nc. During the activation period of the driving circuit 204 , the gate of the driving transistor M 1 (e.g. an NMOSFET transistor), namely, the driving control node Nc, starts being charged by the output voltage of the buffer amplifier 102 . Meanwhile, since the accelerating circuit 202 is simultaneously activated, the accelerating current Ic can flow from the accelerating circuit 202 to the gate of the driving transistor M 1 . As a result, the accelerating current Ic can charge the gate of the driving transistor M 1 , facilitating the rising of the gate voltage level, and thereby accelerating the generation of the driving current Id.

Besides, the accelerating circuit 202 can be further configured to automatically cut off the accelerating current Id when the voltage of the driving control node Nc reaches a specific voltage level. In a specific embodiment, during the activation period of the driving circuit 204 , if the voltage level of the driving control node Nc switches from a first voltage level to a second voltage level to switch the driving transistor M 1 from cutting off to stably conducting, the specific voltage level can be set between the first voltage level and the second voltage level, or at most equal to the second level. Under a proper design, the specific voltage level can be set at a level of the threshold voltage Vth 1 of the driving transistor M 1 . In other words, the accelerating current Id can e be automatically cut off at a time point when the driving transistor M 1 starts conducting to generate the driving current Id.

FIG. 2A also illustrates a block structure diagram of the accelerating circuit 202 according to an embodiment. In this embodiment, the accelerating circuit 202 can include a reference voltage generating unit 206 and a bias current source 208 . The reference voltage generating unit 206 can provide a reference voltage Vref. The bias current source 208 , coupled between the driving control node Nc and the reference voltage generating unit 206 , can be biased by the voltage of the driving control node Nc and the reference voltage Vref to conduct or cut off the accelerating current Ic. Preferably, it can be designed such that the bias current source 208 automatically cuts off the accelerating current Ic when the voltage level of the driving control node Nc rises to a preset level, at which it differs from the voltage level of the reference voltage Vref by a specific value. In other words, the accelerating current Ic can be automatically cut off at a time point when the voltage level of the driving control node Nc=the preset level=the reference voltage−the specific value.

Please refer to FIG. 2B , which is a block structure diagram of a current driver 20 ′ according to another embodiment of the present invention. Structures and operations of the current driver 20 ′ shown in FIG. 2B are similar to those of the current driver 20 shown in FIG. 2A , with a main difference that flow directions of a driving current and an accelerating current are reversed.

In detail, in a driving circuit 204 ′, a driving transistor M 5 can be realized by a PMOSFET transistor instead, which can therefore generate a driving current Id′ flowing toward the current driven device 12 . In order to adapt to this modification, a direction of an accelerating current Ic′ can be generated from the driving control node Nc, i.e. a gate of the driving transistor M 5 , to an accelerating circuit 202 ′ to facilitate the discharging of the driving transistor M 5 . In such a configuration, the gate of the driving transistor M 5 starts to be discharged by an output voltage of a buffer amplifier 102 ′ during the activation period of the driving circuit 204 ′, while the accelerating current Ic′ can simultaneously discharge the gate of the driving transistor M 5 to facilitate the falling of the gate voltage level, further accelerating the generation of the driving current Id′.

Similarly, in a specific embodiment, the accelerating circuit 202 ′ can include a reference voltage generating unit 206 ′, for providing a reference voltage Vref′, and includes a bias current source 208 ′, biased by the voltage of the driving control node Nc′ and the reference voltage Vref′ to conduct or cut off the accelerating current Ic′. Preferably, the bias current source 208 ′ can automatically cut off the accelerating current Ic′ when the voltage of the driving control node Nc′ falls to a preset level, at which it differs from the voltage level of the reference voltage Vref′ by a specific value. In other words, the instant voltage level of the driving control node Nc′=the preset level=the reference voltage+the specific value. Other detailed structures and operations of the current driver 20 ′ are similar to those of the current driver 20 , and thus are not narrated hereinafter.

Please refer to FIG. 3A , which is a detailed circuit diagram of the current driver 20 shown in FIG. 2A according to an embodiment, utilized as an example for illustrating detailed circuits of the accelerating circuit 202 and detailed operations of the current driver 20 . In this embodiment, structures and operations of the driving circuit 204 are similar to those of the current driver 10 , and thus elements and signals with the same functions are denoted by the same symbols, and detailed operations are not narrated hereinafter.

On the other hand, in this embodiment, the bias current source 208 of the accelerating circuit 202 includes a control switch Sc, which is disposed on an accelerating current path Pc and utilized for receiving the control of the driving control node Nc to conduct or cut off the accelerating current path Pc. The control switch Sc can, for example, be realized by a control transistor M 2 , e.g. an NMOSFET transistor, including a gate receiving the reference voltage Vref, a drain coupled to a power supply 304 , and a source coupled to the driving control node Nc.

In such a configuration, whether the control transistor M 2 conducts or cuts off automatically depends on a voltage level difference between a gate voltage Vg 2 , i.e. the reference voltage Vref, and the voltage of the driving control node Nc, i.e. the gate voltage Vg 1 of the driving transistor M 1 . More specifically, when the accelerating circuit 202 and the driving circuit 204 are simultaneously activated, since the voltage level difference between the reference voltage Vref and the gate voltage Vg 1 , which is at a reference voltage level such as zero at the activation moment, is greater than a threshold voltage Vth 2 of the control transistor M 2 , that is, Vref−Vg 1 =Vref>Vth 2 , the control transistor M 2 can automatically conduct, thus generating the accelerating current Ic to charge the gate of the driving transistor M 1 , further facilitating the rising of the level of the gate voltage Vg 1 of the driving transistor M 1 , and thereby accelerating the generation of the driving current Id. Then, when the gate voltage Vg 1 continues to rise to an extent that the voltage level difference between the reference voltage Vref and the gate voltage Vg 1 is less than the threshold voltage Vth 2 , i.e. Vref−Vg 1 <Vth 2 , i.e. the threshold voltage Vth 2 in this embodiment=the specific value defined by relevant description of FIG. 2A , the control transistor M 2 is automatically cut off, stopping generating the accelerating current Ic, and no more charging the driving control node Nc.

Please continue to refer to FIG. 3A , which further illustrates a detailed structure of the reference voltage generating unit 206 according to a specific embodiment of the present invention. In this specific embodiment, the reference voltage generating unit 206 includes a plurality of transistors connected in series, e.g. two transistors M 3 and M 4 (e.g. both NMOSFET transistors in this embodiment). These transistors M 3 and M 4 are connected in series between a power supply 302 and a reference voltage level, e.g. a ground voltage level, and each with a gate and a drain connected with each other. In such a configuration, the reference voltage Vref can be determined according to a reference current Iref as follows:

Vref = Vth ⁢ ⁢ 4 + Iref Kn ⁢ ⁢ 4 + Vth ⁢ ⁢ 3 + Iref Kn ⁢ ⁢ 3 ,

wherein Kn 3 and Kn 4 are constants of a NMOS saturation region formula.

When the reference current Iref is designed to be very small, and each of the transistors M 1 ˜M 4 is designed to have a similar threshold voltage Vth, the above formula can become as follows:

V ref≈ Vth 4 +Vth 3≈2 Vth

As can be seen from the above, a cut-off condition for the control transistor M 2 is Vref−Vg 1 <Vth 2 , which under this design can be further expressed as: 2Vth−Vg 1 <Vth, or Vth<Vg 1 . In other words, with a proper design, when the gate voltage Vg 1 of the driving transistor M 1 is charged to rise to around the threshold voltage Vth, the accelerating current Ic is cut off. This automatic cutting off occurs just at the time point when the driving transistor M 1 starts conducting and generating the driving current Id.

Please refer to FIG. 3B , which is a schematic diagram of waveforms of the activation signal Ena, the gate voltage Vg 1 , the driving current Id and the accelerating current Ic of the current driver 20 shown in FIG. 3A , utilized for illustrating operating principles of the current driver 20 . As shown in FIG. 3B , when the activation signal Ena is at a low voltage level that does not activate the driving circuit 204 and the accelerating circuit 202 , the gate voltage Vg 1 is at a low voltage level, e.g. zero. In response, the driving transistor M 1 does not conduct, and the control transistor M 2 does not conduct accordingly.

Then, when the activation signal Ena is switched to a high voltage level to activate the driving circuit 204 and the accelerating circuit 202 , the voltage buffer 102 charges the gate voltage Vg 1 . Meanwhile, since a voltage level difference between the gate voltage Vg 2 of the control transistor M 2 , i.e. the reference voltage Vref, and a source voltage of the control transistor M 2 , i.e. the gate voltage Vg 1 of the driving transistor M 1 , is greater than the threshold voltage Vth 2 of the control transistor M 2 , i.e. Vg 2 −Vg 1 >Vth 2 , the control transistor M 2 conducts, generating the accelerating current Ic that flows through the accelerating current path Pc to the gate of the driving transistor M 1 , further facilitating the rise of the gate voltage Vg 1 , thereby accelerating the generation of the driving current Id.

Afterwards, the gate voltage Vg 1 continues to rise such that the voltage level difference between the gate voltage Vg 1 , i.e. the reference voltage Vref, and the source voltage, i.e. the driving transistor M 1 the gate voltage Vg 1 , of the control transistor M 2 is less than the threshold voltage Vth 2 , i.e. Vg 2 −Vg 1 <Vth 2 . Accordingly, the control transistor M 2 automatically cuts off the accelerating current path Pc, and stopping charging the gate of the driving transistor M 1 . As described above, the specific voltage level can be properly designed to be Vth 1 , i.e. a level for the driving transistor M 1 to start conducting and generating the driving current Id.

Then, the voltage buffer 102 alone continues to charge the gate of the driving transistor M 1 with a slower rate, causing the driving current Id to continue rising. Simultaneously, the negative feedback fixes the voltage Vr at the level of the input voltage Vin, keeping the level of the driving current Id at Vin/R.

By referring to the waveforms shown in FIG. 3B to observe a rising rate of the gate voltage Vg 1 of the driving transistor M 1 , it can be seen that a voltage rising rate during a conducting period of the control transistor M 2 is much higher (e.g. more than ten times) than a voltage rising rate during a cut-off period of the control transistor M 2 . Since the rising rate of the gate voltage Vg 1 can be accelerated in this embodiment, a delay time Tdelay 2 can be significantly reduced compared with the delay time Tdelay 1 shown in FIG. 1B . In other words, the driving current Id can be generated quickly.

To sum up, the accelerating circuit 202 can conduct the accelerating current path Pc when the activation signal Ena activates the driving circuit 204 , to generate the accelerating current Ic to charge the driving control node Nc, so as to accelerate generating the driving current Id. Besides, the accelerating circuit 202 can further automatically cut off the accelerating current Ic when the voltage of the driving control node Nc, i.e. the gate voltage Vg 1 , rises to a specific value, to stop charging the driving control node Nc without extra control circuits for cutting off the accelerating current Ic.

Please refer to FIG. 4A , which is a detailed circuit diagram of the current driver 20 ′ shown in FIG. 2B according to an embodiment of the present invention. In this embodiment, structures and operations of the driving circuit 204 ′ are similar to those of the current driver 10 . A main difference is that the driving transistor M 1 is replaced by a driving transistor M 5 , e.g. a PMOSFET transistor, of the driving circuit 204 ′. Therefore, during the activation period of the driving circuit 204 ′, the gate of the driving transistor M 5 starts to be discharged by the output voltage of the buffer amplifier 102 ′, so as to reduce the voltage level of the gate of the driving transistor M 5 to conduct a driving current path Pd′. Detailed functions of each element can be derived by referring to the current driver 10 , and thus are not narrated hereinafter.

Similar to the bias current source 208 shown in FIG. 3A , the bias current source 208 ′ of the accelerating circuit 202 ′ includes a control switch Sc′, which is disposed on the accelerating current path Pc′, and utilized for receiving the control of the driving control node Nc′ to conduct or cut off the accelerating current path Pc′. The control switch Sc′ can be realized by a control transistor M 6 , e.g. a PMOSFET transistor. The control transistor M 6 includes a gate receiving the reference voltage Vref′, a source coupled to power supply 404 , and a drain coupled to the driving control node Nc′.

In such a configuration, whether the control transistor M 6 conducts or cuts off automatically depends on a voltage level difference between a gate voltage Vg 6 , i.e. the reference voltage Vref′, and the voltage of the driving control node Nc′, i.e. the gate voltage Vg 5 of the driving transistor M 5 . More specifically, when the accelerating circuit 202 ′ and the driving circuit 204 ′ are simultaneously activated, since the voltage level difference between the reference voltage Vref′ and gate voltage Vg 5 , which at the activation moment is at a reference voltage level such as Vdd, is greater than a threshold voltage Vth 6 of the control transistor M 6 , i.e. Vg 5 −Vref′=Vdd−Vref′>Vth 6 , the control transistor M 6 can automatically conduct, thus generating the accelerating current Ic′ that can discharge the gate of the driving transistor M 5 , thereby accelerating the conducting of the driving transistor M 5 and the generation of the driving current Id′. Then, when gate voltage Vg 5 continues to fall to an extent that the voltage level difference between the reference voltage Vref′ and the gate voltage Vg 5 is less than the threshold voltage Vth 6 , i.e. Vg 5 −Vref′<Vth 6 , the control transistor M 6 is automatically cut off, thus stopping generating the accelerating current Ic′, and no more discharging the driving control node Nc′.

Please continue to refer to FIG. 4A , which further illustrates a detailed structure of the reference voltage generating unit 206 ′ according to a specific embodiment. In this specific embodiment, the reference voltage generating unit 206 ′ includes a plurality of transistors connected in series, e.g. two transistors M 7 and M 8 , which can both be PMOSFET transistors. The two transistors M 7 and M 8 are connected in series between a power supply 402 and a reference voltage level, which, for example, can be a voltage level Vdd higher than the ground voltage level, and each with a gate and a drain connected with each other. In such a configuration, the reference voltage Vref′ can be determined according to a reference current Iref′ as follows:

Vref ′ = Vdd - ( Vth ⁢ ⁢ 8 + Iref ′ Kn ⁢ ⁢ 8 + Vth ⁢ ⁢ 7 + Iref ′ Kn ⁢ ⁢ 7 ) ,

wherein Kn 7 and Kn 8 are constants of a PMOS saturation region formula.

When the reference current Iref′ is designed to be very small, and each of the transistors M 5 -M 8 is designed to have a similar threshold voltage Vth′, the above formula can become as follows:

V ref′= Vdd −( Vth 8+ Vth 7) Vdd− 2 Vth′.

As can be seen from the above, a cut-off condition for the control transistor M 6 is: Vg 5 −Vrer<Vth 6 , which under this design can be further expressed as: Vg 5 −(Vdd−2Vth′)<Vth′, or Vg 5 <Vdd−Vth′. In other words, with a proper design, when the gate voltage Vg 5 of the driving transistor M 5 falls by a threshold voltage Vth′ to reach a specific voltage level Vdd−Vth′, the accelerating current Ic′ is cut off. This automatic cutting off occurs just at the time point when the driving transistor M 5 starts conducting and the driving current Id′ starts generating.

Please refer to FIG. 4B , which is a schematic diagram of waveforms of an activation signal Ena′, the gate voltage Vg 5 , the driving current Id′ and the accelerating current Ic′ of the current driver 20 ′ shown in FIG. 4A , utilized for illustrating operating principles of the current driver 20 ′ shown in FIG. 4A . As shown in FIG. 4B , when the activation signal Ena′ is at a low voltage level that does not activate the driving circuit 204 ′ and the accelerating circuit 202 ′, the gate voltage Vg 5 is at a high voltage level, e.g. Vdd. In response, the driving transistor M 5 does not conduct, and the control transistor M 6 does not conduct accordingly.

Then, when the activation signal Ena′ is switched to a high voltage level to activate the driving circuit 204 ′ and the accelerating circuit 202 ′, an output terminal of the voltage buffer 102 ′ can discharge the gate of the driving transistor M 5 . Meanwhile, because a voltage level difference between a source voltage of the control transistor M 6 , i.e. the gate voltage Vg 5 of the driving transistor M 5 , and the gate voltage Vg 6 , i.e. the reference voltage Vref′, is greater than the control transistor M 6 of the threshold voltage Vth 6 , i.e. Vg 5 −Vg 6 >Vth 6 , the control transistor M 6 starts conducting, thus generating the accelerating current Ic′ that flows from the gate of the driving transistor M 5 through the accelerating current path Pc′, further facilitating the falling of the gate voltage Vg 5 , thereby accelerating the generation of the driving current Id′.

Afterwards, the gate voltage Vg 5 continues falling to reach a preset level such that the voltage level difference between the source voltage of the control transistor M 6 , i.e. the gate voltage Vg 5 of the driving transistor M 5 , and the gate voltage Vg 5 , i.e. the reference voltage Vref′, is less than the threshold voltage Vth 6 , i.e. Vg 5 −Vref′<Vth 6 . The threshold voltage Vth 6 is the specific value defined by the above description. Accordingly, the control transistor M 6 automatically cuts off the accelerating current path Pc′, and stops discharging the gate of the driving transistor M 5 . As described above, the specific voltage level can be properly designed to be Vdd−Vth′, i.e. a level for the driving transistor M 5 to start conducting and generating the driving current Id′.

Then, the voltage buffer 102 ′ alone continues to discharge the gate of the driving transistor M 5 with a slower rate, causing the driving current Id′ to continue rising. Simultaneously, the negative feedback fixes the voltage Vr at the level of the input voltage Vin, keeping the level of the driving current Id′ at Vin/Rof.

By referring to the waveforms shown in FIG. 4B to observe a falling rate of the gate voltage Vg 5 of the driving transistor M 5 , it can be seen that a voltage falling rate during a conducting period of the control transistor M 6 is much higher (e.g., more than ten times) than a voltage falling rate during a cut-off period of the control transistor M 6 . Since the falling rate of the gate voltage Vg 5 can be accelerated in this embodiment, a delay time Tdelay 2 ′ can be significantly reduced compared with that in a configuration without the accelerating circuit 202 ′. In other words, the driving current Id′ can be generated quickly.

To sum up, the accelerating circuit 202 ′ can provide the accelerating current Ic′ to discharge the driving control node Nc′ when the activation signal Ena′ activates the driving circuit 204 ′, so as to accelerate the generation of the driving current Id′. Besides, the accelerating circuit 202 ′ can further automatically cut off the accelerating current Ic′ when the voltage of the driving control node Nc′, i.e. the gate voltage Vg 5 , falls to a specific value, e.g. Vref′+Vth 6 in this embodiment, to stop discharging the driving control node Nc′, without extra control circuits for cutting off the accelerating current Ic′.

Noticeably, in the embodiments shown in FIG. 3A-3B and FIG. 4A-4B , the control switches Sc and Sc′ of the bias current source 208 and 208 ′ are both illustrated by transistors as an example. Other than a MOSFET, the transistor can be replaced with any electronic element with threshold voltage characteristics such as a MESFET, a JFET as well. Furthermore, the control switches Sc and Sc′ can be realized by any other switch devices capable of switching current paths, and the switch device can include one or more electronic elements, as long as the switch device has a first terminal which can be, directly or indirectly, coupled to the reference voltage, and a second terminal, which can be, directly or indirectly, coupled to the driving control node, and the switch can automatically conduct or cut off an accelerating current path according to a voltage level difference between the first terminal and second terminal.

Besides, one or more resistance elements of other types, e.g. with passive resistance such as a resistor, or with active resistance such as a transistor, can be added, and connected in series between the power supply and the control switch, and/or between the control switch and the driving control node. Besides, the power supplies 304 and 404 are both illustrated as current sources. However, each of the power supplies 304 and 404 can be a voltage source or any power supply circuit block capable of providing an accelerating current to flow through the control switch as well, and can be disposed inside or outside the accelerating circuit 204 and 204 ′, respectively.

Besides, similarly, in the embodiments shown in FIG. 3A-3B and FIG. 4A-4B embodiment, the transistors M 3 -M 4 and M 7 -M 8 of the reference voltage generating units 206 and 206 ′ are utilized as resistance elements. However, various different voltage generating circuits can be applied to provide the reference voltage. For example, in other embodiments, one or more resistance elements of the same or different types, e.g. with passive resistance such as a resistor, or with active resistance such as a transistor, or combinations thereof can be applied, connected in series between the power supply and the reference voltage level, with any connection node thereof for outputting the reference voltage. Besides, the power supplies 302 and 402 are both illustrated as current sources. However, each of the power supplies 302 and 402 can be a voltage source, or any other power supply circuit block capable of enabling the current Iref to flow through the reference transistors M 3 -M 4 or M 7 -M 8 as well, and can be disposed inside or outside the accelerating circuit 204 and 204 ′, respectively.

Please refer to FIG. 5A and 5B , which are detailed circuit diagrams of the current driver 20 and 20 ′ shown in FIG. 2A and 2B according to other embodiments, respectively, and are also alterations of embodiments of FIG. 3A and 4A , respectively. By comparing FIG. 3A with FIG. 5A , or FIG. 4A with FIG. 5B , it can be seen that a main difference between the two is that the bias current sources 208 and 208 ′ are added with one or more transistors (e.g. one transistor in the embodiments) respectively. The one or more transistors can be connected in series between the source of the control transistor M 2 and the gate of the driving transistor M 1 , and connected in series between the source of the control transistor M 6 and the gate of the driving transistor M 5 , respectively. Besides, the reference voltage generating units 206 and 206 ′ can have more resistance elements, e.g. transistors in the embodiments.

Noticeably, structures and related descriptions of the accelerating circuits of the above embodiments and the bias current sources and the reference voltage generating circuits thereof are only exemplary embodiments for illustrating, and realizations are not limited to specific rules. Any modifications can be made, as long as when the driving circuit is activated, the accelerating circuit is simultaneously activated to generate an accelerating current to charge or discharge a driving control node, so as to accelerate the conduction of a driving current path. Besides, under circumstances of utilizing a reference voltage generating unit and a bias current source to realize an accelerating circuit, realizations are not limited to specific rules. Any modifications can be made, as long as the reference voltage generating unit can generate voltage, and the bias current source can receive the reference voltage and the bias of a control node of the driving circuit, so as to automatically conduct or cut off an accelerating current path. Those skilled in the art should make modifications or alterations accordingly, which are not limited to detailed structures and operations shown in FIG. 2A-2B to FIG. 5A-5B .

Current driving methods of each of the above embodiments can be summarized into a current driving process 60 as shown in FIG. 6 . The current driving process 60 includes following steps:

Step 602 : Generate a driving current flowing through a driving current path to drive the current driven device 12 , and conduct or cut off the driving current path according to a voltage level of a driving control node.

Step 604 : Provide an accelerating current flowing through the driving control node to accelerate a voltage level transition of the driving control node during an activation period of starting generating the driving current, and automatically cut off the accelerating current when a voltage of the driving control node reaches a preset level.

Details of each step can be derived by referring to corresponding components of the accelerating circuits 202 , 202 ′, and are not narrated hereinafter.

To sum up, the delay time of the prior art wastes excessively long time and therefore cannot meet requirements of high frequency applications. In comparison, the above embodiments add an accelerating circuit to quickly conduct the driving current path, and therefore can shorten the delay time of the activation period of the driving circuit. Additionally, the accelerating circuit can timely and automatically cut off the accelerating current without any extra control circuits. Therefore, the above embodiments can meet requirements of various high frequency applications.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.