Method for manufacturing semiconductor device

This Application is a Divisional of application Ser. No. 12/564,989 filed on Sep. 23, 2009, which is a Continuation of Application PCT/JP2007/057156 filed on Mar. 30, 2007.

A certain aspect of the embodiments discussed herein is related to a semiconductor device.

According to common semiconductor device manufacturing techniques, multiple semiconductor elements are formed into a matrix on a semiconductor substrate such as a silicon wafer, and the semiconductor substrate is cut along scribe lines, so that semiconductor chips having respective individual semiconductor elements formed therein are obtained as semiconductor devices.

In such semiconductor devices (chips), semiconductor layers, insulating layers, and metal layers are exposed at their sections. Therefore, it is common to form a moisture resistant ring having the same layer structure as that of a multilayer interconnection structure in the semiconductor devices in the vicinity of the sections in order to prevent atmospheric moisture from entering the semiconductor devices through the sections.

FIG. 1 is a plan view of part of a semiconductor device formed on a semiconductor substrate according to the related art of the present invention. FIG. 2 is a cross-sectional view of part of the semiconductor device including a moisture resistant ring.

Referring to FIG. 1 , device regions 11 A, 11 B, 11 C, and 11 D are separated by scribe lines indicated by single-dot chain lines on a semiconductor substrate. The device regions 11 A, 11 B, 11 C, and 11 D include circuit regions forming their respective semiconductor devices inside moisture resistant rings 12 A, 12 B, 12 C, and 12 D, respectively. In the case illustrated in FIG. 1 , a circuit region (CKT) 13 is formed in the device region 11 A. A similar circuit region is also formed in each of the other device regions 11 B through 11 D.

Further, according to the configuration of FIG. 1 , protection groove parts 14 A through 14 D are formed in the device regions 11 A through 11 D, respectively, outside the corresponding moisture resistant rings 12 A through 12 D and inside the scribe lines indicated by single-dot chain lines, in order to block propagation of cracks at the time of scribing.

The individual semiconductor devices are separated in the form of semiconductor chips by cutting the silicon substrate along the scribe lines indicated by single-dot chain lines in the plan view of FIG. 1 .

FIG. 2 is a cross-sectional view of a semiconductor device 10 thus obtained.

Referring to FIG. 2 , the semiconductor device 10 is formed on a silicon substrate 15 where isolation regions 151 and a transistor 15 Tr are formed. The transistor 15 Tr is covered with a SiN film 17 A. A multilayer interconnection structure of alternate layers of interlayer insulating films 16 A, 16 B, 16 C, 16 D, 16 E, 16 F, and 16 G each formed of a silicon oxide film and silicon nitride films 17 B, 17 C, 17 D, 17 E, and 17 F is formed on the SiN film 17 A covering the transistor 15 Tr on the silicon substrate 15 .

In the case illustrated in FIG. 2 , in the interlayer insulating film 16 A, via patters 16 a R of a material such as W are continuously formed in contact with the surface of the silicon substrate 15 in correspondence to the moisture resistant ring 12 A, and via plugs 16 a of a material such as W are formed in contact with silicide layers 15 c and 15 d covering diffusion regions 15 a and 15 b , respectively, of the transistor 15 Tr in the circuit region 13 .

Further, in the interlayer insulating film 16 B, a Cu pattern 16 b R is continuously formed in contact with the via patterns 16 a R by a single damascene process in correspondence to the moisture resistant ring 12 A, and Cu interconnection patterns 16 b are formed in contact with the via plugs 16 a also by a single damascene process in the circuit region 13 .

Further, in the interlayer insulating film 16 C, a Cu pattern 16 c R is continuously formed in contact with the Cu pattern 16 b R below by a single or dual damascene process in correspondence to the moisture resistant ring 12 A, and Cu interconnection patterns 16 c having via plugs are formed in contact with the Cu interconnection patterns 16 b also by a single or dual damascene process in the circuit region 13 .

Further, in the interlayer insulating film 16 D, a Cu pattern 16 d R is continuously formed in contact with the Cu pattern 16 c R below by a single or dual damascene process in correspondence to the moisture resistant ring 12 A, and Cu interconnection patterns 16 d having via plugs are formed in contact with the Cu interconnection patterns 16 c also by a single or dual damascene process in the circuit region 13 .

Further, in the interlayer insulating film 16 E, a Cu pattern 16 e R is continuously formed in contact with a Cu pattern below (not graphically illustrated) by a dual damascene process in correspondence to the moisture resistant ring 12 A, and Cu interconnection patterns 16 e having via plugs are formed in contact with Cu interconnection patterns (not graphically illustrated) also by a dual damascene process in the circuit region 13 .

Further, in the interlayer insulating film 16 F, a Cu pattern 16 f R is continuously formed in contact with the Cu pattern 16 e R below by a dual damascene process in correspondence to the moisture resistant ring 12 A, and Cu interconnection patterns 16 f having via plugs are formed in contact with the Cu interconnection patterns 16 e also by a dual damascene process in the circuit region 13 .

Further, in the interlayer insulating film 16 G, a W pattern 16 g R is continuously formed in contact with the Cu pattern 16 f R below by a damascene process in correspondence to the moisture resistant ring 12 A, and a Cu via plug 16 g is formed in contact with the corresponding Cu interconnection pattern 16 f also by a damascene process in the circuit region 13 .

Here, the Cu interconnection patterns 16 b through 16 f and the Cu patterns 16 b R through 16 f R are covered with a barrier metal film of Ta or the like, and the W via plugs 16 a and 16 g and the W patterns 16 a R and 16 g R are covered with a barrier film of TiN or the like.

Further, on the interlayer insulating film 16 G, an Al pattern 18 A sandwiched between adhesion films of a Ti/TiN structure is formed in contact with the W pattern 16 g R in correspondence to the moisture resistant ring 12 A, and a pad electrode 18 B having a similar structure is formed on and in contact with the via plug 16 g.

Further, the Al pattern 18 A and the pad electrode 18 B are covered with a silicon oxide film 18 deposited by high-density plasma CVD on the interlayer insulating film 16 G. Further, a passivation film 19 of a SiN film is formed on the silicon oxide film 18 . An opening 19 A is formed in the passivation film 19 and the silicon oxide film 18 so as to expose the pad electrode 18 B.

According to the configuration of FIG. 2 , scribing is performed with a dicing saw at the left side end in FIG. 2 as indicated by an arrow. The protection groove 14 A illustrated above with reference to FIG. 1 is formed outside the moisture resistant ring 12 A in order to block propagation of cracks at the time of scribing.

On the other hand, according to the semiconductor device 10 of the configuration of FIG. 2 , its left side end in FIG. 2 is exposed to the atmosphere. Therefore, as illustrated in FIG. 3 , moisture (H 2 O) enters the portions of the interlayer insulating films 16 A through 16 F outside the moisture resistant ring 12 A, but the moisture resistant ring 12 A prevents this moisture from entering the circuit region 13 . Accordingly, there is a problem in that the moisture resistant ring 12 A, on which a heavy workload is imposed, is susceptible to corrosion. If there is a defect in part of the moisture resistant ring 12 A, moisture enters the semiconductor device 10 through the part. In FIG. 3 , such a defect is in the Cu pattern 16 c R of the moisture resistant ring 12 A circled with a broken line.

This problem of the workload on the moisture resistant ring 12 A is conspicuous particularly in the case of using low dielectric constant films of low density, or so-called Low-K films, as the interlayer insulating films 16 A through 16 F.

FIG. 4 is a diagram illustrating a semiconductor device that reduces such a workload on a moisture resistant ring according to the related art of the present invention. In FIG. 4 , the same elements as those described above are referred to by the same reference numerals, and a description thereof is omitted.

Referring to FIG. 4 , the protection groove part 14 A is formed so deep as to reach the surface of the silicon substrate 15 , and the SiN passivation film 19 is formed to continuously cover the surface of the protection groove part 14 A.

As a result, the interlayer insulating films 16 A through 16 F and the interlayer insulating film 16 G have their respective ends continuously covered with the SiN passivation film 19 , so as to reduce a substantial workload on the moisture resistant ring 12 A.

The following are examples of the related art of the present invention: Japanese Laid-open Patent Publication No. 2004-47575, Japanese Laid-open Patent Publication No. 2004-134450, Japanese Laid-open Patent Publication No. 2004-79596, Japanese Laid-open Patent Publication No. 2003-273043, Japanese Laid-open Patent Publication No. 2004-119468, Japanese Laid-open Patent Publication No. 2005-217411, Japanese Laid-open Patent Publication No. 2005-260059, Japanese Laid-open Patent Publication No. 2004-296904, and Japanese Laid-open Patent Publication No. 2006-114723.

According to an aspect of the present invention, a semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including a plurality of interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO 2 film; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose a surface of the substrate; a protection film continuously covering an upper surface of the layered body except for an electrode pad on the multilayer interconnection structure, and sidewall surfaces and a bottom surface of the protection groove part; and an interface film including Si and C as principal components and formed between the protection film and the sidewall surfaces of the protection groove part.

According to another aspect of the present invention, a semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose a surface of the substrate; and a first metal mask pattern and a second metal mask pattern extending along an outer-side edge and an inner-side edge, respectively, of the protection groove part on an upper surface of the layered body.

According to yet another aspect of the present invention, a semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure; a moisture resistant ring extending continuously in the layered body so as to surround a device region where an active element is formed; a protection groove part formed continuously along and outside the moisture resistant ring in the layered body so as to expose a surface of the substrate; and a protection film covering an upper surface of the layered body except for an electrode pad on the multilayer interconnection structure and covering an inner-edge-side sidewall surface of the protection groove part continuously from the upper surface of the layered body on an internal side of the protection groove part, the protection film being partially removed in a region on and outside an outer-edge-side sidewall surface of the protection groove part.

The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and not restrictive of the invention, as claimed.

FIG. 1 is a plan view of part of a semiconductor device formed on a semiconductor substrate according to related art;

FIG. 2 is a cross-sectional view of part of the semiconductor device according to the related art;

FIG. 3 is a cross-sectional view of the part of the semiconductor device according to the related art;

FIG. 4 is a cross-sectional view of part of another semiconductor device according to the related art;

FIG. 5 is a cross-sectional view of a semiconductor device according to a first embodiment;

FIGS. 6A through 6F are diagrams illustrating a process for manufacturing the semiconductor device of FIG. 5 according to the first embodiment;

FIG. 7 is a cross-sectional view of a variation of the semiconductor device of FIG. 5 according to the first embodiment;

FIGS. 8A through 8C are diagrams illustrating a process for manufacturing a semiconductor device according to a second embodiment;

FIG. 9 is a diagram illustrating a variation of the second embodiment;

FIG. 10 is a diagram illustrating another variation of the second embodiment;

FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment;

FIG. 12 is a cross-sectional view of a variation of the semiconductor device of FIG. 11 according to the third embodiment;

FIG. 13 is a cross-sectional view of another variation of the semiconductor device of FIG. 11 according to the third embodiment;

FIG. 14 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 15 is a cross-sectional view of a variation of the semiconductor device of FIG. 14 according to the fourth embodiment; and

FIG. 16 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

As described above, according to the configuration of FIG. 4 , a substantial workload on the moisture resistant ring 12 A may be reduced, so that the reliability of the semiconductor device may be expected to increase.

However, forming the structure of FIG. 4 is accompanied by formation of the deep groove 14 A in the layered body formed of the interlayer insulating films 16 A through 16 G, which may cause a problem in patterning accuracy particularly in the case of performing pattering using a resist pattern as a mask.

Further, the SiN passivation film 19 , which is a film storing stress, has the problem of being likely to be reduced in adhesion and removed particularly if the interlayer insulating films 16 A through 16 F are low dielectric constant films.

This SiN passivation film 19 may be formed by depositing a silicon oxide film by high-density plasma CVD. In particular, however, if the interlayer insulating films 16 A through 16 F are organic low dielectric constant films or low dielectric constant films including many organic groups, the interlayer insulating films 16 A through 16 F may be eroded by an oxygen atmosphere at the time of film deposition. Therefore, it is considered difficult to apply such a technique.

Further, according to the configuration of FIG. 4 , if the passivation film 19 is formed of a SiN film storing stress, a fracture at the time of scribing may reach the circuit region 13 inside the moisture resistant ring 12 A through the passivation film 19 so as to reduce the reliability of the semiconductor device.

Preferred embodiments of the present invention are explained below with reference to accompanying drawings.

[a] First Embodiment

FIG. 5 illustrates a semiconductor device 20 according to a first embodiment of the present invention.

Referring to FIG. 5 , the semiconductor device 20 is formed on a silicon substrate 25 where isolation regions 25 I and a transistor 25 Tr are formed. The transistor 25 Tr is covered with a SiN film 27 A. A layered body including a multilayer interconnection structure of alternate layers of interlayer insulating films 26 A, 26 B, 26 C, 26 D, 26 E, 26 F, and 26 G and etching stopper films 27 B, 27 C, 27 D, 27 E, and 27 F of SiN or SiC is formed on the SiN film 27 A covering the transistor 25 Tr on the silicon substrate 25 .

In the case illustrated in FIG. 5 , in the interlayer insulating film 26 A, via patters 26 a R of a material such as W are continuously formed in contact with the surface of the silicon substrate 25 in correspondence to a moisture resistant ring 22 A, and via plugs 26 a of a material such as W are formed in contact with silicide layers 25 c and 25 d covering diffusion regions 25 a and 25 b , respectively, of the transistor 25 Tr in a circuit region 23 surrounded by the moisture resistant ring 22 A.

Further, in the interlayer insulating film 26 B, a Cu pattern 26 b R is continuously formed in contact with the via patterns 26 a R by a single damascene process in correspondence to the moisture resistant ring 22 A, and Cu interconnection patterns 26 b are formed in contact with the via plugs 26 a also by a single damascene process in the circuit region 23 .

Further, in the interlayer insulating film 26 C, a Cu pattern 26 c R is continuously formed in contact with the Cu pattern 26 b R below by a dual damascene process in correspondence to the moisture resistant ring 22 A, and Cu interconnection patterns 26 c having via plugs are formed in contact with the Cu interconnection patterns 26 b by a single or dual damascene process in the circuit region 23 .

Further, in the interlayer insulating film 26 D, a Cu pattern 26 d R is continuously formed in contact with the Cu pattern 26 c R below by a single or dual damascene process in correspondence to the moisture resistant ring 22 A, and Cu interconnection patterns 26 d having via plugs are formed in contact with the Cu interconnection patterns 26 c by a dual damascene process in the circuit region 23 .

Further, in the interlayer insulating film 26 E, a Cu pattern 26 e R is continuously formed in contact with a Cu pattern below (not graphically illustrated) by a dual damascene process in correspondence to the moisture resistant ring 22 A, and Cu interconnection patterns 26 e having via plugs are formed in contact with Cu interconnection patterns (not graphically illustrated) also by a dual damascene process in the circuit region 23 .

Further, in the interlayer insulating film 26 F, a Cu pattern 26 f R is continuously formed in contact with the Cu pattern 26 e R below by a dual damascene process in correspondence to the moisture resistant ring 22 A, and Cu interconnection patterns 26 f having via plugs are formed in contact with the Cu interconnection patterns 26 e also by a dual damascene process in the circuit region 23 .

Further, in the interlayer insulating film 26 G, a W pattern 26 g R is continuously formed in contact with the Cu pattern 26 f R below by a damascene process in correspondence to the moisture resistant ring 22 A, and a Cu via plug 26 g is formed in contact with the corresponding Cu interconnection pattern 26 f also by a damascene process in the circuit region 23 .

Here, the Cu interconnection patterns 26 b through 26 f and the Cu patterns 26 b R through 26 f R are covered with a barrier metal film such as a Ta film or a Ta/TaN layered film, and the W via plugs 26 a and 26 g and the W patterns 26 a R and 26 g R are covered with a barrier film of TiN or the like.

Further, on the interlayer insulating film 26 G, an Al pattern 28 A sandwiched between adhesion films of a Ti/TiN structure is formed in contact with the W pattern 26 g R in correspondence to the moisture resistant ring 22 A, and a pad electrode 28 B having a similar structure is formed on and in contact with the via plug 26 G. In the case illustrated in FIG. 5 , the interlayer insulating film 26 G is formed of a silicon oxide film.

Further, the Al pattern 28 A and the pad electrode 28 B are covered with a silicon oxide film 28 deposited by high-density plasma CVD on the interlayer insulating film 26 G. Further, a passivation film 29 of a SiN film is formed on the silicon oxide film 28 by, for example, plasma CVD. An opening 29 A is formed in the passivation film 29 and the silicon oxide film 28 so as to expose the pad electrode 28 B.

As the interlayer insulating films 26 A through 26 F, hydrocarbon insulating films commercially available under the name of Flare or SiLK (registered trademark), organic or inorganic siloxane films, and their porous films may be used. The interlayer insulating films 26 A through 26 F may be formed by plasma CVD or coating. The interlayer insulating films 26 A through 26 D are formed to be, for example, approximately 200 nm to 400 nm in thickness, and the interlayer insulating films 26 E and 26 F are formed to be, for example, approximately 400 nm to 600 nm in thickness.

In this embodiment, a protection groove part 24 A that reaches the surface of the silicon substrate 25 is formed continuously along and outside the moisture resistant ring 22 A in the layered body in the same manner as the protection groove part 14 A of FIG. 4 . The silicon oxide film 28 and the passivation film 29 continuously cover an inner-side (inner-edge-side) sidewall surface 24 Aa, a bottom surface 24 Ab, and an outer-side (outer-edge-side) sidewall surface 24 Ac of the protection groove part 24 A.

The protection groove part 24 A is formed by performing dry etching on a layered body of the interlayer insulating films 26 A through 26 G stacked in layers until the surface of the silicon substrate 25 is exposed using a resist pattern as a mask.

Further, according to this embodiment, a SiC interface film 28 I of 5 nm to 200 nm in thickness is formed by plasma CVD between the silicon oxide film 28 and the inner-side sidewall surface 24 Aa, the bottom surface 24 Ab, and the outer-side sidewall surface 24 Ac of the protection groove part 24 A.

Formation of this interface film 28 I prevents damage to the low dielectric constant interlayer insulating films 26 A through 26 F exposed at the inner-side sidewall surface 24 Aa or outer-side sidewall surface 24 Ac of the protection groove part 24 A at the time of forming the silicon oxide film 28 over the inner-side sidewall surface 24 Aa, the bottom surface 24 Ab, and the outer-side sidewall surface 24 Ac of the protection groove part 24 A.

The interface film 28 I is not limited in composition to SiC, and may be replaced with films whose principal components are Si and C, such as a SiCH film, a SiOC film, and SiOCH film, as long as these films prevent damage to the low dielectric constant interlayer insulating films 26 A through 26 F at the time of forming the silicon oxide film 28 .

In the case of forming the interface film 28 I of a SiC film, the interface film 28 I may be formed by, for example, plasma CVD where tetramethylsilane is fed as a material and plasma-excited at a substrate temperature of 350° C. to 400° C.

Thus, according to this embodiment, the surfaces, that is, the inner-side sidewall surface 24 Aa, the bottom surface 24 Ab, and the outer-side sidewall surface 24 Ac, of the protection groove part 24 A are covered continuously with the interface film 28 I before forming the silicon oxide film 28 on the surfaces of the protection groove part 24 A by high-density plasma CVD. This prevents the surfaces of the protection groove part 24 A from being damaged by oxygen radicals and ions at the time of forming the silicon oxide film 28 . Since the interface film 28 I is formed under an oxygen-poor condition, no substantial damage is caused to the exposed end surfaces of the interlayer insulating films 26 A through 26 F in the protection groove part 24 A.

Further, forming the silicon oxide film 28 under the SiN passivation film 29 makes it possible to prevent separation of the SiN passivation film 29 , which is prone to store stress.

In the case illustrated in FIG. 5 , the left end in FIG. 5 is scribed, so that the (left) end surface is exposed to the atmosphere. A large part of atmospheric moisture, however, is blocked by the SiN passivation film 29 in the protection groove part 24 A, so that a workload on the moisture resistant ring 22 A is significantly reduced.

A description is given below, with reference to FIGS. 6A through 6G , of a process for manufacturing the semiconductor device 20 .

Referring to FIG. 6A , a layered body of the interlayer insulating films 26 A through 26 G stacked in layers is formed on the silicon substrate 25 where the transistor (active element) 25 Tr is formed. A layered structure of the W or Cu patterns 26 a R through 26 g R is formed in correspondence to the moisture resistant ring 22 A in the layered body. The Al pattern 28 A is formed on top of the layered body. Further, a layered structure of the W or Cu patterns 26 a through 26 g is formed in correspondence to a multilayer interconnection structure in the circuit region 23 in the layered body.

In the process of FIG. 6B , the protection groove part 24 A is formed outside the moisture resistant ring 22 A by dry etching using a gas mixture of a CF-based gas, O 2 , Ar, etc., as an etching gas, so as to expose the silicon substrate 25 . In the process of FIG. 6B , the dry etching is performed with the surface of the layered body except for a region where the protection groove part 24 A is to be formed being protected with a resist mask.

Further, in the process of FIG. 6B , with the formation of the protection groove part 24 A, the interlayer insulating films 26 A through 26 F are exposed to the atmosphere in the protection groove part 24 A. As a result, the interlayer insulating films 26 A through 26 F, even before scribing, absorb moisture outside the moisture resistant ring 22 A. In the process of FIG. 6C , however, the structure of FIG. 6B is dehydrated, and the SiC interface film 28 I of the above-described thickness is formed on the structure of FIG. 6B by the above-described plasma CVD process. If the interface film 28 I is less than or equal to 5 nm in thickness, the interface film 28 I fails to produce its effect as an interface film. If the interface film 28 I is more than or equal to 200 nm in thickness, this results in an unnecessarily long process time.

Next, in the process of FIG. 6D , the silicon oxide film 28 of, for example, 1200 nm to 1500 nm in thickness is formed on the structure of FIG. 6C using silane and oxygen as materials at plasma power of approximately 700 W and at a substrate temperature of approximately 400° C. while applying a substrate bias of approximately 4 kW. Further, in the process of FIG. 6E , the SiN passivation film 29 of 500 nm in thickness is formed on the structure of FIG. 6D using silane and ammonia as materials at plasma power of approximately 750 W and at a substrate temperature of approximately 400° C.

Further, in the process of FIG. 6F , the opening 29 A is formed in the SiN passivation film 29 , the silicon oxide film 28 , and the interface film 28 I so as to expose the electrode pad 28 B.

Further, after the process of FIG. 6F , a silicon wafer (on which the semiconductor device 20 is formed) is scribed along scribing lines as illustrated in FIG. 1 , so that the semiconductor device 20 of FIG. 5 is produced.

If the SiN passivation film 29 has sufficient adhesion, the silicon oxide film 28 may be formed before formation of the protection groove part 24 A and the SiN passivation film 29 may be formed on and in direct contact with the interface film 28 I in the protection groove part 24 A as illustrated in FIG. 7 after formation of a groove that reaches the substrate 25 in correspondence to the protection groove part 24 A.

[b] Second Embodiment

Next, a description is given, with reference to FIGS. 8A through 8C , of a second embodiment of the present invention. In FIGS. 8A through 8C , elements corresponding to those described above are referred to by the same reference numerals, and a description thereof is omitted.

In the first embodiment, a resist process is employed to form the protection groove part 24 A by dry etching in the process of FIG. 6B . In the case of forming the protection groove part 24 A, dry etching may take such a long time that a resist pattern may not withstand the long dry etching particularly if the semiconductor device has a large number of interlayer insulating films.

This embodiment is directed to such a case where the number of interlayer insulating films in a multilayer interconnection structure is so large that it takes a long time to form the protection groove part 24 A.

Referring to FIG. 8A , Al patterns 28 C and 28 D are formed on the topmost layer of the silicon oxide film 26 G in such a manner as to define a region where the protection groove part 24 A is to be formed. The Al patterns 28 C and 28 D are formed simultaneously with the Al pattern 28 A and the pad electrode 28 B using the same mask. Then, using the Al patterns 28 C and 28 D as a hard mask, the layered body of the interlayer insulating films 26 A through 26 G is subjected to dry etching between the Al patterns 28 C and 28 D, so that the protection groove part 24 A is formed.

According to this embodiment, in the next process of FIG. 8B , the structure of FIG. 8A is dehydrated, and the interface film 28 I is formed in the same manner as in the process of FIG. 6C . Further, in the process of FIG. 8C , the passivation film 29 is formed on the interface film 28 I in the same manner as in the process of FIG. 6E . FIG. 8C illustrates a state where the semiconductor device is further scribed.

According to this configuration, as described above, the protection groove part 24 A is formed with stability, so that it is possible to avoid problems such as exposure of the moisture resistant ring 22 A due to the sideward advancement of a dry etching process for forming the protection groove part 24 A.

In the case described with reference to FIGS. 8A through 8C , the SiN passivation film 29 is in direct contact with the interface film 28 I. This embodiment, however, is not limited to this particular case, and is effective also in the case where the same silicon oxide film formed by high-density plasma CVD as the silicon oxide film 28 is interposed between the interface film 28 I and the SiN passivation film 29 .

Thus, forming the Al patterns 28 C and 28 D does not increase the number of masks, and thus does not complicate the manufacturing process of the semiconductor device.

FIG. 9 illustrates a variation of the process of FIG. 8A .

Referring to FIG. 9 , according to this variation, the Al pattern 28 A is also used as the Al pattern 28 D of FIG. 8A . This makes it possible to reduce chip size as indicated by double-headed arrow W in FIG. 9 compared with the case of FIG. 8A .

FIG. 10 illustrates another variation of the process of FIG. 8A .

Referring to FIG. 10 , according to this variation, another moisture resistant ring 22 B is formed on the outer side of the protection groove part 24 A. The moisture resistant ring 22 B is the same as the moisture resistant ring 22 A, and is formed of Cu or W patterns 26 a P, 26 b P, 26 c P, 26 d P, 26 e P, 26 f P, and 26 g P stacked in layers. The Al pattern 28 C is formed as the topmost pattern of the moisture resistant ring 22 B.

Also according to this configuration, it is possible to control the shape of the protection groove part 24 A with accuracy by performing dry etching using the Al patterns 28 A and 28 C as a mask.

This separate moisture resistant ring 22 B may be formed simultaneously with the moisture resistant ring 22 A without an increase in the number of processes. Further, the moisture resistant ring 22 B is present on the outer side of the protection groove part 24 A. This additional moisture resistant ring structure checks the progress of the interface propagation of cracks.

[c] Third Embodiment

FIG. 11 illustrates a semiconductor device 40 according to a third embodiment of the present invention. In FIG. 11 , elements corresponding to those described above are referred to by the same reference numerals, and a description thereof is omitted.

Referring to FIG. 11 , according to this embodiment, the SiN passivation film 29 directly covers the inner-side sidewall surface 24 Aa and the bottom surface 24 Ab of the protection groove part 24 A, but a portion of the SiN passivation film 29 covering the outer-side sidewall surface 24 Ac of the protection groove part 24 A is removed by performing the same dry etching process as performed to form the protection groove part 24 A using a mask pattern formed by slightly offsetting mask data used to form the protection groove part 24 A in the scribe line direction. Further, as a result of this dry etching process, a step part 24 a is formed on the outer-side sidewall surface 24 Ac of the protection groove part 24 A in the case of FIG. 11 .

This configuration prevents cracks from entering the circuit region 23 inside the moisture resistant ring 22 A through the SiN passivation film 29 storing strain at the time of separating the semiconductor device 40 by a scribing process.

Further, according to this embodiment, it is possible to avoid an increase in the number of masks by carrying out the process of removing the SiN passivation film 29 in the protection groove part 24 A simultaneously with the process of forming the opening 29 A that exposes the pad electrode 28 B. In this case, etching substantially stops in the opening 29 A when the pad electrode 22 B becomes exposed, while further progressing only on the outer-side sidewall surface 24 Ac of the protection groove part 24 A.

In the case of FIG. 11 , the interlayer insulating films 26 A through 26 F are formed of silicon oxide films, and the SiN passivation film 29 is in direct contact with the interlayer insulating films 26 A through 26 F in the protection groove part 24 A. As described above with reference to FIG. 5 or FIG. 7 , if the interlayer insulating films 26 A through 26 F are low dielectric constant films lower in dielectric constant than SiO 2 , it is preferable to interpose the silicon oxide film 28 and the interface film 28 I or the interface film 28 I between the SiN passivation film 29 and the inner-side sidewall surface 24 Aa and the bottom surface 24 Ab in the protection groove part 24 A.

FIG. 12 illustrates a variation of the configuration of FIG. 11 , where the SiN passivation film 29 remains on a portion of the outer-side sidewall surface 24 Ac of the protection groove part 24 A.

This embodiment may include such a case.

Further, FIG. 13 illustrates another variation of the configuration of FIG. 11 , where a portion of the SiN passivation film 29 left at the time of etching the outer-side sidewall surface 24 Ac of the protection groove part 24 A forms a projection 29 a.

This embodiment may include such a case.

[d] Fourth Embodiment

FIG. 14 illustrates a semiconductor device 60 according to a fourth embodiment of the present invention. In FIG. 14 , elements corresponding to those described above are referred to by the same reference numerals, and a description thereof is omitted.

Referring to FIG. 14 , according to this embodiment, the SiN passivation film 29 continuously covers the inner-side sidewall surface 24 Aa, the bottom surface 24 Ab, and the outer-side sidewall surface 24 Ac of the protection groove part 24 A, and an opening 29 B is continuously formed on the outer side of the protection groove part 24 A in the layered body of the interlayer insulating films 26 A through 26 G so as to surround the protection groove part 24 A. The opening 29 B is formed simultaneously with the opening 29 A.

According to this configuration, even if cracks are generated in the SiN passivation film 29 in the scribing process of the semiconductor device 60 , the opening 29 B prevents the cracks from propagating to enter the circuit region inside the moisture resistant ring 22 A.

It is seen from FIG. 14 , which illustrates the pre-scribing state of the semiconductor device 60 , that moisture has entered part of the layered body on the outer side of the protection groove part 24 A from the opening 29 B. This part is also exposed to the atmosphere at the time of scribing to allow entry of moisture. However, the SiN passivation film 29 prevents this moisture from entering the inside of the protection groove part 24 A, so that a workload on the moisture resistant ring 22 A is significantly reduced.

In the case of FIG. 14 , the interlayer insulating films 26 A through 26 F are formed of silicon oxide films, and the SiN passivation film 29 is in direct contact with the interlayer insulating films 26 A through 26 F in the protection groove part 24 A. As described above with reference to FIG. 5 or FIG. 7 , if the interlayer insulating films 26 A through 26 F are low dielectric constant films lower in dielectric constant than SiO 2 , it is preferable to interpose the silicon oxide film 28 and the interface film 28 I or the interface film 28 I between the SiN passivation film 29 and the inner-side sidewall surface 24 Aa, the bottom surface 24 Ab, and the outer-side sidewall surface 24 Ac in the protection groove part 24 A.

FIG. 15 illustrates a variation of the configuration of FIG. 14 , where an Al pattern 28 E is formed simultaneously with the Al pattern 28 A and the pad electrode 28 B on the layered body in correspondence to an opening 29 C so as to surround the protection groove part 24 A.

According to this variation, the Al pattern 28 E is formed at a position corresponding to where the opening 29 C is to be formed. Therefore, at the time of forming the opening 29 C, dry etching for forming the opening 29 C stops at the Al pattern 28 E and is prevented from getting deep inside the layered body.

Further, no moisture enters the part of the layered body on the outer side of the protection groove part 24 A before scribing.

[e] Fifth Embodiment

FIG. 16 illustrates a semiconductor device 80 according to a fifth embodiment of the present invention. In FIG. 16 , elements corresponding to those described above are referred to by the same reference numerals, and a description thereof is omitted.

Referring to FIG. 16 , according to this embodiment, the protection groove part 24 A formed outside the moisture resistant ring 22 A in the layered body formed of the stacked layers of the interlayer insulating films 26 A through 26 G on the silicon substrate 25 is continuously covered with the SiN passivation film 29 , and a resin layer 30 of water soluble resin or the like is formed on the SiN passivation film 29 so as to fill in the protection groove part 24 A.

According to this embodiment, the silicon wafer is scribed with the resin layer 30 formed. Accordingly, the energy of cracks is absorbed by the resin layer 30 so as to prevent the cracks from propagating to the circuit region 23 .

Application of the resin layer 30 is not limited to the configuration of FIG. 16 , and the resin layer 30 may be applied to any of the configurations of the above-described embodiments.

According to an aspect of the present invention, a method of manufacturing a semiconductor device is provided that includes forming a groove in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO 2 film and including a multilayer interconnection structure, the groove being between a moisture resistant ring and a scribe line and reaching a surface of a semiconductor substrate, the moisture resistant ring surrounding the multilayer interconnection structure in the layered body; forming an interface film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the interface film along the sidewall surfaces and the bottom surface of the groove.

According to an aspect of the present invention, a method of manufacturing a semiconductor device is provided that includes forming a groove in a layered body including a multilayer interconnection structure, the groove being between a moisture resistant ring and a scribe line and reaching a surface of a semiconductor substrate, the moisture resistant ring surrounding the multilayer interconnection structure in the layered body; and forming a protection film covering sidewall surfaces and a bottom surface of the groove using a metal pattern formed on the multilayer interconnection structure as a mask.

According to an aspect of the present invention, a method of manufacturing a semiconductor device is provided that includes forming a groove in a layered body including a multilayer interconnection structure, the groove being between a moisture resistant ring and a scribe line and reaching a surface of a semiconductor substrate, the moisture resistant ring surrounding the multilayer interconnection structure in the layered body; forming a protection film covering a first sidewall surface, a bottom surface, and a second sidewall surface of the groove, the first sidewall surface being closer to the moisture resistant ring than the second sidewall surface is, the second sidewall surface being closer to the scribe line than the first sidewall surface is; and at least partially removing a part of the protection film covering the second sidewall surface of the groove.

According to an aspect of the present invention, a method of manufacturing a semiconductor device is provided that includes forming a groove in a layered body including a multilayer interconnection structure, the groove being between a moisture resistant ring in the multilayer structure and a scribe line and reaching a surface of a semiconductor substrate; forming a protection film covering sidewall surfaces and a bottom surface of the groove; and removing the protection film on an upper surface of the layered body on an outer side of the groove.

According to an aspect of the present invention, a protection groove part so deep as to reach the surface of a substrate is formed outside a moisture resistant ring in a semiconductor device having a layered body forming a multilayer interconnection structure on the substrate. This protects part of the semiconductor device inside the moisture resistant ring from cracks at the time of dicing. In this configuration, covering at least the inner-side sidewall surface of the protection groove part with a protection film prevents entry of moisture into the semiconductor device through the inner-side sidewall surface of the protection groove part.

According to an aspect of the present invention, even if the multilayer interconnection structure is formed of low dielectric constant interlayer insulating films stacked in layers, covering the (inner-side and outer-side) sidewall surfaces of the protection groove part with an interface film including Si and C as principal components avoids the problem of erosion of the end faces of the interlayer insulating films exposed at the sidewall surfaces of the protection groove part at the time of forming the protection film.

According to an aspect of the present invention, a desired protection groove part is stably formed in the layered body using a metal pattern formed on the surface of the layered body as a hard mask even if the protection groove part is so deep as to reach the surface of the substrate.

According to an aspect of the present invention, removing the protection film on the outer-side sidewall surface of the protection groove part and/or on the outer side of the protection groove part prevents entry of cracks into the semiconductor device through the protection film storing strain at the time of separating the semiconductor device by a scribing process, thus improving the manufacturing yield of semiconductor devices.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority or inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.