Semiconductor integrated circuit, radio communication device and time to digital converter

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-204695 filed on Sep. 13, 2010, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor integrated circuit, a radio communication device and a time to digital converter.

A radio communication device represented by a cellular phone can include a PLL (Phase Lock Loop) circuit for generating a local oscillator (hereinafter referred to as LO) signal. In recent years, an ADPLL (All Digital Phase Lock Loop) circuit where whole processing is performed by digital circuits is often implemented.

In the ADPLL circuit, a time to digital converter (hereinafter referred to as TDC) for converting a phase difference between the generated LO signal and a reference signal outputted from the outside to a digital value is used. In a general conventional TDC, delay elements such as inverters are connected in series. However, the delay time may vary due to a variation of semiconductor manufacturing, process and so on. Therefore, it is necessary to normalize phase difference information by performing complex operations. As a result, there are problems that the volume of the PLL becomes large and the consumption power increases.

FIG. 1 is a schematic block diagram of a radio communication device 100 according to one embodiment.

FIG. 2 is a schematic block diagram of a semiconductor integrated device 200 .

FIG. 3 is a flowchart showing an example of the processing operation of the semiconductor integrated circuit 200 of FIG. 2 .

FIG. 4 is a waveform showing an example of the reference signal REF, the signal ACC 1 and the signal ACC 2 .

FIG. 5 is a schematic block diagram showing an example of the internal configuration of the TDC 24 .

FIG. 6 is a waveform showing an example of the delay signals dly[ 1 ] to dly[n] and the reference signal REF.

FIG. 7 is a circuit configuration showing an internal configuration of the PPG 32 .

FIG. 8 is a circuit configuration showing a specific example of the PPG 32 .

In general, according to one embodiment, a semiconductor integrated device includes a digitally controlled oscillator, a counter, a time to digital converter, an adder, and a control signal generator. The digitally controlled oscillator is configured to generate an oscillation signal having a frequency depending on a first digital signal. The counter is configured to count the number of pulses of the oscillation signal to output a counted value as a second digital signal in synchronization with a reference signal. The time to digital converter is configured to generate a third digital signal corresponding to a phase difference between the oscillation signal and the reference signal. The adder is configured to generate a fourth digital signal by adding the second digital signal to the third digital signal. The control signal generator is configured to generate the first digital signal based on a value obtained by accumulating a frequency command word in synchronization with the reference signal and the fourth digital signal in such a manner that the frequency of the oscillation signal approaches a predetermined frequency. The time to digital converter includes a frequency-divider, a plurality of impedance elements, and a phase difference detector. The frequency-divider is configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals. The plurality of impedance elements is configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal. The phase difference detector is configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals.

Embodiments will now be explained with reference to the accompanying drawings.

(First Embodiment)

FIG. 1 is a schematic block diagram of a radio communication device 100 according to one embodiment. The radio communication device 100 of FIG. 1 is mounted on a cellular phone, for example. The radio communication device 100 has an antenna 1 , a switch (SW) 2 , a signal transmitter 3 and a signal receiver 4 . Note that, the radio communication device 100 may include only one of the signal transmitter 3 and the signal receiver 4 .

The antenna 1 transmits or receives a radio signal. The switch 2 controls whether the antenna 1 transmits or receives the radio signal. The signal transmitter 3 processes an input radio signal inputted from a baseband LSI (Large Scale Integrated circuit) etc. (not shown), and outputs the processed radio signal to the antenna 1 . The signal receiver 4 processes the radio signal received by the antenna 1 , and outputs the processed signal to the outside.

The signal transmitter 3 has an input signal processing circuit 5 , a first semiconductor integrated circuit 6 , a modulation circuit 7 and a power amplifier (PA) 8 . The input signal processing circuit 5 processes a signal inputted from the outside. The first semiconductor integrated circuit 6 generates an LO signal. Based on this LO signal, the modulation circuit 7 modulates the output signal from the input signal processing circuit 5 . The power amplifier 8 amplifies the output signal from the modulation circuit 7 , and outputs the amplified signal to the antenna 1 .

The signal receiver 4 has an LNA (Low Noise Amplifier) 9 , a second semiconductor integrated circuit 10 , a demodulation circuit 11 and an output signal processing circuit 12 . The LNA 9 amplifies the radio signal received by the antenna 1 . The second integrated circuit 10 generates an LO signal. Based on this LO signal, the demodulation circuit 11 demodulates the radio signal amplified by the LNA 9 . The output signal processing circuit 12 processes the demodulated signal and outputs the processed signal to the outside.

When the first and the second semiconductor integrated circuits 6 and 10 can generate the LO signals having low phase noise, it is possible to encode audio/video signals in a predetermined format to transmit them, or to decode signals received by the antenna 1 to reproduce original audio/video signals stably without error. Therefore, in the present embodiment, the LO signal is generated as follows.

FIG. 2 is a schematic block diagram of a semiconductor integrated device 200 capable of used as the first and the second semiconductor integrated circuits 6 and 10 . A reference signal REF and a frequency command word FCW are inputted to the semiconductor integrated device 200 . The reference signal REF is, for example, generated by a crystal (not shown). Although the frequency Fref of the reference signal REF is not so high (for example, 13 MHz), there is little phase noise therein.

The semiconductor integrated circuit 200 of FIG. 2 generates the LO signal having a frequency higher than the frequency Fref of the reference signal REF, more specifically, generates the LO signal having the frequency of Fref*FCW as a target frequency. The present embodiment shows an example where Fref=13 MHz, FCW=185, and the LO signal having the frequency Flo of 2405 MHz (=13 MHz*185, approximately 2.4 GHz) is generated. This frequency Flo is used in a certain radio communication.

The semiconductor integrated circuit 200 of FIG. 2 has a digitally controlled oscillator (hereinafter referred to as DCO) 21 , a flip-flop (FF) 22 , a counter 23 , a TDC 24 , an adder 25 , an accumulator 26 , and a control signal generator 27 .

The DCO 21 generates the LO signal whose frequency depends on an oscillator tuning word OTW (first digital signal). The DCO 21 is implemented by controlling a plurality of varactor capacitors in two values. As the oscillator tuning word OTW is larger, the frequency Flo of the LO signal becomes lower.

The reference signal REF is inputted to a data terminal D of the flip-flop 22 , and the LO signal is inputted to a clock terminal thereof. The flip-flop 22 holds the value of the reference signal REF in synchronization with the LO signal.

The counter 23 has an accumulator 23 a . The LO signal is inputted to the accumulator 23 a as a clock, and the accumulator 23 a counts the number of the pulses of the LO signal. The output signal of the flip-flop 22 is inputted to the counter 23 as a clock. In synchronization with the output signal of the flip-flop 22 , the counter 23 outputs the count value of the accumulator 23 a as a signal CNTV (second digital signal).

The value of the signal CNTV corresponds to an integer part of a ratio Flo/Fref. For example, when the frequency Flo of the LO signal equals to the target frequency 2405 MHz, the accumulator 23 a counts up by “1” at 2405 MHz, while the counter 23 outputs the count value of the accumulator 23 a at Fref=13 MHz. Therefore, the value of the signal CNTV increases by “185” (=2405 MHz/13 MHz). The value of “185” equals to the frequency command word FCW. On the other hand, when the frequency Flo is higher (lower) than 2405 MHz, the value of the signal CNTV increases by a value larger (smaller) than “185”.

The TDC 24 measures a phase difference between the LO signal and the reference signal Fref with an accuracy smaller than a cycle of the LO signal to output the measured value as a signal d (third digital signal). More specifically, the TDC 24 generates the signal d by comparing phases of a plurality of delay signals having delay times different from each other obtained by delaying the LO signal with the phase of the reference signal Fref. The signal d corresponds to a decimal part of the ratio Flo/Fref.

As described below, the TDC 24 of the present embodiment generates the delay signals not by serially-connected delay elements, but by generating a frequency-divided signal by a frequency divider and voltage-dividing the frequency-divided signal by resistances. Therefore, it is unnecessary to normalize variation of the delay elements, and thus, the signal d can be generated by a small size and low consumption power circuit.

The adder 25 adds the signal CNTV to the signal d and outputs the added value as a signal ACC 2 (fourth digital signal). The signal ACC 2 corresponds to the ratio Flo/Fref.

The reference signal REF is inputted to the accumulator 26 as a clock. The accumulator 26 accumulates the frequency command word FCW in synchronization with the reference signal REF to output the accumulated value as a signal ACC 1 . Therefore, the signal ACC increases by the frequency command word FCW in synchronization with the reference signal REF.

The control signal generator 27 has, for example, a subtractor 27 a , a loop filter 27 b and a multiplier 27 c . The subtractor 27 a outputs a difference value obtained by subtracting the value of the signal ACC 2 from the value of the signal ACC 1 to the loop filter 27 b . The loop filter 27 b smooths the difference value to remove the high-frequency component therefrom. The multiplier 27 c multiplies the output value of the loop filter 27 b by a predetermined coefficient K to output the oscillator tuning word OTW.

The control signal generator 27 controls the oscillator tuning word OTW so that the frequency Flo of the LO signal approaches the target frequency Fref*FCW based on the signals ACC 1 and ACC 2 . More specifically, when the frequency Flo of the LO signal is higher (lower) than 2405 MHz, the signal ACC 2 becomes larger (smaller) than the signal ACC 1 . Then, the control signal generator 27 controls the oscillator tuning word OTW so that the frequency Flo becomes lower (higher).

FIG. 3 is a flowchart showing an example of the processing operation of the semiconductor integrated circuit 200 of FIG. 2 . Firstly, the counter 23 counts the number of the pulses of the LO signal in synchronization with the reference signal REF to generate the signal CNTV corresponding to the integer part of the ratio Flo/Fref (Step S 1 ). Furthermore, the TDC 24 detects the phase difference between the LO signal and the reference signal REF to generate the signal d corresponding to the decimal part of the ratio Flo/Fref (Step S 2 ).

Then, the control signal generator 27 generates the oscillator tuning word OTW based on the signal ACC 1 obtained by accumulating the frequency command word FCW in synchronization with the reference signal REF and the signal ACC 2 obtained by adding the integer part of the ratio Flo/Fref to the decimal part thereof. More specifically, when ACC 1 >ACC 2 , because the frequency Flo is lower than the target frequency FCW*Fref (Step S 3 —YES), the control signal generator 27 generates the frequency command word FCW so that the frequency of the LO signal generated by the DCO 21 becomes higher (Step S 4 ). On the other hand, when ACC 1 <ACC 2 , because the frequency Flo is higher than the target frequency FCW*Fref (Step S 5 —YES), the control signal generator 27 generates the frequency command word FCW so that the frequency of the LO signal generated by the DCO 21 becomes lower (Step S 6 ). Then, the DCO 21 generates the LO signal whose frequency depends on the generated frequency command word FCW.

By repeating such a feedback operation, the LO signal is controlled in such a manner that the frequency Flo of the LO signal approaches the target frequency FCW*Fref.

FIG. 4 is a waveform showing an example of the reference signal REF, the signal ACC 1 and the signal ACC 2 . Note that, FIG. 4 shows an example where both of the signals ACC 1 and ACC 2 have eight bits. Furthermore, although the signal ACC 2 is a digital signal, the signal ACC 2 is represented as a decimal value in order to simplify the explanation.

As shown in FIG. 4 , the value of the signal ACC 1 generated by the accumulator 26 increases by “185” which is a value of the frequency command word FCW in synchronization with the reference signal REF. For example, the value of the signal ACC 1 is “0” at time t 0 , “185” at time t 1 and “114” (=“185”+“185”−“256”) at time t 2 , respectively.

On the other hand, as stated above, the signal ACC 2 corresponds to the ratio Flo/Fref. For example, during time t 1 to t 2 , the value of the signal ACC 2 is “185.1”, which is larger than the value of the signal ACC 1 of “185”. This means that the frequency Flo of the LO signal is slightly higher than the target frequency 2405 MHz. In this case, the control signal generator 27 generates the oscillator tuning word OTW so that the frequency of the LO signal becomes lower. Here, the integer part “185” of “185.1” is detected by the counter 23 and the decimal part “0.1” thereof is detected by the TDC 24 .

Contrarily, during time t 2 to t 3 , the value of the signal ACC 2 is “113.9”, which is smaller than the value of the signal ACC 1 of “114”. This means that the frequency Flo of the LO signal is slightly lower than the target frequency 2405 MHz. In this case, the control signal generator 27 generates the oscillator tuning word OTW so that the frequency of the LO signal becomes higher. Here, the integer part “113” of “113.9” is detected by the counter 23 and the decimal part “0.9” thereof is detected by the TDC 24 .

Note that, because the loop filter 27 b is included in the control signal generator 27 , magnitude relationship between the signal ACC 1 and the signal ACC 2 is not reflected immediately.

Hereinafter, an internal configuration of the TDC 24 , which is one of the characteristic features of the present embodiment, will be explained in detail. FIG. 5 is a schematic block diagram showing an example of the internal configuration of the TDC 24 . The TDC 24 has a frequency-divider (DIV) 31 , a passive phase generator (hereinafter referred to as PPG) 32 , and a phase difference detector 35 having “n” flip-flops 331 to 33 n (one of them is represented as flip-flop 33 k ) and an encoder 34 .

The frequency-divider 31 generates four-phase frequency-divided signals LO 1 to LO 4 having phases different from each other by “90” degree, for example. The frequency-divider 31 is implemented by a quadrature VCO, a ring oscillator, or a polyphase filter, for example. Note that, the frequency divider 31 may generate not only four-phase frequency-divided signals but also eight- or sixteen-phase frequency-divided signals.

The PPG 32 further divides the four-phase frequency-divided signals LO 1 to LO 4 into “m” to generate 4*m(=“n”)-phase delay signals dly[ 1 ] to dly[n]. Note that, the delay signal dly[ 1 ] is the LO signal itself. Furthermore, the phase difference, namely, the delay time between the delay signals dly[ 1 ] to dly[n] and the delay signal dly[ 1 ] becomes larger in this order. An internal configuration of the PPG 32 will be explained below with reference to FIG. 7 .

The phase difference detector 35 outputs the signal d by comparing the reference signal REF with each of the delay signals dly[ 1 ] to dly[n]. More specifically, the delay signal dly[k] is inputted to a data terminal D of the corresponding flip-flop 33 k , and the reference signal REF is inputted to a clock terminal thereof. The flip-flop 33 k holds the value of the delay signal dly[k] in synchronization with the reference signal REF to output the hold value as the signal q[k]. Furthermore, the encoder 34 generates the signal d indicative of the phase difference between the LO signal and the reference signal REF to output it based on the signals q[1] to q[n].

FIG. 6 is a waveform showing an example of the delay signals dly[ 1 ] to dly[n] and the reference signal REF. In FIG. 6 , the delay signal dly[ 1 ], namely, the LO signal rises up at time t 10 , and subsequently, the delay signals dly[ 2 ] and dly[ 3 ] rise up at time t 20 and time t 30 , respectively.

Here, it is assumed that the reference signal REF rises up at time t 25 which is between time t 20 and time t 30 , the flip-flop 331 to 33 n hold the values of the delay signals dly[ 1 ] to dly[n] as the signals q[1] to q[n] at time t 25 , respectively. As a result, the signal q[2] is set to be high, and the signal q[3] is set to be low. The encoder 34 detects that the value switches from high to low at between the signal q[2] and the signal q[3], based on which, the encoder 34 outputs the signal d indicative of the phase difference between the LO signal and the reference signal REF.

FIG. 7 is a circuit configuration showing an internal configuration of the PPG 32 . The PPG 32 of FIG. 7 generates the delay signals dly[ 1 ] to dly[ 4 m] by further dividing the four frequency-divided signals LO 1 to LO 4 generated by the frequency-divider 31 of FIG. 5 into “m”.

The PPG 32 has “ 4 m ” resistances R 1 to R 4 m . The resistances R 1 to Rm are connected in series between the frequency-divided signal LO 1 and the frequency-divided signal LO 2 . The resistances Rm+1 to R 2 m are connected in series between the frequency-divided signal LO 2 and the frequency-divided signal LO 3 . The resistances R 2 m +1 to R 3 m are connected in series between the frequency-divided signal LO 3 and the frequency-divided signal LO 4 . The resistances R 3 m +1 to R 4 m are connected in series between the frequency-divided signal LO 4 and the frequency-divided signal LO 1 . Here, it is preferable that the delay times of the delay signals dly[ 1 ] to dly[ 4 m] are set at regular intervals in order to reduce spurious component outputted from the semiconductor integrated circuit 200 . Therefore, it is preferable that the resistance value becomes larger as the resistance is connected closer to the frequency-divided signal. For example, R 1 >R 2 >. . . <Rm−1<Rm.

The delay signal dly[k+1] is outputted from the connection node of the resistance Rk (k=“1” to 4 m −1) and the resistance Rk+1, and the delay signal dly[ 1 ] is outputted from the connection node of the resistance R 4 m and the resistance R 1 . For example, the delay signal dly[ 2 ] is obtained by dividing the voltage of the frequency-divided signals LO 1 and LO 2 by the resistances R 1 to Rm. The delay time of the delay signal dly[ 2 ] obtained by the voltage division has a value between the delay time of the frequency-divided signal LO 1 and the delay time of the frequency-divided signal LO 2 . The other delay signals are similarly arranged.

Note that, each of the following pairs shows the same signal: the frequency-divided signal LO 1 and the delay signal dly[ 1 ]; LO 2 and dly[m+1]; LO 3 and dly[ 2 m +1]; and LO 4 and dly[ 3 m +1].

By appropriately setting the resistance values of the resistances R 1 to R 4 m , the delay times of the delay signals dly[ 1 ] to dly[ 4 m] can be set at regular intervals.

FIG. 8 is a circuit configuration showing a specific example of the PPG 32 . The PPG 32 of FIG. 8 is an example where m=4 in the PPG 32 of FIG. 7 . Hereinafter, conditions required for the PPG 32 of FIG. 8 will be obtain in order to set the delay times of the delay signals dly[ 1 ] to dly[ 16 ] at regular intervals.

The resistance values of the resistances R 1 to R 16 must be symmetrically set between two arbitrary frequency-divided signals. Therefore, the resistance value of eight resistances closest to the frequency-divided signals is defined as r 1 , and the resistance value of the other resistances is defined as r 2 .

Further, because the LO signal and the frequency-divided signals LO 1 to LO 4 generated therefrom have a high frequency of about 2.4 GHz, the waveform can be approximated not by a rectangle but by a sine wave. Additionally, considering that the frequency-divided signals LO 1 to LO 4 have phases different from each other by “90” degrees, the following equations (1) to (4) can be established.

LO1=sin ωt  (1)

LO2=cos ωt  (2)

LO3=−sin ωt  (3)

LO4=−cos ωt  (4)

Here, ω=2π*Flo. For example, the delay signals dly[ 2 ] to dly[ 4 ] have a voltage obtained by dividing the voltage of the frequency-divided signals LO 1 and LO 2 by the resistances R 1 to R 4 . Accordingly, dly[ 1 ] to dly[ 5 ] can be expressed by the following equations (5) to (9).

Here, A, α, and β can be expressed by the following equations (10) to (12).

Then, the resistance values r 1 and r 2 are set to satisfy the following equation (13).

r 1=√2 *r 2  (13)

Accordingly, α=22.5 degrees and β=67.5 degrees, by which the delay signals dly[ 1 ] to dly[ 5 ] can have phases shifted from each other by “22.5” degrees. As a result, the delay signals dly[ 1 ] to dly[ 16 ] have phases different from each other by 360/16 degrees, and the delay times are set at regular intervals. Therefore, the spurious component outputted from the semiconductor integrated circuit 200 can be reduced.

As stated above, the TDC 24 according to the present embodiment firstly generates a plurality of frequency-divided signals by frequency-dividing the LO signal by the frequency-divider 31 . Then, the delay signals of the LO signal are generated by voltage-dividing the frequency-divided signals by a plurality of resistances. Therefore, it is unnecessary to normalize the phase difference information by complex operations. Accordingly, the circuit for normalizing is not needed, thereby downsizing the volume of the circuit and reducing the consumption power. Further, because the normalizing operation is not needed, it is possible to shorten the delay time of the feedback loop. As a result, Fref*FCW can be set to be a value equal to or more than 100 MHz to generate the LO signal (oscillation signal) having a high frequency (for example, 2.4 GHz). Furthermore, by adjusting the resistances in the TDC 24 , the delay times of the delay signals can be set at regular intervals.

In FIGS. 7 and 8 , the resistances may be replaced by general impedance elements such as capacitors, inductors, and transistors the gate of which is biased to a predetermined potential.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fail within the scope and spirit of the inventions.