Level shifter design

The present invention relates generally to digital circuits and more particularly to level shifting circuits for shifting digital signals between two different voltage levels.

The field-effect-transistor (FET, or transistor) uses either electrons (in N-channel FET) or holes (in P-channel FET) for conduction. The four terminals of a transistor are source, gate, drain, and body (substrate). In transistors, the drain-to-source current flows via a conducting channel that connects the source region to the drain region. The conductivity is controlled by the electric field that is produced when a voltage is applied between the gate and source terminals, denoted by V gs . Usually, the body terminal is connected to the highest or lowest voltage within the circuit. The body terminal and the source terminal are sometimes connected together since the source is also sometimes connected to the highest or lowest voltage within the circuit. Normally, an input signal is applied to the gate terminal of a transistor, and an output signal is connected to the source or the drain terminal of a transistor. A first terminal of a transistor can be either its source terminal or its drain terminal, and a second terminal of a transistor is the drain or source terminal of the transistor.

A digital circuit accepts input signals and produces output signals, both could be represented by certain allowed voltages. A flip-flop (a latch) is a circuit that has two stable states and can be used to store state information. The latch circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs.

In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground (or some other common reference point), although other standards exist. The range of voltage levels that represents each state depends on the logic family being used. An active-high signal represents a binary digit of 1, or asserted state of a logical condition, by the higher of two voltages. An active-low signal represents a binary digit of 0, or asserted state of a logical condition, by the lower of two voltages. In three-state logic, an output device can also be high impedance. This is not a logic level, but means that the output is not controlling the state of the connected circuit. A level shifter connects one digital circuit that uses one logic level to another digital circuit that uses another logic level.

Manufacturers have developed different processes to produce Integrated Circuits (IC) that operate at different voltage levels. Some common IC operating voltage levels include 5V+/−10%, 3.3V+/−10%, and 2.5V+/−10%. In using decreased voltage levels, manufacturers limit the adverse effects of power dissipation (e.g., heat), while continuing to allow for ever increasing IC densities.

Nevertheless, when a new, low-voltage IC process technology emerges, it is often desirable for the new technology to be able to operate with existing high-voltage levels. IC process technologies, and their respective operating voltages, are often defined by the gate-oxide breakdown voltage between the terminals of a device (e.g., a transistor) implemented using the particular process technology. Consequently, a potential problem with interfacing circuitry implemented in a low-voltage process technology with a voltage that exceeds device limits is that, one or more devices implemented in the low-voltage process may experience damage, either temporary or permanent, that can hinder the circuit's ability to perform its desired function.

A voltage level shifter can function as a high-voltage tolerant output driver providing the ability to regulate an input voltage V IN that may exceed the maximum operating voltage of the process technology. Without high-voltage tolerant output driver, exceeding the device voltage limits dictated by the process technology may result in damage of devices.

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1( a )-( c ) depict illustrative block diagrams of exemplary embodiments of level shifter circuits in various details;

FIGS. 2( a )-( d ) depict illustrative block diagrams of exemplary embodiments of level shifter circuits in various details, comprising an additional transistor compared to FIGS. 1( a )-( c ); and

FIGS. 3( a )-( d ) depict illustrative block diagrams of exemplary embodiments of level shifter circuits in various details, wherein the level shifter circuits comprising a first component level shifter circuit and a second component level shifter circuit which may receive two different inputs.

The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Illustrative embodiments will be discussed with respect to a level shifter design, which are implemented using nMOS transistors, pMOS transistors, invertors, and other basic logic circuits. Those of skill in the art will readily recognize that there are many variations which implement equivalent functions and the illustrative embodiments are made for illustrative purpose only.

FIG. 1( a ) illustrates a block diagram of an illustrative embodiment of a level-shifter circuit. The circuit comprises a first inverter X 1 , a capacitor C 1 , a resistor R 1 , and a latch circuit “latch”. The first inverter X 1 , operates with a potential difference between a first voltage V 1 and a second voltage V 2 , and has an input terminal connected to the input signal node V 0 of the level shifter, and an output terminal connected to a first terminal of the capacitor C 1 . The capacitor C 1 has a second terminal connected to an input node of the latch. The resistor R 1 has a first terminal connected to a third voltage node V 3 and a second terminal connected to the input node of the latch. Finally, the latch circuit operates under a potential difference between a fourth voltage V 4 and a fifth voltage V 5 , and has an output node connected to the output signal node Vout of the level shifter. The input signal V 0 has a voltage value in the range of between V 1 and V 2 , while the output signal Vout of the level shifter has a voltage value in the range of between V 4 and V 5 . Some of the voltage levels V 1 to V 5 may be the same depending on the application being used for. Some of the voltages V 1 to V 5 may be active high or active low voltage signals. For illustrative purpose, the value of V 5 is smaller than the value of V 4 , and the value of V 2 is smaller than the value of V 1 . An abstract block diagram showing only the related operating voltage signals V 1 to V 5 , an input voltage signal V 0 , and an output voltage signal Vout is also presented in FIG. 1( a ) for representing the illustrative level shifter.

FIG. 1( b ) is an illustrative circuit diagram showing more details of an exemplary arrangement of a level shifter according to the first embodiment of FIG. 1( a ). The latch circuit “latch” of FIG. 1( a ) is illustratively implemented by a loop of two inverters X 2 and X 3 in FIG. 1( b ). An output terminal of the inverter X 2 is connected to an input terminal of the inverter X 3 while an output terminal of the inverter X 3 is connected to an input terminal of the inverter X 2 . The inverters X 2 and X 3 are driven with a potential difference between a voltage V 4 =VH and a voltage V 5 =VL, where VH is larger than VL. The Resistor R 1 has a first terminal connected to the voltage V 3 =VH as well. Furthermore, the inverter X 1 is driven with a potential difference between a voltage V 1 =Vh and a ground voltage V 2 . VIP is the input signal node of the level shifter and DRV_P is the output signal node of the level shifter.

Those of skill in the art will readily recognize that there are many variations which implement equivalent functions and the illustrative embodiments are made for illustrative purpose only. The latch can be implemented by other flip-flop circuits other than the two inverter loop.

The operation of the level shifter shown in FIG. 1( b ) is as follows. As set out above, one terminal of the latch circuit comprised of the inverters X 2 and X 3 is indicated by the node VX and the other terminal of the latch circuit is connected to the node DRV_P. Further, the output terminal of the inverting element X 1 is indicated by a node Va. VC 1 denotes a potential difference across the capacitor C 1 .

Let it be assumed that, at an initial state, a voltage Vss lower than a circuit threshold value of the inverter X 1 is inputted as an input signal VIP to the inverter X 1 . In this case, a voltage Vh is outputted from the inverter X 1 and a potential on the node Va becomes a voltage Vh. Since the node VX is set to a voltage VH, a potential difference VC 1 across the capacitor C 1 becomes a potential |Vh−VH|, and the potential of DRV_P is of the voltage VL.

Next, assume a voltage Vcc higher than the circuit threshold value of the inverter X 1 is inputted as an input signal VIP to the inverter X 1 . Then, from the inverter X 1 a voltage V 2 (in this case, ground) is outputted and the node Va is set to a voltage ground=V 2 . When a potential on the node Va varies from the voltage Vh to a voltage V 2 , a potential difference VC 1 across the capacitor C 1 is momentarily held to |Vh−VH| and, due to a capacitive coupling, a potential on the node Va causes a transition on Vx to be VH−(Vh−V 2 )=VH−Vh, since V 2 =ground voltage.

If, here, the respective voltages VH, VL, Vh and ground voltage are so set as to make a potential on the node VX lower than the threshold voltage of X 1 , that is, VH−Vh<(VH+VL)/2, then the potential on the node VX and potential on the node DRV_P are inverted, so that the node VX is set to VL and the node DRV_P is set to a voltage VH. When the potential on the node VX and potential on the DRV_P are inverted and become stable, the potential difference VC 1 becomes VL.

Furthermore, assume a voltage Vss lower than a circuit threshold value of the inverter X 1 is next inputted as an input signal VIP to the inverter X 1 . Then, from the inverter X 1 a voltage Vh is outputted and the node Va is set to a voltage Vh. When a potential on the node Va varies from the ground voltage V 2 to a voltage Vh, a potential difference VC 1 across the capacitor C 1 is held to be VL, and, due to a capacitive coupling, a potential on the node Va causes a transition on Vx to be VL+Vh.

If, here, the respective voltages VH, VL, Vh and ground voltage are so set as to make a potential on the node VX lower than the threshold voltage of X 3 , that is, VL+Vh<(VH+VL)/2, then the potential on the node VX and potential on the node DRV_P are inverted, so that the node VX is set to VH and the node DRV_P is set to a voltage VL. When the potential on the node VX and potential on the DRV_P are inverted and become stable, the potential difference VC 1 becomes VH−Vh. The purpose of R 1 is to define the input of the latch to high level during high-impedance input.

The limitation of the voltage levels of FIG. 1( b ) is as below:

FIG. 1( c ) is an illustrative circuit diagram showing more details of an exemplary arrangement of a level shifter according to the first embodiment of FIG. 1( a ). The inverter X 1 is driven with a potential difference between a voltage Vh and a ground voltage. The resistor R 1 has a first terminal connected to the ground voltage as well. The latch circuit “latch” of FIG. 1( a ) is further illustratively implemented by a loop of two inverters X 2 and X 3 in FIG. 1( c ). An output terminal of the inverter X 2 is connected to an input terminal of the inverter X 3 while an output terminal of the inverter X 3 is connected to an input terminal of the inverter X 2 . The inverters X 2 and X 3 are driven with a potential difference between a voltage Vh and a ground voltage. Furthermore, VIN is the input signal node of the level shifter and DRV_N is the output signal node of the level shifter. The circuit in FIG. 1( c ) operates similarly as the circuit in FIG. 1( b ) does, which can be readily recognized by those of skill in the art. The purpose of R 2 is to define the input of the latch to high level during high-impedance input.

The limitation of the voltage levels of FIG. 1( c ) is as below:

The detail operations of FIG. 1( b ) and FIG. 1( c ) are summarized in Table 1 below.

FIG. 2( a ) illustrates a block diagram of an illustrative embodiment of a level-shifter circuit with a different reference voltage level by connecting to an additional voltage extension transistor. Compared to the illustrative block diagram in FIG. 1( a ), the circuit in FIG. 2( a ) comprises an additional P-transistor MFP 1 , wherein the voltage V 5 signal node of the latch of the level shifter of FIG. 1( a ) is connected to a first terminal of the P-transistor while a second terminal of the P-transistor is connected to a sixth voltage signal, and a gate of the P-transistor is connected to a seventh voltage signal. With the voltage extension transistor P-transistor, the new level shifter could operate under 7 different voltage signal connections V 1 to V 7 , with V 0 as the input voltage and Vout as the output voltage, which can be illustrated by an abstract block diagram also shown in FIG. 2( a ).

FIG. 2( c ) illustrates another exemplary block diagram of an illustrative embodiment of a level-shifter circuit with a different reference voltage level. Compared to the illustrative block diagram in FIG. 1( a ), the circuit in FIG. 2( c ) comprises an additional N-transistor MFN 1 , wherein the voltage V 4 signal of the latch of the level shifter of FIG. 1( a ) is connected to a first terminal of the N-transistor while a second terminal of the N-transistor is connected to a sixth voltage signal, and a gate of the N-transistor is connected to a seventh voltage signal. With the voltage extension transistor N-transistor, the new level shifter could operate under 7 different voltage signal connections V 1 to V 7 , with V 0 as the input voltage and Vout as the output voltage, which can be illustrated by an abstract block diagram also shown in FIG. 2( c ).

The level shifters in FIG. 2( a ) and FIG. 2( c ) can be illustratively implemented by circuits shown in FIG. 2( b ) and FIG. 2( d ) respectively. In both FIG. 2( b ) and FIG. 2( d ), the latch circuit of FIG. 2( a ) and FIG. 2( c ) is implemented by two inverters, wherein an output terminal of the first inverter X 2 is connected to an input terminal of the second inverter X 3 while an output terminal of the second inverter is connected to an input terminal of the first inverter. Other voltage signals of the circuit shown in FIG. 2( b ) are similar to the voltage signals in circuit FIG. 1( b ). Other voltage signals of the circuit shown in FIG. 2( d ) are similar to the voltage signals in circuit FIG. 1( c ). FIG. 2( b ) can be viewed as adding to the circuit FIG. 1( b ) a P-transistor to have a different reference voltage level for the circuit in FIG. 2( b ) to operate. FIG. 2( d ) can be viewed as adding to the circuit FIG. 1( c ) an N-transistor to have a different reference voltage level for the circuit in FIG. 2( d ) to operate.

FIG. 3( a ) illustrates a block diagram of an illustrative embodiment of a level-shifter circuit which comprises two component level shifters, wherein a first component level shifter is as shown in FIG. 2( a ) and a second component level shifter is as shown in FIG. 2( c ). The first component level shifter in FIG. 3( a ) is an embodiment shown in FIG. 2( a ) comprising the inverter XP 1 , latch 1 , capacitor C 1 , resistor R 1 , and an extension transistor MFP 1 , with corresponding voltage signals VP 1 to VP 7 . The second component level shifter in FIG. 3( a ) is an embodiment shown in FIG. 2( c ) comprising inverters XN 1 , latch 2 , capacitor C 2 , resistor R 2 , and an extension transistor MFN 1 , with corresponding voltage signals VN 1 to VN 7 . The new level shifter which could operate with two different input voltages V 11 and V 12 to the two component level shifters respectively, and produce one output voltage DRV. Furthermore, a first inverter X 7 with an input terminal connected to an output voltage signal node DRV_P of the first component level shifter and an output terminal, driven by voltages V 8 and V 9 . The output of inverter X 7 is connected to a gate of a P-transistor MP, wherein MP has its first terminal connected a voltage V 12 , and its second terminal connected to the first output voltage of the device DRV. Moreover, a second component level shifter as shown in FIG. 2( c ) is connected to the second input voltage V 12 and the second component level shifter has an output node DRV_N, which operates according to the operations shown in FIG. 2( c ). The output signal node DRV_N is connected to a second inverter X 8 which is driven by voltages V 10 and V 11 . The output node of the second inverter X 8 is connected to a gate terminal of an N-transistor MN, wherein MN has its first terminal connected a voltage V 13 , and its second terminal connected to the first output voltage of the device DRV.

FIG. 3( b ) illustrates a circuit diagram of a more detailed exemplary embodiment of a level-shifter circuit shown in FIG. 3( a ) comprising two component level shifters. The first component level shifter in FIG. 3( b ) is an embodiment shown in FIG. 2( b ) comprising inverters XP 1 , XP 2 , XP 3 , capacitor C 1 , resistor R 1 , and an extension transistor MFP 1 , with corresponding voltage signals VP 1 to VP 7 . The second component level shifter in FIG. 3( b ) is an embodiment shown in FIG. 2( d ) comprising inverters XN 1 , XN 2 , XN 3 , capacitor C 2 , resistor R 2 , and an extension transistor MFN 1 , with corresponding voltage signals VN 1 to VN 7 . Other inverters X 7 and X 8 , transistors MP and MN are the same as shown in FIG. 3( a ). The same circuit diagram is also shown in another exemplary embodiment in FIG. 3( d ). Furthermore, the two input voltage nodes V 11 and V 12 of FIG. 3( a ) are connected together to form one voltage signal V 11 =V 12 in FIG. 3( b ), while V 11 and V 12 have an non-overlapping phase in FIG. 3( d ).

FIG. 3( b ) and FIG. 3( d ) are shown only as exemplary circuits of a level shifter illustratively shown in FIG. 3( a ). Those of skill in the art will readily recognize that there are many variations which implement equivalent functions and the illustrative embodiments are made for illustrative purpose only. The latch can be implemented by other flip-flop circuits other than the two inverter loop as shown in the two component level shifters in FIG. 3( b ) and FIG. 3( d ).

Further circuit techniques can be applied to the exemplary circuits shown in FIG. 3( b ) and FIG. 3( d ) to form other different embodiments with equivalent functions. One such illustrative transformation is shown in FIG. 3( c ), where the two component level shifters share one inverter XP 1 =XN 1 , since the two inverters XP 1 and XN 1 in FIG. 3( b ) operate under the exact same condition with the same input and therefore their outputs should be the same. Those of skill in the art will readily recognize that there are many variations which implement equivalent functions.

Illustrative level shifter embodiments can be used in various system settings. FIG. 3( b ) shows the output of the level shifter DRV is driving a capacitor load. Other load combinations of capacitor, resistor, and inductors can be driven by the output of the level shifter as shown in FIG. 3( d ).

The level shifter circuits can be disposed in currently available technology such as in a semiconductor device or on a printed circuit board. The level shifter circuits can be disposed in future available technology as well.

Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the features and functions discussed above can be implemented in software, hardware, or firmware, or a combination thereof. As another example, it will be readily understood by those skilled in the art that may be varied while remaining within the scope of the present disclosure.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.