Motherboard having time delay circuit for delaying PSON signal

1. Technical Field

The present disclosure relates to motherboards having a time delay circuit for delaying a power supply on (PSON) signal.

2. Description of Related Art

In a computer system, the micro ATX and ATX specifications recommend a 24-pin main connector interface for power supply. This interface incorporates standard +5V, +12V, 3.3V, 5V standby, and soft-power signals. Proper implementation of PSON#, 5VSB, and PW-OK is required for an ATX-compliant power supply.

PSON# is an active low Transistor-Transistor Logic (TTL) signal that turns on all of the main power rails including 3.3V, 5V, −5V, 12V, and −12V power rails. When this signal is held high by the PC board or left open-circuited, outputs of the power rails should not deliver current and should be held at a zero potential with respect to ground. Power should be delivered to the rails only if the PSON# signal is held at ground potential.

Sometimes, the power button of the computer system is triggered repeatedly in a very short time interval, and the power rails of the power supply do not have time to power down fully, which may cause power up sequence failure.

Therefore, a motherboard having a circuit for delaying the PSON signal to prevent the above described power up/down failure is desired.

FIG. 1 illustrates a block diagram of a motherboard according to an exemplary embodiment, showing the motherboard connected to a power supply unit.

FIG. 2 illustrates a circuit diagram of the motherboard of FIG. 1 .

Referring to FIGS. 1 and 2 , a motherboard 100 , according to an exemplary embodiment, includes a time delay circuit 10 and a motherboard power supply connector 30 . The motherboard power supply connector 30 is connected to a power supply unit 200 . The power supply unit 200 , such as an ATX power supply unit, provides voltages to work the motherboard 100 .

The time delay circuit 10 has an input terminal 101 configured for receiving a power supply on (PSON#) signal from the motherboard 100 . The PSON# signal is retrieved from a Super I/O of the motherboard 100 . The time delay circuit 10 has an output terminal 102 connected to the motherboard power supply connector 30 .

In this embodiment, the time delay circuit 10 includes a time delay chip U 1 , an electrical switch Q 1 , resistors R 1 -R 5 and capacitors C 1 -C 3 . Pin function descriptions of the time delay chip U 1 are listed in the following table.

The capacitor C 2 and the resistor R 5 are connected in series and are both grounded. The SENSE pin is connected to a first node between the capacitor C 2 and the resistor R 5 and is connected to the input terminal 101 of the time delay circuit 10 via the first node and the resistor R 2 to receive the PSON# signal.

The VDD pin is connected to a power supply terminal V 3 DU. The GND pin is grounded. The MR pin is connected to ground via the resistor R 3 and the capacitor C 1 in series in that order. The power supply terminal V 3 DU is connected to a second node between the resistor R 3 and the capacitor C 1 . The RESET pin is connected to a control terminal of the electrical switch Q 1 . The resistor R 4 is connected between a third node and the power supply terminal V 3 DU. The third node is between the control terminal of the electrical switch Q 1 and the RESET pin. The CT pin is grounded via the capacitor C 3 . A relationship between the capacitance C of the capacitor C 3 and the time delay T is characterized by the following equation: C=(T−0.5×0.001)×175, where a unit of the capacitance C is nanofarad (nF) and a unit of the time delay T is second. Generally, the time delay T is set to be greater than 0.5 seconds. For example, C=150 nF, and T=C/175+0.5×0.001=150/175+0.5×0.001=0.858(s).

The control terminal of the electrical switch Q 1 is connected to the RESET pin. A first terminal of the electrical switch Q 1 is grounded. A second terminal of the electrical switch Q 1 is connected to a standby power supply terminal V 5 SB via the resistor R 1 . The output terminal 102 of the time delay circuit 10 is connected to a fourth node between the second terminal of the electrical switch Q 1 and the resistor R 1 .

In this embodiment, the motherboard power supply connector 30 has 24 pins for respectively connecting to a connector of the power supply unit 200 . Pin function descriptions of the motherboard power supply connector 30 are listed in the following table.

The No. 16 pin is the PSON# pin of the motherboard power supply connector 30 (hereinafter the PSON# pin 16 ). The No. 8 pin is the PWRGD# pin of the motherboard power supply connector 30 (hereinafter the PWRGD# pin 8 ).

The motherboard power supply connector 30 further includes a first electrical switch Q 21 , a second electrical switch Q 20 , a third electrical switch Q 19 , resistors R 33 , R 35 , R 32 and R 31 , and capacitors C 27 and C 28 . A control terminal of the first electrical switch Q 21 is connected to the output terminal 102 of the time delay circuit 10 . A first terminal of the first electrical switch Q 21 is grounded. A second terminal of the first electrical switch Q 21 is connected to the power supply terminal V 5 SB via the resistor R 33 . The PSON# pin 16 is connected to a fifth node between the second terminal of the first electrical switch Q 21 and the resistor R 33 .

A control terminal of the second electrical switch Q 20 is grounded via the capacitor C 28 . The PWRGD# pin 8 is connected to a sixth node between the control terminal of the second electrical switch Q 20 and the capacitor C 28 . The PWRGD# pin 8 is connected to a power supply terminal VCC via the sixth node and the resistor R 35 in that order, in series. The control terminal of the second electrical switch Q 20 is connected to the power supply terminal VCC via the resistor R 35 . A first terminal of the second electrical switch Q 20 is grounded. A second terminal of the second electrical switch Q 20 is connected to the power supply terminal V 3 DU via the resistor 32 . A control terminal of the third electrical switch Q 19 is connected to a seventh node between the second terminal of the second electrical switch Q 20 and the resistor R 32 . A first terminal of the third electrical switch Q 19 is grounded. A second terminal of the third electrical switch Q 19 is connected to a power supply terminal VCC 3 via the resistor R 31 . A PWRGD# terminal 201 of the motherboard power supply connector 30 is connected to the PWRGD# pin 8 . A system activation signal terminal 202 of the motherboard power supply connector 30 is connected to an eighth node between the resistor R 31 and the second terminal of the third electrical switch Q 1 . The system activation signal is converted from the PWRGD# signal and is configured for activating other electronic components, such as a central processing unit or a hard disk drive, in a computer system.

The motherboard power supply connector 30 includes a monitoring terminal 203 . The monitoring terminal 203 is connected between the fifth node and the PSON# pin 16 . The fifth node is between the second terminal of the first electrical switch Q 21 and the resistor R 33 . In this way, if the PSON# signal is generated because of computer fault under the condition of the power button of the computer system not being triggered, the motherboard 100 is capable of preventing undesirable power-on of the motherboard 100 .

When the power button of the computer system is triggered, the motherboard 100 generates a low level PSON# signal. The PSON# signal is outputted to the input terminal 101 of the time delay circuit 10 . The time delay circuit 10 can delay outputting the PSON# signal to the PSON# pin 16 of the motherboard power supply connector 30 in the pre-set time. Thus, power rails of the power supply unit 200 have enough time to power down fully before the arrival of the PSON# signal which turns on the power rails. Therefore the computer system can be normally responsive to the power on (low level PSON# signal) signal and power up failure is prevented.

It is to be understood, however, that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.