Analog divider

This application claims the benefit of U.S. provisional patent application No. 61/424,913, entitled “Analog Multiplier,” filed on Dec. 20, 2010, the disclosure of which is incorporated herein by reference in its entirety. This application is related to a concurrently filed U.S. non-provisional patent application Ser. No. 13/047,211, entitled “Analog Multiplier,” filed on Mar. 14, 2011, the disclosure of which is incorporated herein by reference in its entirety.

Embodiments described herein relate to an analog multiplier circuit. In addition, the embodiments described herein are further related to use of an analog multiplier to generate one or more controlled currents based upon a first input voltage and a second input voltage.

Analog multipliers may be used to multiply two analog signals to produce an output, which is effectively the product of the analog signals. In some cases, an analog multiplier may be used to multiply a first analog signal by the inverse of a second analog signal. The output of an analog multiplier may be either a voltage or a current.

Some analog multipliers may use two diodes to generate a current, which is an exponential function of the two input voltages. As a result, any offset voltage from the two input voltages may be exponentially magnified. In addition, the exponential function of the diodes tends to be sensitive to both process variations and temperature variations. As a result, the output of an analog multiplier may vary with process.

These process variations may affect the accuracy of the analog multiplier and lead to poor manufacturing yields or result in the need for post manufacturing calibration. Accordingly, there is a need for a new analog multiplier circuit or technique that substantially reduces or eliminates the process and batch to batch variations in an output of an analog multiplier.

The embodiments described in the detailed description relate to process independent analog multipliers used to generate a process independent controlled current source. A first field effect transistor and a second field effect transistor are controlled to operate in a triode region of operation. A first fixed resistor may be coupled to the drain of the first field effect transistor. A first operational amplifier is configured to receive a first reference voltage, where the operational amplifier regulates the voltage across the first fixed resistor and the drain-to-source resistance of the first field effect transistor to be substantially equal to the supply voltage less the first voltage. A constant current source coupled to the first resistor provides a reference current to pass through the first resistor and drain-to-source resistance of the first field effect transistor.

A second field effect transistor is also controlled to operate in the triode region of operation and to have substantially the same drain-to-source impedance as the first field effect transistor. A control node of the second field effect transistor is coupled to a control node of the first field effect transistor. The resistance of the first resistor may equal the resistance of the second resistor. A second resistor may be coupled to the drain of the second field effect transistor. As a result, the combined resistance of the second resistor and the drain-to-source resistance of the second field effect transistor may be substantially equal to the combined resistance of the drain-to-source resistance of the first field effect transistor and the resistance of the first resistor.

A second operational amplifier may be configured to regulate a second control voltage and may be placed across the combined resistance of the second resistor and the drain-to-source resistance of the second field effect transistor. As a result, the drain current of the second field effect transistor is substantially equal to the reference current multiplied by a ratio of the supply voltage less the second voltage divided by the supply voltage less the first voltage. A current mirror coupled to the output of the second operational amplifier provides an output current substantially equal to the drain current of the second field effect transistor.

A first exemplary embodiment of an analog multiplier includes a voltage controlled resistance circuit, a first operational amplifier, and a first transistor. The voltage controlled resistance circuit may include a first node, a second node coupled to a supply voltage, and a control node coupled to a first input voltage. The voltage controlled resistance circuit may further include a reference current source configured to provide a reference current. The impedance between the first node and second node of the voltage controlled resistance circuit may be based upon a ratio of the supply voltage less the first input voltage divided by the reference current. The first operational amplifier may include an inverted input coupled to a second input voltage, a non-inverted input coupled to the first node of the voltage controlled resistance circuit, and an output node. The first transistor may include a gate in communication with the output node of the first operational amplifier, a source coupled to a reference voltage, and a drain coupled to the non-inverted input of the first operational amplifier and the first node of the voltage controlled resistance circuit.

Another exemplary embodiment of an analog multiplier may be a method including generating a reference current, wherein the reference current passes through a first element. A first voltage generated across the first element is controlled to set a resistance of the first element based upon a first input voltage. A resistance of a second element is controlled to be substantially equal to the resistance of the first element. A second voltage generated across the second element is controlled based upon a second input voltage to generate a current passing through a third element.

Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 depicts an exemplary embodiment of an analog multiplier referenced to a constant current source.

FIG. 2 depicts a second exemplary embodiment of an analog multiplier referenced to a constant current source.

FIG. 3 depicts a third exemplary embodiment of an analog multiplier referenced to a constant current source.

FIG. 4 depicts an exemplary application of the analog multiplier of FIGS. 1-2 to control the operation of a radio frequency power amplifier.

FIG. 5 depicts an exemplary relationship between a controlled current output and a first input voltage and a second input voltage.

FIG. 6 depicts an exemplary application of the analog multipliers of FIGS. 1-3 to generate either a proportional to absolute temperature current source or an inversely proportional to absolute temperature current source referenced to a constant current source.

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

The embodiments described herein relate to process independent analog multipliers used to generate a process independent controlled current source. A first field effect transistor and a second field effect transistor are controlled to operate in a triode region of operation. A first fixed resistor may be coupled to the drain of the first field effect transistor. A first operational amplifier is configured to receive a first reference voltage, where the operational amplifier regulates the voltage across the first fixed resistor and the drain-to-source resistance of the first field effect transistor to be substantially equal to the supply voltage less the first voltage. A constant current source coupled to the first resistor provides a reference current to pass through the first resistor and drain-to-source resistance of the first field effect transistor.

A second field effect transistor is also controlled to operate in the triode region of operation and to have substantially the same drain-to-source impedance as the first field effect transistor. A control node of the second field effect transistor is coupled to a control node of the first field effect transistor. The resistance of the first resistor may equal the resistance of the second resistor. A second resistor may be coupled to the drain of the second field effect transistor. As a result, the combined resistance of the second resistor and the drain-to-source resistance of the second field effect transistor may be substantially equal to the combined resistance of the drain-to-source resistance of the first field effect transistor and the resistance of the first resistor.

A second operational amplifier may be configured to regulate a second control voltage and may be placed across the combined resistance of the second resistor and the drain-to-source resistance of the second field effect transistor. As a result, the drain current of the second field effect transistor is substantially equal to the reference current multiplied by a ratio of the supply voltage less the second voltage divided by the supply voltage less the first voltage. A current mirror coupled to the output of the second operational amplifier provides an output current substantially equal to the drain current of the second field effect transistor.

FIG. 1 depicts an exemplary embodiment of an analog multiplier 10 , where the output current I OUT is substantially based upon a current of a constant current source I CC and the ratio of a second input voltage V 2 to a first input voltage V 1 .

The analog multiplier 10 includes a first controlled resistance R REF and a second controlled resistance R RP . The impedance of the first controlled resistance R REF equals the resistance of a first resistor R 1 plus a drain-to-source resistance R MN1 of a first transistor MN 1 . A source of the first transistor MN 1 is coupled to a reference voltage, ground, while the drain of the first transistor is coupled to the first resistor R 1 . The resistance of the second controlled resistance R RP equals a resistance of a second resistor R 2 plus a drain-to-source resistance R MN2 of a second transistor MN 2 . A source of the second transistor MN 2 is coupled to a reference voltage, ground, while the drain of the second transistor is coupled to the second resistor R 2 . The drain-to-source resistance R MN1 of the first transistor MN 1 , operating in a triode mode region of operation, is provided by equation (1).

R MN ⁢ ⁢ 1 = 1 K MN ⁢ ⁢ 1 ⁡ ( V gs MN ⁢ ⁢ 1 - V t - V ds MN ⁢ ⁢ 1 / 2 ) , ( 1 )

where V gs MN1 is the gate-to-source voltage of the first transistor MN 1 , V t is the threshold voltage of the first transistor MN 1 , V ds MN1 is the drain-to-source voltage across the first transistor MN 1 , and K MN1 is a constant. The value of K MN1 for a NMOS FET transistor may be calculated as given in equation (2).

K MN ⁢ ⁢ 1 = μ n ⁢ C ox ⁡ ( W MN ⁢ ⁢ 1 L MN ⁢ ⁢ 1 ) , ( 2 )

where L MN1 is the channel length of the first transistor MN 1 , W MN1 is the channel width of the first transistor MN 1 , μ MN1 is the mobility of an electron in a material of the first transistor MN 1 , and C ox is the gate oxide capacitance per unit area of the first transistor MN 1 .

As indicated by equation (1), the drain-to-source impedance of the first transistor is dependent upon the drain-to-source voltage V ds MN1 of the first transistor. The non-linear effects of the drain-to-source voltage V ds MN1 on the impedance across the FET transistor may be compensated for by a first linearization circuit composed of a third resistor R 3 and a fourth resistor R 4 , for the first transistor MN 1 ; and a second linearization circuit composed of a fifth resistor R 5 and a sixth resistor R 6 , for the second transistor MN 2 .

The third resistor R 3 is coupled between the output of a first operation amplifier OPAMP 1 and the gate of the first transistor MN 1 . The fourth resistor R 4 is coupled between the gate and drain of the first transistor MN 1 . The fifth resistor R 5 is coupled between the output of the first operational amplifier OPAMP 1 and the gate of the second transistor MN 2 . The sixth resistor R 6 is coupled between the gate and drain of the second transistor MN 2 .

The first operational amplifier OPAMP 1 generates a gate control voltage V g based upon the difference between a first input voltage V 1 , applied to the inverting input of the OPAMP 1 and the voltage V REF across the first controlled resistance R REF . The gate-to-source voltage V gs MN1 of the first transistor MN 1 is given by equation (3), where the gate current is assumed to be zero relative to the current “i” passing through resistors R 3 and R 4 .

V gs MN1 =V g −iR 3   (3)

The voltage V ds MN1 of the first transistor MN 1 is given by equation (4).

V ds MN1 =V g −i ( R 3 +R 4 )  (4)

Setting the resistance of R 3 and R 4 to R, re-arranging variables, and solving for V gs MN1 of the first transistor MN 1 yields equation (5).

V =( V g −V ds MN1 )/2  (5),

where V g is a gate control voltage at the output of the operational amplifier OPAMP 1 , and V ds MN1 is the drain-to-source voltage of the first transistor MN 1 .

Substituting equation (5) into equation (1) yields a “linearized” equation (6) for the drain-to-source resistance R MN1 of the first transistor MN 1 that is not dependent upon the drain-to-source voltage V ds MN1 of the first transistor MN 1 .

Assuming that a resistance of the fifth resistor R 5 equals the resistance of the sixth resistor R 6 , a similar result is reached for the drain-to-source resistance of the second transistor MN 2 , which is given by equation (7).

Assuming that the first transistor MN 1 and the second transistor MN 2 have the same threshold voltage V t , the ratio of the drain-to-source resistance of the first transistor MN 1 to the drain-to-source resistance of the second transistor MN 2 is shown in equation (8).

R MN ⁢ ⁢ 1 R MN ⁢ ⁢ 2 = K MN ⁢ ⁢ 2 K MN ⁢ ⁢ 1 = ( L MN ⁢ ⁢ 1 × W MN ⁢ ⁢ 2 ) ( L MN ⁢ ⁢ 2 × W MN ⁢ ⁢ 1 ) ( 8 )

where L MN2 is the channel length of the second transistor MN 2 , and W MN2 is the channel width of the second transistor MN 2 .

Accordingly, using the same channel length and channel width for both the first transistor MN 1 and the second transistor MN 2 sets the drain-to-source resistance R MN2 of the second transistor MN 2 equal to the drain-to-source resistance R MN1 of the first transistor MN 1 . Alternatively, the channel length and channel width of the first transistor MN 1 may be different than the channel length and channel width of the second transistor MN 2 such that the drain-to-source resistance R MN1 of the first transistor MN 1 is proportional to the drain-to-source resistance R MN2 of the second transistor MN 2 .

As an example, in some exemplary embodiments of the analog multiplier the drain-to source resistance R MN2 of the second transistor MN 2 may be a factor “n” times the drain-to-source resistance R MN1 of the first transistor MN 1 . In other embodiments, the resistance of the second resistor R 2 is also the factor “n” times the resistance of the first resistor R 1 such that the combined resistance of the drain-to-source resistance R MN2 of the second transistor and the resistance of the second resistor R 2 is the factor of “n” times the combined resistance of the of the drain-to-source resistance R MN1 of the first transistor and the resistance of the first resistor. In some embodiments the factor “n” is greater than one. In other embodiments the factor “n” may be less than one.

A constant current source I CC is coupled between the first resistor R 1 and a supply voltage V SUPPLY . The voltage generated across the first controlled resistance R REF , (V REF ), is controlled based upon the first input voltage V 1 divided by the current passing through the constant current source I CC , where the voltage drop across the inverting input of the first operational amplifier OPAMP 1 and the non-inverting input of the first operational amplifier OPAMP 1 is assumed to approach zero volts.

Accordingly, the resistance of the first controlled resistance R REF is given by equation (9), where V 1 is a first control voltage.

The analog multiplier 10 further includes a second operational amplifier OPAMP 2 having an inverting input coupled to a second control voltage V 2 , and a non-inverting input coupled to the second controlled resistance R RP . A drain of a third transistor MP 1 is also coupled to the non-inverting input of the second operational amplifier OPAMP 2 . The source of the third transistor MP 1 is coupled to the supply voltage V SUPPLY . The gate of the third transistor MP 1 is coupled to the output of the second operational amplifier OPAMP 2 .

A second input voltage V 2 is provided to the inverting input of the second operational amplifier OPAMP 2 . Assuming that the voltage drop across the inverting input of the second operational amplifier OPAMP 2 and the non-inverting input of the second operational OPAMP 2 approaches zero volts, the second input voltage V 2 is placed across the second controlled resistance R RP . Assuming that the current passing through the sixth resistor R 6 is more than an order of magnitude less than the drain current of the second transistor I MN2 , the current passing through the second controlled resistance R RP (I MN2 ) is given by equation (10).

Setting the resistance of the first resistor R 1 equal to the resistance of the second resistor R 2 such that R REF equals R RP yields equation (11), where R MN1 equals R MN2 .

Assuming that the input impedance of the second operational amplifier OPAMP 2 is very large, the drain current I MP1 of the third transistor MP 1 equals the drain current I MN1 of the second transistor MN 2 . A fourth transistor MP 2 mirrors the drain current I MP1 of the third transistor MP 1 . The fourth transistor MP 2 includes a source coupled to the voltage supply V SUPPLY and a gate coupled to the output of the second operational amplifier OPAMP 2 . As a result, the output current I OUT passing through the fourth transistor MP 2 is equal to the drain current I MP1 passing through the third transistor MP 1 . In some embodiments of the analog multiplier 10 the fourth transistor MP 2 may be configured to have an output current I OUT proportional to the drain current passing through the third transistor MP 1 . Accordingly, the output current I OUT is given by equation (12).

In an alternative embodiment, the resistance of the first resistor and the second resistor are set to zero. In this case, the output current I OUT may be based upon the ratio of the drain-to-source resistance R MN1 of the first transistor MN 1 to the drain-to-source resistance R MN2 of the second transistor MN 2 , as shown in equation (13).

Accordingly, the output current I OUT is given by equation (14), which permits the output current to be scaled according to the relative channel length to channel width ratios of the first transistor MN 1 and the second transistor MN 2 .

FIG. 2 depicts another exemplary embodiment of an analog multiplier 12 , which is similar in function to the analog amplifier 10 depicted in FIG. 1 . As depicted in FIG. 2 , the first linearization circuit and the second linearization circuit are eliminated. The gates of the first transistor MN 1 and the second transistor MN 2 are directly tied to the output of the first operational amplifier. In addition, the fourth resistor R 4 and the sixth resistor R 6 are removed. Accordingly, the resistance of the first controlled resistance R REF is given by equation (15).

R REF = 1 K MN ⁢ ⁢ 1 ⁡ ( V gs MN ⁢ ⁢ 1 - V t - V ds MN ⁢ ⁢ 1 / 2 ) + R 1 ( 15 )

where V ds MN1 is the drain-to-source voltage across the first transistor MN 1 , and V gs MN1 is the gate-to-source voltage of the second transistor MN 1 .

Similarly, the resistance of the second controlled resistance R RP is given by equation (16).

R RP = 1 K MN ⁢ ⁢ 2 ⁡ ( V gs MN ⁢ ⁢ 2 - V t - V ds MN ⁢ ⁢ 2 / 2 ) + R 2 ( 16 )

where V ds MN2 is the drain-to-source voltage across the first transistor MN 2 , and V gs MN2 is the gate-to-source voltage of the second transistor MN 2 . The gate-to-source voltage V gs MN1 of the first transistor MN 1 and the gate-to-source voltage V gs MN2 of the second transistor MN 2 are each equal to V g . When the first input voltage V 1 equals the second input voltage V 2 , the drain-to-source resistance R MN1 of the first transistor MN 1 equals the drain-to-source resistance R MN2 of the second transistor MN 2 . Otherwise, the drain-to-source resistance R MN1 of the first transistor MN 1 does not equal the drain-to-source resistance R MN2 of the second transistor MN 2 because V ds MN1 ≠V ds MN2 . The difference between the drain-to-source resistance R MN1 of the first transistor MN 1 and the drain-to-source resistance R MN2 of the second transistor MN 2 may be calculated based upon the ratio of R MN1 divided by R MN2 , as shown in equation (17), where

[ R MN ⁢ ⁢ 1 R MN ⁢ ⁢ 2 ] = 1 + K ⁡ ( V ds MN ⁢ ⁢ 1 - V ds MN ⁢ ⁢ 2 ) 2 × I CC ⁢ V DS MN ⁢ ⁢ 1 ( 17 )

where K MN1 and K MN2 are the same and

V gs MN ⁢ ⁢ 1 - V t = V g - V t = I CC K × V ds MN ⁢ ⁢ 1 + V ds MN ⁢ ⁢ 1 / 2 ( 17. ⁢ b )

which yields an error factor λ given as equation (17.c).

λ = K ⁡ ( V ds MN ⁢ ⁢ 1 - V ds MN ⁢ ⁢ 2 ) 2 × I CC ⁢ V DS MN ⁢ ⁢ 1 ( 17. ⁢ c )

Accordingly, the error factor λ, by which R MN1 does not equal R MN2 , may be minimized by minimizing the difference between the V ds MN1 and V ds MN2 or increasing the current output of the constant current source I CC relative to the value of K.

In an alternative exemplary embodiment, a first linearizing resistor (not shown) may be placed across the drain-to-source terminals of the first transistor MN 1 and a second linearizing resistor (not shown) may be placed across the drain-to-source terminals of the second transistor MN 2 .

FIG. 3 depicts an exemplary embodiment of an analog multiplier 20 referenced to a constant current source I CC . Similar to the analog multiplier 10 of FIG. 1 , the analog multiplier 20 includes a first controlled resistance R REF coupled between the supply voltage V SUPPLY and the constant current source I CC . The first controlled resistance R REF includes the drain-to-source resistance R MP1 of the first transistor MP 1 and resistance of the first resistor R 1 . The analog multiplier 20 further includes a second controlled resistance R RP , which includes the drain-to-source resistance R MP2 of the second transistor MP 2 and the resistance of a second resistor R 2 . The second controlled resistance R RP is coupled between the voltage supply V SUPPLY and the drain of a third transistor MN 1 . The source of the third transistor MN 1 is coupled to a reference voltage, which may be ground. A fourth transistor MN 2 is configured to mirror the drain current of the third transistor MN 1 . The source of the fourth transistor MN 2 is coupled to the reference voltage, which may be ground.

Similar to analog multiplier 10 of FIG. 1 , the analog multiplier 20 includes a first operational amplifier OPAMP 1 having an inverting input coupled to a first input voltage V 1 , a non-inverting input coupled to the constant current source I CC , and an output. The output of the first operational amplifier OPAMP 1 is coupled to a first linearization circuit formed by the third resistor R 3 and the fourth resistor R 4 . The third resistor R 3 is coupled between the gate of the first transistor MP 1 and the output of the first operational amplifier OPAMP 1 . The fourth resistor R 4 is coupled between the gate and drain of the first transistor MP 1 . The output of the first operational amplifier OPAMP 1 is also coupled to a second linearization circuit formed by a fifth resistor R 5 and a sixth resistor R 6 . The fifth resistor R 5 is coupled between the gate of the second transistor MP 2 and the output of the first operational amplifier OPAMP 1 . The sixth resistor R 6 is coupled between the gate and drain of the second transistor MP 2 .

Also similar to the analog multiplier 10 of FIG. 1 , the drain-to-source resistance R MP1 of the first transistor MP 1 is given by equation (18), and the drain-to-source resistance R MP2 of the second transistor MP 2 is given by equation (19).

R MP ⁢ ⁢ 1 = 1 K MP ⁢ ⁢ 1 ⁡ [ V g / 2 - V t ] ( 18 ) R MP ⁢ ⁢ 2 = 1 K MP ⁢ ⁢ 2 ⁡ [ V g / 2 - V t ] ( 19 )

where V g is the voltage between the output of the first operational amplifier OPAMP 1 and the sources of the first transistor MP 1 and the second transistor MP 2 .

Also similar to the analog multiplier 10 of FIG. 1 , the analog multiplier 20 of FIG. 3 further includes a second operational amplifier OPAMP 2 having an inverting output coupled to a second input voltage V 2 , a non-inverting input coupled to the second resistor R 2 , and an output coupled to the gate of the third transistor MN 1 .

The resistance of the first controlled resistance R REF is given by equation (20), where V 1 is the first control voltage.

Assuming that the resistance of the first resistor R 1 equals the resistance of the second resistance R 2 and that K MP1 =K MP2 , the drain current of the second transistor MP 2 is given by equation (21).

Assuming that the current passing through the sixth resistor R 6 is minimal compared to the drain current I MP2 of the second transistor MP 2 , the drain current I MN1 of the third transistor MN 1 is substantially equal to the drain current I MP2 of the second transistor MP 2 . Because the fourth transistor MN 2 is configured to mirror the drain current I MN1 of the third transistor MN 1 , the output current I OUT is given by equation (22).

Alternatively, a fifth transistor (not shown) may be configured to mirror the current through the second transistor MP 2 of FIG. 3 by coupling the gate of the fifth transistor to the gate of the second transistor MP 2 . In this case, the source of the fifth transistor is coupled to the supply voltage V SUPPLY . The drain current of the fifth transistor will be proportional to the drain current of the second transistor MP 2 of FIG. 3 .

FIG. 4 depicts an exemplary application of the analog multiplier of FIG. 2 to control the operation of a radio frequency power amplifier. The analog multiplier 30 includes a first voltage input V 1 , a second voltage input V 2 , and a controlled current output I OUT . Assuming that the analog multiplier 30 is similar to the analog amplifier 10 of FIG. 1 , the output current I OUT is given by equation (23),

I OUT = [ V 2 V 1 ] × I CC ( 23 )

where I CC is a reference current. The reference current I CC may be set by an external resistance (not shown). The controlled current output I OUT may be coupled to the power input of a radio frequency (RF) amplifier 32 . The RF amplifier 32 may be configured to receive an RF input and provide an RF output to an antenna 33 . The RF amplifier 32 may be a wideband code division multiple access (WCDMA) power amplifier.

A first reference voltage output V A of a band gap reference 34 is coupled to the first voltage input V 1 of the analog multiplier 30 . The band gap reference 34 may be configured to provide a substantially temperature invariant control voltage V A . A ramp voltage generator circuit 36 includes a V RAMP output voltage coupled to the second voltage input V 2 of the analog multiplier. The ramp voltage generator circuit 36 may include a configurable offset voltage. The V RAMP output voltage may be used to control the output power of the RF amplifier 32 .

FIG. 5 depicts an example relationship between the controlled current output I OUT of the analog multiplier 30 for different values of reference current I CC , where the first voltage input V 1 is 2.0 volts, and the second voltage output V 2 equals (V RAMP −0.2 volts), as shown in equation (24).

I OUT = [ V RAMP - .2 ⁢ ⁢ V 2 ⁢ ⁢ V ] × I CC . ( 24 )

As depicted in FIG. 6 , the non-linear error factor A for the analog multiplier 12 of FIG. 2 is less than 1%.

FIG. 6 depicts an exemplary application of the analog multiplier of FIGS. 1-2 . A reference voltage generator circuit 40 includes an analog multiplier 32 , a band gap reference 34 , and a reference voltage generator 40 . The first input voltage V 1 of the analog multiplier 32 may be coupled to the first reference voltage output V A of the band gap reference 34 . The second input voltage V 2 of the analog multiplier 32 may be coupled to a reference voltage generator output V B of the reference voltage generator 40 . The reference voltage generator output V B may be a control voltage. As a non-limiting example, the reference voltage may be a proportional to absolute temperature voltage reference V PTAT , an inversely proportional to absolute temperature voltage reference V NTAT , or another band gap reference. The controlled current output I OUT is controlled by the ratio of the V B to V A .

Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.