Dual output DC-DC charge pump regulator

The present disclosure claims priority to U.S. Provisional App. No. 61/306,796 for “Dual Flycap Dual Output DC-DC Regulator” filed Feb. 22, 2010; U.S. Provisional App. No. 61/306,822 for “Dual Output DC-DC Regulator” filed Feb. 22, 2010; and U.S. Provisional App. No. 61/355,952 for “Dual Output DC-DC Switched Capacitor Regulator” filed Jun. 17, 2010, all of which are incorporated herein by reference in their entirety for all purposes.

Particular embodiments generally relate to a dual output direct current (DC)-to-DC regulator.

Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

A charge pump is a DC-to-DC converter that uses capacitors to create either a higher or lower voltage output. Charge pumps use switches to control different connections for the capacitors. For example, in a first phase, a flying capacitor is connected to a voltage supply to charge the flying capacitor. In a second phase, the flying capacitor is disconnected from the voltage supply and connected to a second capacitor at an output. Charge then flows from the flying capacitor to the second capacitor, which increases the voltage across the second capacitor. The above process between the first phase and the second phase continues at a pre-determined frequency. The process regulates the output voltage across the second capacitor to maintain the output voltage a desired level.

The charge pump regulates the output voltage at a single output. However, if multiple outputs are required, then an additional flying capacitor, an additional output capacitor, and an additional set of switches are needed to regulate the second output. This may be an inefficient use of integrated circuit (IC) chip area.

In one embodiment, an apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output.

In one embodiment, the apparatus includes a seventh switch coupled to the first voltage reference and an eighth switch coupled to the second voltage reference. A ninth switch is coupled to a first terminal of a fifth capacitor and the first terminal of the second capacitor. A tenth switch is coupled to a second terminal of the fifth capacitor and the first terminal of the second capacitor. An eleventh switch is coupled to the second terminal of the fifth capacitor and the first terminal of the third capacitor. A twelfth switch is coupled to the first terminal of the fifth capacitor and the first terminal of the third capacitor.

In one embodiment, a system includes the first reference voltage; the second reference voltage; the first capacitor; the second capacitor; and the third capacitor.

In one embodiment, a method includes: coupling a first switch coupled to a first voltage reference; coupling a second switch coupled to a second voltage reference; coupling a third switch coupled to a first terminal of a first capacitor and a first terminal of a second capacitor; coupling a fourth switch coupled to a second terminal of the first capacitor and the first terminal of the second capacitor; coupling a fifth switch coupled to the second terminal of the first capacitor and a first terminal of a third capacitor; coupling a sixth switch coupled to the first terminal of the first capacitor and the first terminal of the third capacitor, and controlling the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch to maintain a first voltage level at a first output and a second voltage level at a second output.

The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention.

FIG. 1 depicts an example of a regulator according to one embodiment.

FIG. 2 a depicts a first case in the switching scheme according to one embodiment.

FIG. 2 b depicts a second case for the switching scheme according to one embodiment.

FIG. 2 c depicts a third case in the switching scheme according to one embodiment.

FIG. 2 d depicts a fourth case of the switching scheme according to one embodiment.

FIG. 3 a depicts an example of a critical path according to one embodiment.

FIG. 3 b depicts the resistances in the critical path according to one embodiment.

FIG. 4 depicts an example of a regulator using dual flying capacitors according to one embodiment.

FIG. 5 a depicts an example of using dual flying capacitors Cf 1 and Cf 2 in the first case of the switching scheme according to one embodiment.

FIG. 5 b depicts a second case using dual flying capacitors according to one embodiment.

FIG. 5 c depicts a third case using dual flying capacitors according to one embodiment.

FIG. 6 depicts a method for maintaining a first voltage level at a first output and a second voltage level at a second output according to one embodiment.

Described herein are techniques for a regulator. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

Single Flying Capacitor

FIG. 1 depicts an example of a regulator 100 according to one embodiment. Regulator 100 maintains output voltages at dual outputs (e.g. output V 12 and output V 18 ). A switched capacitor design transfers charge among a flying capacitor (Cf), a first output capacitor (C 12 ), and a second output capacitor (C 18 ). In one example, output V 12 is maintained substantially at 1.2 volts, output V 18 is maintained substantially at 1.8 volts, and a voltage reference Vdd is at 3.3 volts. Although these voltages are described, other voltages may be used.

In one embodiment, an IC chip includes switches SW 1 -SW 6 . Voltage reference Vdd, voltage reference GND, and capacitors Cf, C 12 , and C 18 are located off chip. In regulator 100 , multiple switches, such as switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , and SW 6 , are controlled in different switching schemes. Switch SW 1 couples reference voltage Vdd to flying capacitor Cf through pins P 1 and P 2 of the chip. Switch SW 2 couples flying capacitor Cf to a second reference voltage, such as ground (GND), through pins P 3 and P 6 . Switch SW 3 couples capacitor C 12 to a first terminal of flying capacitor Cf through pins P 3 and P 5 . Switch SW 4 couples capacitor C 12 to a second terminal of flying capacitor Cf through pins P 2 and P 5 . Also, switch SW 5 and switch SW 6 couple capacitor C 18 to the second terminal (through pins P 4 and P 2 ) and the first terminal (through pins P 4 and P 3 ) of flying capacitor Cf, respectively. Capacitors C 12 and C 18 are also coupled to ground.

A switching scheme is performed based on the output voltages at outputs V 12 and V 18 . Each case may include two phases that are switched between according to a reference signal. The switching scheme that is used may be determined based on voltages at outputs V 12 and V 18 and couple capacitors Cf, C 12 , and C 18 in different paths. A high efficiency is provided and a total resistance of a critical path is less than total resistance restrictions due to characteristics of a layout for the design.

FIG. 2 a depicts a first case in the switching scheme according to one embodiment. The first case may be used when the following high and low voltages for outputs V 12 and V 18 are found:

V 12 H<1.2;

V 18 H<1.8;

V 12 L>1.15; and

V 18 L>1.75,

wherein H denotes the high voltage measured and L denotes the low voltage measured at outputs V 12 or V 18 . In this case, both the high voltages at outputs V 12 and V 18 are below the desired levels. Thus, the switching scheme attempts to increase the voltages at outputs V 12 and V 18 to maintain them at 1.2 volts and 1.8 volts, respectively.

In phase 1 (φ1), switches SW 1 and SW 6 are closed and switches SW 2 , SW 3 , SW 4 , and SW 5 are open. This couples the second terminal of the flying capacitor Cf to the reference voltage Vdd and the first terminal of the flying capacitor Cf to output V 18 . Also, capacitor C 12 is coupled to output V 12 .

The voltage at the second terminal of flying capacitor Cf will be Vdd−V 18 =1.5 volts. The voltage across flying capacitor Cf starts at 1.2 volts (the starting voltage across flying capacitor Cf is from phase 2 , which is described below). Thus, there is a voltage difference ΔV of 0.3 volts. If capacitor C 18 is of a sufficiently large size, then the voltage across capacitor C 18 remains at 1.8 volts. The current used to charge flying capacitor Cf to the voltage of Vdd−V 18 then flows to a load coupled to output V 18 , which increases the voltage at the load (and output V 18 ).

In phase 2 (φ2), switches SW 2 and SW 4 are closed and switches SW 1 , SW 3 , SW 5 , and SW 6 are open. Capacitor C 18 is coupled to the load at output V 18 . Also, flying capacitor Cf is coupled to capacitor C 12 . The voltage at the second terminal of flying capacitor Cf is Vdd−V 18 . If the voltage Vdd−V 18 is greater than the voltage across capacitor C 12 , which is less than 1.2 volts, then charge flows from flying capacitor Cf to capacitor C 12 . Flying capacitor Cf and capacitor C 12 will eventually equal the same charge. For example, if the voltage across flying capacitor Cf is 3.3−1.8=1.5 volts, then a voltage difference ΔV of 0.3 volts may be used to charge capacitor C 12 . This may be enough voltage to charge capacitor C 12 to the desired level of 1.2 volts. The frequency of the switching scheme may switch back to phase 1 at a time around when capacitor C 12 is charged to 1.2 volts.

The voltages across capacitors Cf, C 12 , and C 18 do not change significantly between phase 1 and phase 2 . Thus, the efficiency of regulator 100 is high, such as around 91%. Additionally, both outputs V 12 and V 18 are charged using flying capacitor Cf and switches SW 1 -SW 6 . For example, in phase 1 , output V 18 is charged, and in phase 2 , output V 12 is charged.

FIG. 2 b depicts a second case for the switching scheme according to one embodiment. The second case may be used when the following high and low voltages for outputs V 12 and V 18 are found:

V 12 H>1.2;

V 18 H<1.8; and

either V 18 L<1.75; or

V 12 L<1.15.

In one embodiment, in phase 1 , the switches are controlled such that the voltage at output V 18 is increased. For example, switches SW 3 and SW 5 are closed while switches SW 1 , SW 2 , SW 4 and SW 6 are open. This couples capacitor C 12 to the first terminal of flying capacitor Cf and to the output V 12 . Also, capacitor C 18 is coupled to the second terminal of flying capacitor Cf and output V 18 .

The charge across flying capacitor Cf may be Vdd−V 18 =1.5 volts. In this case, charge flows to capacitor C 18 , which is below 1.8 volts. This increases the voltage at output V 18 .

Different configurations may be used in phase 2 . For example, in phase 2 a , switches SW 1 and SW 6 are closed while switches SW 2 , SW 3 , SW 4 , and SW 5 are open. This circuit configuration is the same as discussed with respect to phase 1 in the first case in FIG. 2 a . In this case, flying capacitor Cf is charged and current flows to the load at output V 18 . This increases the voltage at output V 18 . Accordingly, the voltage at output V 18 is increased in both phases.

In another embodiment, instead of charging flying capacitor Cf using the configuration in phase 2 a , capacitor C 12 may be used to charge flying capacitor Cf in a phase 2 b . For example, if the voltage across capacitor C 12 is greater than 1.2 volts, then the charge from capacitor C 12 may be used to charge flying capacitor Cf However, if the low voltage at output V 12 is V 12 L<1.15, then the configuration shown in phase 2 a of FIG. 2 a may be used because the low voltage across capacitor C 12 is less than 1.2 volts and it may not be desirable to use capacitor C 12 to charge flying capacitor Cf.

In phase 2 b , switches SW 2 and SW 4 are closed while switches SW 1 , SW 3 , SW 5 , and SW 6 are open. The second terminal of flying capacitor Cf is coupled to capacitor C 12 at output V 12 . Also, capacitor C 18 is coupled to output V 18 . The charge from capacitor C 12 charges flying capacitor Cf.

FIG. 2 c depicts a third case in the switching scheme according to one embodiment. The third case may be used when the following high and low voltages for outputs V 12 and V 18 are found:

V 12 H<1.2;

V 18 H>1.8; and

either V 18 L<1.75; or

V 12 L<1.15.

In the third case, the high voltage at output V 18 is greater than 1.8 and the high voltage at output V 12 is less than 1.2 volts. The low voltage for output V 18 may be less than 1.75 or the low voltage at output V 12 may be less than 1.15 volts. The switching scheme attempts to increase the voltage at output V 12 . In a phase 1 a of the third case, the switches are controlled such that the voltage at output V 12 is increased. For example, in phase 1 a , switches SW 1 and SW 3 are closed and switches SW 2 , SW 4 , SW 5 , and SW 6 are open. This couples capacitor C 18 to output V 18 . Also, the second terminal of flying capacitor Cf is coupled to voltage reference Vdd. The first terminal of flying capacitor Cf is coupled to capacitor C 12 and output V 12 . This configuration is similar to phase 1 of the first case in FIG. 2 a except that flying capacitor Cf is coupled to capacitor C 12 instead of capacitor C 18 .

The voltage at the second terminal of flying capacitor Cf will be Vdd−V 12 =2.1 volts. The voltage across capacitor Cf is 1.2 volts. Thus, there is a voltage difference ΔV of 0.9 volts. If capacitor C 12 is of a sufficiently large size, then the voltage across capacitor C 12 remains at 1.2 volts. The current used to charge flying capacitor Cf to the voltage of Vdd−V 12 then flows to a load coupled to output V 12 , which increases the voltage at the load (and output V 12 ).

Other configurations may also be used to charge capacitor Cf, such as a charge across capacitor C 18 may be used to charge capacitor Cf as shown in phase 1 b . However, if the low voltage for output V 18 is less than 1.75, then it may not be desirable to use the charge from capacitor C 18 to charge capacitor Cf. In phase 1 b , switches SW 2 and SW 5 are closed and switches SW 1 , SW 3 , SW 4 , and SW 6 are open. This couples capacitor C 18 to the second terminal of flying capacitor Cf The charge across capacitor C 18 charges flying capacitor Cf.

In phase 2 , capacitor C 18 continues to be coupled to output V 18 ; however, switches SW 2 and SW 4 are closed while switches SW 1 , SW 3 , SW 5 , and SW 6 are open. This couples the second terminal of flying capacitor Cf to output V 12 and capacitor C 12 . The voltage across flying capacitor Cf is Vdd−V 12 , and charge flows from flying capacitor Cf to capacitor C 12 because this voltage is greater than the voltage across capacitor C 12 . For example, the voltage across flying capacitor Cf may be 2.1 volts. As charge transfers from flying capacitor Cf to capacitor C 12 , the voltage at output V 12 is increased. The frequency of the switching scheme may switch back to phase 1 at a time around when capacitor C 12 is charged to 1.2 volts.

FIG. 2 d depicts a fourth case of the switching scheme according to one embodiment. The fourth case may be used when the following voltages for outputs V 12 and V 18 are found:

V 12 H>=1.2;

V 18 H>=1.8;

In this case, the voltages at output V 12 and output V 18 are substantially equal to or slightly above 1.2 and 1.8 volts, respectively. Accordingly, in phase 1 and phase 2 , switch SW 2 is closed and switches SW 1 , SW 3 , SW 4 , SW 5 , and SW 6 are open. Capacitor C 18 is coupled to output V 18 and capacitor C 12 is coupled to output V 12 . Flying capacitor is floating. This leaves regulator 100 in a steady state in which the voltages and outputs V 12 and V 18 are maintained.

The above switching schemes are efficient. The efficiency may be a measure of transferring charge from a source to a load, such as from a capacitor to a capacitor coupled to the output. The efficiencies may be high because the amount of charge transferred is low. The efficiency for the first case may be around 91%, the efficiency for the second case around 72.8%, and the efficiency for the third case around 72.8%. These efficiencies may be higher than the conventional charge pump. For a combined efficiency, each case may be multiplied by their expected occurrence and the outcomes added.

Depending on the design of regulator 100 , there may be restrictions with regard to a total resistance within a path in a layout of the IC chip during a switching scheme. For example, for phase 1 of the first case, there is a voltage difference ΔV of 0.3 volts−3.3V−1.8V−1.2V (Vdd−V 18 −V 12 ). Because the voltage difference ΔV is 0.3 volts, if the total resistance in the path is too high, then the time it takes to charge flying capacitor Cf may become too long or take too many time constants. Assuming the following conditions of a load current (I 1 )=100 mA and a minimum voltage difference (ΔV)=0.3 volts, the following resistance total (R TOTAL ) may be determined using the following equations:

I L = Cf × Δ ⁢ ⁢ V × f osc R TOTAL ⁢ C f = 1 / 2 ⁢ nf osc R TOTAL = 1 / ( 2 ⁢ nf osc ⁢ C f ) R TOTAL = Δ ⁢ ⁢ V 2 ⁢ n * I L ,

wherein I L is a current through the load, Cf is the capacitance of the flying capacitor, f osc is the frequency of the output signal, and n is the number of time constants.

This provides a resistance total that is R TOTAL =03.75 ohms for four time constants. Four time constants may be desirable because flying capacitor Cf may be charged to 98% of the desired voltage.

The total resistance takes into account the resistance of switches, metal wires, bond wires, and equivalent series resistance (ESR) of capacitors in the path. FIG. 3 a depicts an example of a critical path 302 according to one embodiment. Critical path 302 couples reference voltage Vdd to flying capacitor Cf and capacitor C 18 . The resistances for switches SW 1 and SW 6 , the bond wires, and the ESR of flying capacitor Cf and capacitor C 18 are in the path. The bond wires are wires that couple from the IC chip to external components. For example, bond wires are needed to couple switch SW 1 to reference voltage Vdd, a pin P 1 to voltage reference Vdd, pins P 2 and P 3 to flying capacitor Cf, and pin P 4 to capacitor C 18 .

FIG. 3 b depicts the resistances in the critical path according to one embodiment. As shown, the resistances for the bond wire to reference voltage Vdd (3.3V Bond Wire), switch SW 1 (SW 1 Ron), bond wire from pin P 2 to flying capacitor Cf (Cf IN Bond Wire), and the ESR resistance for flying capacitor Cf (Cf ESR) are shown. After flying capacitor Cf, resistances for the bond wire from capacitor Cf to pin P 3 (Cf OUT Bond Wire), switch SW 6 (SW 6 Ron), the bond wire from switch SW 6 to capacitor C 18 (1.8V Bond Wire), and the ESR resistance for capacitor C 18 (C 18 ESR) are shown. Using a double bond or triple bond wire connection, the total resistance may be below the R TOTAL calculated above of 0.375 ohms. The resistance may be minimized by maximizing the area of switches SW 1 and SW 6 and also minimizing the length of the bond wires.

Dual Flying Capacitor

Particular embodiments may use a dual flying capacitor with two outputs. The dual flying capacitors may be used because of the small ΔV in phase 1 of FIG. 2 a . If the output current is higher than 100 mA, such as 200 mA, then the total resistance R TOTAL for a path may be lower than desired. The total resistance may be R=ΔV\(2*n*Ia), wherein n is a number of time constants and Ia is an output current. The total resistance depends on the voltage difference ΔV and the output current Ia. The output current Ia may be the output current at voltages V 18 or V 12 . If the output current increases, then the total resistance allowed for a path goes down. Also, if Vdd is lower than 3.3V, such as at 3.1V, then the total resistance allowed for a path also goes down. With two switches and four bond wires in a critical path, having a smaller switch resistance may cause design difficulties. Thus, increasing the voltage difference ΔV may be beneficial.

FIG. 4 depicts an example of a regulator 400 using dual flying capacitors according to one embodiment. The switches of FIG. 1 may be duplicated for two flying capacitors Cf 1 and Cf 2 . For example, flying capacitor Cf 1 , switches SW 1 A-SW 6 A, capacitor C 12 and capacitor C 18 are similar to the circuit shown in FIG. 1 . An additional set of switches SW 1 B-SW 6 B and extra pins P 7 and P 8 are also needed in the chip. Flying capacitor Cf 2 is located off chip and coupled to the chip through pins P 7 and P 8 .

An additional switch SW 7 is used when flying capacitors Cf 1 and Cf 2 are coupled in series. In this case, the second terminal of flying capacitor Cf 1 is coupled to the first terminal of capacitor Cf 2 via switch SW 7 . When flying capacitors Cf 1 and Cf 2 are coupled in parallel, then the corresponding A and B switches are closed, such as if the second terminal of flying capacitor Cf 1 should be coupled to capacitor C 18 , then switches SW 5 A and SW 5 B are closed to couple flying capacitors Cf 1 and Cf 2 to capacitor C 18 .

FIG. 5 a depicts an example of using dual flying capacitors Cf 1 and Cf 2 in the first case of the switching scheme according to one embodiment. In this case, flying capacitor Cf in FIG. 2 a is replaced by flying capacitors Cf 1 and Cf 2 . For example, the second terminal for flying capacitors Cf 1 and Cf 2 are coupled to reference voltage Vdd and the first terminal of flying capacitors Cf 1 and Cf 2 are coupled to capacitor C 18 and output V 18 .

The voltage at output V 18 is 1.8 volts. As will be described in more detail below, the voltage across flying capacitors Cf 1 and Cf 2 is 0.6 volts each. Thus, the voltage at the second terminal of flying capacitors Cf 1 and Cf 2 is 2.4 volts (Vdd 0.6V). A voltage difference ΔV of 0.7 volts is provided (Vdd−V 18 −0.5*V 12 =3.1V−1.8V−0.6V=0.7V).

In phase 2 , capacitor C 12 is coupled to flying capacitors Cf 2 and Cf 1 . The voltage across flying capacitors Cf 2 and Cf 1 is Vdd−V 18 volts and is transferred to capacitor C 12 until the charge across both flying capacitors Cf 1 and Cf 2 is 1.2 volts. Thus, the charge is 0.6 volts across each flying capacitor Cf 1 and Cf 2 .

By having a larger ΔV, the resistance R TOTAL =ΔV\(2*n*Ia)=438 milliohms for four time constants. This gives a larger margin for switch sizes, bond wire resistance, and capacitor ESR, if the output current is larger or the reference voltage Vdd is smaller.

FIG. 5 b depicts a second case using dual flying capacitors according to one embodiment. As shown in phase 1 , flying capacitor Cf is replaced by flying capacitors Cf 1 and Cf 2 . In phase 2 a , flying capacitor Cf is replaced by flying capacitors Cf 1 and Cf 2 . In phase 1 , the operation is similar as discussed with respect to FIG. 2 b , except the voltage across flying capacitor Cf is split between flying capacitors Cf 1 and Cf 2 . However, in phase 2 a , the ΔV is greater because the voltage across flying capacitors Cf 1 and Cf 2 is split between them. In phase 2 b , the operation is similar to that described with respect to phase 2 of FIG. 5 a.

FIG. 5 c depicts a third case using dual flying capacitors according to one embodiment. In phase 1 , a circuit is similar to phase 1 a in FIG. 5 a except that flying capacitors Cf 1 and Cf 2 have their second terminal coupled to reference voltage Vdd and their first terminal coupled to capacitor C 12 and output voltage V 12 . In this case, the voltage difference ΔV is increased because the voltage across flying capacitor Cf is split between flying capacitors Cf 1 and Cf 2 . In phase 1 b , the flying capacitor Cf is replaced by flying capacitors Cf 1 and Cf 2 in series. Charge is transferred from capacitor C 18 to flying capacitors Cf 1 and Cf 2 . Also, in phase 2 , flying capacitor Cf is replaced by flying capacitors Cf 1 and Cf 2 in series, which is similar to that shown in phase 2 of FIG. 5 a . In this case, charge across flying capacitors Cf 1 and Cf 2 is transferred to capacitor C 12 .

In the fourth case, flying capacitors Cf 1 and Cf 2 are floating and thus the operation is the same as described with respect to FIG. 2 b.

FIG. 6 depicts a method for maintaining a first voltage level at a first output and a second voltage level at a second output according to one embodiment. At 602 , regulator 100 couples a first switch coupled to a first voltage reference. At 604 , regulator 100 couples a second switch coupled to a second voltage reference.

At 606 , regulator 100 couples a third switch coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. At 608 , regulator 100 couples a fourth switch coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. At 610 , regulator 100 couples a fifth switch coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. At 612 , regulator 100 couples a sixth switch coupled to the first terminal of the first capacitor and the first terminal of the third capacitor.

At 614 , regulator 100 controls the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch to maintain a first voltage level at a first output and a second voltage level at a second output.

As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.