Method and device for converting a digital input signal to an analog output signal

This application is based on and claims the priority under 35 USC 119 of German Patent Application 10 2010 006 634.6, filed on Feb. 3, 2010, the entire disclosure of which is incorporated herein by reference.

The present invention relates to a method and a device for converting a digital input signal to an analog output signal.

Methods and/or devices of the generic kind mentioned above are used in nearly all fields of electrical engineering in which digitally determined data have to be transmitted in analog form to corresponding signal receivers. An important field of application is in vehicle safety systems.

The conversion of digital values into analog signals is usually performed with digital-to-analog converters (DAC) which are in most cases available as integrated circuits. The prices of such converters rise disproportionately to the increases in conversion resolution and speed.

Another, less expensive method is the use of pulse-width modulation systems (PWM). The required PWM signals are generated from digital signals with variable pulse width and subsequently low-pass filtered. One disadvantage of this alternative method is that the resolution depends on the time base of the PWM frequency. This leads to a conflict of objectives between resolution and achievable conversion rate. Another disadvantage is that the signal level of the analog signal to be generated depends on the signal level of the PWM signals, which can make additional adaptation circuits (attenuators, amplifiers, level shifters, etc.) necessary.

Applications often require the highest possible resolution in a precisely given voltage range and at the same time a high conversion rate.

Many applications also require different voltage ranges of the analog output signals. These voltage ranges exhibit manufacturing tolerances. In addition, the voltage ranges vary due to influences of the environment, especially changes of the ambient temperature, and also depending on the lifespan of the signal converter or owing to controlled influences, i.e. intentional adjustment of operating points.

The time base for the pulse-width signal cannot be increased infinitely in most applications. If performing a conversion based on the pulse-width modulation method, the high conversion resolution at a given time base requires a longer signal time and hence a lower signal frequency of the pulse-width modulated intermediate signal. This in turn leads to a lower conversion rate and thus to a slowdown of conversion. The longer signal time also increases the complexity of the subsequent low-pass filtering of the pulse-width modulated intermediate signal, since a low cut-off frequency is required there.

An object of the present invention is therefore to provide a method and/or device for converting a digital input signal to an analog output signal that minimizes the disadvantages mentioned above.

The problem is solved according to the invention with a method comprising the following steps. In the first step, a first and second pulse-width modulated signal is used for generating a first and second analog intermediate signal. The second intermediate signal is converted to a third intermediate signal, said conversion being controlled by a third pulse-width modulated signal. A fourth analog intermediate signal is generated from the third intermediate signal. The analog output signal is then generated from the first intermediate signal and the fourth intermediate signal. The first, second and/or third pulse-width modulated signal is preferably but not necessarily derived from the same digital input signal.

In a preferred embodiment, the second intermediate signal is converted to a third intermediate signal, said conversion being controlled by a third pulse-width modulated signal, and the third intermediate signal is converted by filtering to the fourth analog intermediate signal, wherein the signal portions of the second intermediate signal can pass to the third intermediate signal during the turn-on time and/or pulse duration of the third pulse-width modulated signal, and the signal portions of the second intermediate signal cannot pass to the third intermediate signal during the turn-off time of the third pulse-width modulated signal. During the turn-off time of the third pulse-width modulated signal, an additional reference signal can pass to the third intermediate signal instead of the second intermediate signal, said reference signal being for example an analog signal and being typically but not necessarily a static signal.

The first intermediate signal and the fourth intermediate signal are then superimposed to form the analog output signal, preferably by an adder circuit. The first pulse-width modulated signal is used for regulating the offset proportion of the analog output signal. The second pulse-width modulated signal is used for regulating the distance between the maximum and the minimum value in the analog output signal. The first and second pulse-width modulated signals are preferably set by way of manual or automatic calibration before or during operation of a corresponding device performing this method. The third pulse-width modulated signal, however, is preferably generated from the digital input signal.

The invention's object is further achieved with a device, wherein said device has

a. a first means for generating a first, second and/or third pulse-width modulated signal in dependence on the digital input signal, b. a second means for converting the first pulse-width modulated signal to a first analog intermediate signal, c. a third means for converting the second pulse-width modulated signal to a second analog intermediate signal, d. a fourth means for converting the second analog intermediate signal to a third intermediate signal, e. a fifth means for converting the third intermediate signal to a fourth analog intermediate signal, f. a sixth means for combining the first intermediate signal and the fourth intermediate signal to the analog output signal.

The fourth means converts in said device the second analog intermediate signal to the third intermediate signal, said conversion being controlled by the third pulse-width modulated signal, wherein the fourth means lets the signal portions of the second intermediate signal pass to the third intermediate signal during the turn-on time and/or pulse duration of the third pulse-width modulated signal, and does not let the signal portions of the second intermediate signal pass to the third intermediate signal during the turn-off time of the third pulse-width modulated signal. Instead, the fourth means lets a preferably analog reference signal with a given reference potential pass to the third intermediate signal during the turn-off time of the third pulse-width modulated signal.

For this purpose the fourth means has a controllable switch which is constituted as switchable between two input terminals. The second intermediate signal is applied to a first input terminal and the reference signal with the reference potential is applied to a second input terminal.

The switch switches between the two input terminals, the switching being controlled by the third pulse-width modulated signal, thus transmitting either the second intermediate signal or the reference signal to the output terminal.

The abovementioned first means is preferably a microprocessor or a microcontroller and has at least three outputs for a pulse-width modulated signal. The first means usually generates all three pulse-width modulated signals from the digital input signal.

The sixth means has a superimposing circuit, typically an adder, which sums the first intermediate signal and the fourth intermediate signal to the analog output signal.

The present invention creates a method and/or device for converting a digital input signal to an analog output signal, said method or device being cheaper than known methods or devices and also easier to implement.

In the following the invention will be explained in detail by means of the embodiments and with the aid of the figures. The figures show:

FIG. 1 the method of the invention, using a block diagram,

FIG. 2 an exemplary wiring diagram of the device of the invention,

FIG. 3 a signal diagram for describing the method of the invention.

FIG. 1 shows the method of the invention using a block diagram. According to this, three pulse-width modulated signals (PWM signals) S_p 1 , S_p 2 , S_p 3 are generated.

The first PWM signal S_p 1 is used here to generate an offset proportion of the analog output signal S_aa. The second PWM signal S_p 2 is used to adjust the possible voltage swing of the analog output signal S_aa to the application. The third PWM signal S_p 3 is used to adjust the analog output signal S_aa within the limits predetermined by S_p 1 and S_p 2 , wherein, independent of S_p 1 and S_p 2 , the maximum number of quantization levels and hence the highest possible resolution is always available. These three PWM signals S_p 1 , S_p 2 , S_p 3 are preferably generated independently of each other, and the signal times of the three PWM signals S_p 1 , S_p 2 , S_p 3 are adjustable independently of each other. Therefore the resolutions of the analog intermediate signals S_z 1 , S_z 2 , S_z 3 generated from the PWM signals S_p 1 , S_p 2 , S_p 3 , i.e. by low-pass filtering, are also adjustable independently of each other.

These three signals can all be generated directly or indirectly from the digital input signal S_de which is to be converted to an analog output signal S_aa according to the invention.

The first PWM signal S_p 1 (hereinafter referred to as offset PWM signal) and the second PWM signal S_p 2 (hereinafter referred to as range PWM signal) are adjusted, depending on the application,

once during the calibration of the device of the invention, either during the manufacturing process or following the manufacturing process, on repeated manual calibration during the product life cycle of the device, by automatic calibration at regular intervals during runtime operation of the device, or by automatic calibration at irregular intervals during runtime operation of the device, said automatic calibration being triggered by external or internal events or by user intervention.

In this way the work range or voltage range of the analog output signal S_aa can be optimally adjusted to the application.

The third PWM signal S_p 3 can then be adjusted depending on the digital input signal. With the third PWM signal S_p 3 , the work range limited by the range PWM signal S_p 2 can be optimally resolved.

Since the offset and range PWM signals S_p 1 , S_p 2 are only adjusted on demand and thus provide mostly static signals during the actual digital-to-analog conversion, the filtering of these signals S_p 1 , S_p 2 to analog intermediate signals S_z 1 , S_z 2 does not have a negative impact on the conversion time or conversion rate. The actual conversion is only controlled by the third PWM signal S_p 3 .

The three PWM signals S_p 1 , S_p 2 and S_p 3 can be output signals of a microcontroller 110 . The source of the three PWM signals S_p 1 , S_p 2 , S_p 3 is totally irrelevant in this respect. They can be derived from the digital input signal S_de, but also from one or several analog signals not detailed in this embodiment, or from measured signals received through an interface. The offset and range PWM signals S_p 1 , S_p 2 , which can be calibrated, can also be saved in a memory before processing and read on demand.

As shown in FIG. 2 , the analog intermediate signals S_z 1 , S_z 2 are generated from the corresponding PWM signals S_p 1 , S_p 2 using low-pass filtering 120 , 130 , wherein the two PWM signals S_p 1 , S_p 2 are filtered each by a passive and subsequently by an active low-pass filter 121 , 131 , 122 , 132 according to FIG. 2 . Alternatively the low-pass filtering 120 , 130 can be achieved with one low-pass filter or with one or several low-pass filters of other known filter types. The passive low-pass filters 121 , 131 serve to suppress high frequency components of the offset and range PWM signals S_p 1 , S_p 2 . The active low-pass filters 122 , 132 serve to decouple the impedances of the intermediate signals S_z 1 , S_z 2 from the output terminals of the microcontroller 110 .

The first analog intermediate signal S_z 1 (hereinafter referred to as offset signal) is used for offset compensation on the analog output signal S_aa or for raising the total signal level of the output signal S_aa to fulfill specified signal level requirements. The voltage level Uos of the offset signal S_z 1 is adjustable by changing the signal level of the offset PWM signal S_p 1 correspondingly, as shown in FIG. 3 . The lower voltage limit of the output signal S_aa is determined by the offset signal S_z 1 . The offset signal S_z 1 is fed to an adder 160 , 161 .

The second analog intermediate signal S_z 2 (hereinafter referred to as range signal) determines the voltage interval of the analog output signal S_aa, which is the interval in which the voltage level of the output signal S_aa can vary. Added to the offset signal S_z 1 , the range signal S_z 2 forms the upper voltage limit of the output signal S_aa. The range signal S_z 2 is fed to a controllable analog switch 140 , 141 , wherein said range signal S_z 2 is applied to a first input terminal 1411 . A second input terminal 1412 of the switch 141 is fed with a reference signal S_r. The reference signal S_r is preferably a zero signal (a signal with level 0). The switch 141 is driven by a third PWM signal S_p 3 , wherein said switch 141 lets either the range signal S_z 2 or the reference signal S_r pass to the switch output 1413 , controlled by the third PWM signal S_p 3 . Unlike the other two PWM signals S_p 1 , S_p 2 , the third PWM signal S_p 3 is directly applied to switch 141 without filtering. As a result a third intermediate signal S_z 3 is generated at output 1413 of switch 141 , said third intermediate signal S_z 3 being converted to a fourth analog intermediate signal S_z 4 by low-pass filtering 150 through, for example, a passive and an active low-pass filter 151 , 152 , as shown in FIG. 3 . This fourth analog intermediate signal S_z 4 is also passed to the adder 160 , 161 .

The adder 161 adds both the second and the fourth intermediate signals S_z 2 , S_z 4 together, thus generating the analog output signal S_aa. Optionally, said analog output signal is amplified and signal noise is filtered out 171 , 172 .

The voltage range of the analog output signal S_aa converted according to the invention has a value range that can be freely adapted to the respective application thanks to the range PWM signal S_p 2 , said value range being independent of the signal level of the output terminals of the microcontroller 110 . In addition, the output signal S_aa has a high signal resolution, depending on the signal level of the third PWM signal S_p 3 .

The complete circuit of the device of the invention, as shown in FIG. 2 , and/or all circuit components like the filters 121 , 122 , 131 , 132 , 151 , 152 , 172 , the operational amplifier 171 and the analog switch 141 can be powered by a single voltage source.

Although the invention has been described with reference to specific example embodiments, it will be appreciated that it is intended to cover all modifications and equivalents within the scope of the appended claims. It should also be understood that the present disclosure includes all possible combinations of any individual features recited in any of the appended claims. The abstract of the disclosure does not define or limit the claimed invention, but rather merely abstracts certain features disclosed in the application.

S_de digital input signal

S_aa analog output signal

S_p 1 first pulse-width modulated signal

S_p 2 second pulse-width modulated signal

S_p 3 third pulse-width modulated signal

S_z 1 first analog intermediate signal

S_z 2 second analog intermediate signal

S_z 3 third intermediate signal

S_z 4 fourth analog intermediate signal

S_r reference signal

110 first means for generating a first, second and/or third pulse-width modulated signal S_p 1 , S_p 2 , S_p 3

120 second means for converting the first pulse-width modulated signal S_p 1 is to a first analog intermediate signal S_z 1

121 passive filter

122 active filter

130 third means for converting the second pulse-width modulated signal S_p 2 to a second analog intermediate signal S_z 2

131 passive filter

132 active filter

140 fourth means for converting the second analog intermediate signal S_z 2 to a third intermediate signal S_z 3

141 controllable switch in the fourth means 140

1411 , 1412 input terminal of switch 141

1413 output terminal of switch 141

150 fifth means for converting the third intermediate signal S_z 3 to a fourth analog intermediate signal S_z 4

151 passive filter

152 active filter

160 sixth means for adding the first intermediate signal S_z 1 and the fourth intermediate signal S_z 4 to the analog output signal S_aa microprocessor in the first means 110

161 adder in the sixth means 160

170 amplifier unit

171 amplifier

172 active filter

Uos voltage level of offset signal S_z 1

Ures manually adjustable maximum voltage range of the second analog intermediate signal S_z 2

Uint voltage level of the second analog intermediate signal S_z 2 which is adjustable by changing the signal level of the second offset PWM signal S_p 2 correspondingly