Fabrication of replacement metal gate devices

This application claims priority to U.S. Provisional Ser. No. 61/389,546 filed on Oct. 4, 2010, incorporated herein by reference in its entirety.

This application is related to commonly assigned applications: Ser. No. 13/012,142, filed Jan. 24, 2011; Ser. No. 13/012,821, filed Jan. 25, 2011; and Ser. No. 13/012,836, filed Jan. 25, 2011, all incorporated herein by reference.

The present invention relates to semiconductor fabrication and devices, and in particular to systems and methods for chemical mechanical planarization (CMP) of high-k metal gate structures to achieve a highly planar final structure.

The great success of the complementary metal oxide semiconductor (CMOS) technology can be attributed to transistor scalability. For over a quarter of a century, very little has changed in the basic transistor design except the dimensions. The scaling concept requires that all the physical dimensions (length, width and thickness) be reduced simultaneously. As these physical dimensions start approaching molecular scales, it has become extremely difficult to achieve performance gain by simple device scaling alone. Several strategies involving new device structures and material options are being developed in an attempt to extend the planar transistor design and preserve device scaling beyond ˜50 nm gate length.

One way to solve the device scaling problems is to use different materials in a gate structure. A SiO 2 gate oxide is a material that has enabled scaling of CMOS devices to gain performance improvements in the past. The physical thickness of gate oxide in transistors has been decreasing steadily with the decrease in gate length. For a 90 nm node, for example, the thickness of gate oxide is about 12 Å and experimental transistors with 8 Å gate oxide thickness have been reported. However, continued gate oxide scaling is becoming extremely difficult because the gate oxide leakage in SiO 2 increases with decreasing physical thickness, and SiO 2 can no longer play its role effectively as the gate dielectric.

Methods for polishing to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step removes the dielectric of the gate structure and exposes a gate conductor.

A method for the planarization of high-k metal gate structures is described. The strategy is to use slurries with appropriate selectivity to polish certain materials in preference to other materials to achieve a highly planar final structure. In the case of high-k metal gate devices, a three step CMP process is provided. The first step is a planarization step with an oxide selective slurry stopping on 300 to 600 Å of oxide remaining The second step involves polishing with a slurry that has a selectivity ratio of 1:1:1 with respect to oxide, nitride and polysilicon (poly Si). In next step, a slurry with a high polish rate for nitride and very low polish rates for oxide and poly Si is used. The compositions of the slurries used for the various polish steps are also disclosed.

A method for polishing replacement metal gate structures to planarize oxide layers and expose underlying nitride and polysilicon covered areas includes a first chemical mechanical polish step to remove overburden and planarize oxide layers leaving 300 to 600 Å of oxide remaining; a second chemical mechanical polish step including removal of the oxide layers and exposing underlying nitride and polysilicon covered surfaces with an oxide: nitride: polysilicon selectivity of about 1:1:1 to about 2:1:1 to provide planar topography; a third chemical mechanical polish step to remove the nitride layers and expose the polysilicon layers; and replacing at least a portion of the polysilicon layer with a metal layer to form the metal gate structure.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:

FIGS. 1A-1F are cross-sectional views showing process steps for fabrication of a replacement high-k metal gate structure in accordance with one embodiment; and

FIG. 2 is a block/flow diagram showing a multi-step polish process for replacement high-k metal gate structures in accordance with the present principles.

In accordance with the present principles, methods for planarization of high-k metal gate structures are described. One strategy is to use slurries with appropriate selectivity to polish certain materials in preference to other materials to achieve a highly planar final structure. In the case of high-k metal gate devices, a three step CMP process is provided. In one embodiment, a planarization step is performed on an oxide layer with a selective slurry stopping with approximately 300 to 600 Å of oxide remaining. A next step includes polishing with a slurry that has a selectivity ratio of 1:1:1 with respect to oxide, nitride and polysilicon. Then, a slurry is employed for polishing with a high polish rate for nitride and very low polish rates for oxide and polysilicon. Compositions of the slurries used for the various polish steps are disclosed.

It is to be understood that the flowchart and block diagrams in the Figures may, in some alternative implementations, occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

It is also to be understood that the present invention will be described in terms of given illustrative architectures; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention. Throughout this disclosure oxide, nitride and polysilicon materials are described. However, these materials are illustrative and other materials are also contemplated and within the scope of the invention. In addition, dimensions of thicknesses are described throughout this disclosure. These thickness dimensions are illustrative and other dimensions may be employed in accordance with the present principles.

Devices as described herein may be part of a design for an integrated circuit chip. The chip design may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

The methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

High dielectric constant (high-k) materials such as hafnium and zirconium based oxides and silicates reduce leakage current significantly (e.g., by 100×) and can be used at higher thickness then, e.g., SiO 2 . However, replacing SiO 2 with high-k materials in polysilicon gates leads to two major problems. Because of the defects that form at the gate dielectric/polysilicon gate electrode interface, a voltage at which the transistor switches (threshold voltage V t ) becomes too high. Secondly, electron mobility in the device channel is severely degraded due to surface phonon scattering. Both these problems affect the transistor switching speeds. Use of metal gates with appropriate work functions can provide the right threshold voltages (V t ) and significantly reduce channel mobility degradation. With the combination of high-k gate dielectrics and metal gates, the transistor performance can be significantly improved, and scaling below ˜50 nm becomes possible.

For the fabrication of metal gate devices in conventional CMOS processing, high temperature dopant activation is employed. Most metals with a high work function are stable at these temperatures. However, the interface between the high-k dielectric and work function metal is sensitive to high temperature processing and significant changes occur in the interfacial characteristics. This manifests as V t variations and decreased device reliability. Thus, the materials used in the metal gate stack determine the device integration run path.

A metal gate structure with stack materials that can withstand high temperature processing can be integrated with a gate-first fabrication approach, which may be compatible with conventional CMOS processing. Any metal gate structure with stack materials that cannot withstand high temperature processing needs to be built after all the front-end processing steps, including high temperature junction activation. This integration method involves fabrication of sacrificial polysilicon gates and replacing these sacrificial gates with metal gates (hence the name: replacement metal gate).

Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIGS. 1A-1F , a process flow including several chemical mechanical polishing (CMP) steps for a gate-last or damascene metal gate flow are illustratively shown for a fabrication of a high-k metal gate structure in accordance with the present principles. The following description will illustratively describe the process flow using oxide, nitride and polysilicon on a silicon substrate. However, it should be understood that other materials may be employed.

In FIG. 1A , a device 10 includes a gate oxide layer 14 formed on a substrate 12 . The substrate 12 may include a bulk silicon material, other bulk material or may include a semiconductor-on-insulator (SOI) structure. Other materials or structures may be employed. A polysilicon layer 16 is formed on the oxide 14 followed by a nitride layer 18 . The stack of layers (oxide 14 , polysilicon 16 and nitride 18 ) is patterned to form a gate stack. In a particularly useful embodiment layer 14 may include silicon dioxide or other high k dielectric materials such as oxides and silicates of metals such as Hafnium and the like.

In FIG. 1B , a spacer 20 is formed on side walls of the gate stack. The spacer may be formed by a rapid thermal chemical vapor deposition (RTCVD) of SiN or equivalent process. This may be followed by a spacer etch back to complete the spacers 20 . A silicide process is employed to form silicided junctions 22 .

Planarization processes for high-k metal gate devices will now be described. In FIG. 1C , an oxide layer 24 is formed over the gate structures and the adjacent silicided regions 22 . In FIG. 1D , excess oxide overburden is removed to form a surface 26 . In one embodiment, approximately 300-600 Å of oxide remains over nitride 18 after polishing. For this planarization, an oxide polish slurry with, e.g., a 4:1 oxide to nitride selectivity or ceria/surfactant based slurry may be employed.

In FIG. 1E , another planarization is performed with a slurry with approximately 1:1 oxide to nitride polish rate selectivity. This achieves equal polish rates for oxide and nitride in the various parts of the structure to avoid dishing and erosion due to differences in the polish rates of the two materials, e.g., oxide 24 and nitride 18 and 20 . About 100 to 200 Å of nitride 18 remains after this step to form surface 28 . The oxide 24 is preferably completely removed over the gate structure and the nitride 18 and 20 is exposed everywhere in the chip after this step. To ensure that no oxide 24 is left on top of nitride 18 and 20 , an additional wet etch with, e.g., diluted HF, may be employed.

In FIG. 1F , a next step is to polish nitride 18 and expose polysilicon 16 . This is accomplished by a slurry with high selectivity towards nitride 18 , 20 with very low polish rates for oxide 24 and polysilicon 16 . One advantage of the process is that it provides the flexibility of using slurries with different selectivity to achieve a highly planar post polish topography (surface 30 ). This process employs slurries that are capable of providing different polish rates for oxide 24 , nitride 18 , 20 and polysilicon 16 layers which can be varied to achieve highly planar post polish topography. In subsequent steps, the polysilicon 16 is removed in whole or in part (sacrificial polysilicon gate) and is replaced with a metal where the polysilicon had been removed. The metal forms a metal gate structure (hence the name replacement metal gate). A metal such as copper, aluminum, silver, gold, etc. may be formed in place of the polysilicon 16 . This provides a gate dielectric 14 layer (e.g., SiO 2 or high k dielectric) with a metal gate conductor (to form a structure compatible with a high-k metal gate structure).

Slurry compositions for the three step CMP process for high-k metal gate applications may include the following. For the CMP slurry employed to achieve FIG. 1D , the large initial topography is reduced while removing the bulk of the oxide overburden and leaving a planar oxide layer 24 of approximately 300 Å every where in the semiconductor device (die). Since a high oxide removal rate is desired and virtually no nitride surfaces are exposed during the initial stages of polish, the slurry selectivity is not a factor. This can be achieved by oxide polish slurries with, e.g., approximately 4:1 oxide to nitride selectivity. The oxide slurries may comprise alkaline compounds like potassium hydroxide or ammonium hydroxide and silica abrasives which are selected from fumed silica and colloidal silica. However, to improve the planarity and achieve uniform oxide thickness across various pattern densities, it may be necessary to incorporate additives to the oxide slurries. Ceria/surfactant systems can also be used in this step to achieve the desired planarity and uniformity.

For a CMP slurry to achieve FIG. 1E and/or FIG. 1F , the remaining ˜300 Å of the oxide layer 24 is removed to expose underlying surfaces (nitride 18 , 20 ) and achieve a highly planar final surface 28 that is free of defects such as polish scratches, pits and other blemishes. To achieve high planarity, it is necessary to have approximately the same polish rates for oxide 24 , nitride 18 , 20 and polysilicon 16 covered surfaces. The polish rates of oxide, nitride and polysilicon should not be very high since this inevitably will lead to poor controllability. Thus, it would be highly desirable to have slurry that has polish rates in the range of 300 to 600 Å/min for the three materials. This will provide appropriate polish times with good controllability and allow over-polish margins to planarize hard to polish structures.

The polish rates of different materials vary with line width, pattern density and feature size in an actual circuit layout. The local polish rates of different materials in patterned structures are very complex functions of the polish rates of the same materials in blanket wafers. Thus, it is necessary to optimize the slurry selectivity by polishing patterned wafers and measuring the planarity experimentally to ensure that the desired goals are achieved. Since the die layouts vary between technology nodes and even among different products in the same technology node, it is highly desirable to be able to change the polish rate selectivity by varying the concentrations of the components in the slurry. Thus, polish rate selectivity should be “tunable” within a range for the slurry system to be usable across a wide range of products and technology nodes. The ability to tune the polish rate selectivity is a factor in the polish steps for FIGS. 1E and 1F in achieving a highly planar final surface using the present methods.

A slurry according to the present embodiments may include the following components: a) Abrasive, b) pH modulator, c) Organic acid. a) Abrasive: The abrasive may be at least one type of abrasive particle selected from inorganic and/or organic materials. Examples of the inorganic abrasive particles include silica, alumina, titania, zirconia, ceria, and the like. Examples of the silica may include fumed silica, silica synthesized by a sol-gel method, and colloidal silica. The fumed silica may be obtained by reacting silicon tetra chloride with oxygen and water in gaseous phase. The silica synthesized by the sol-gel method may be obtained by hydrolysis and/or condensation of an alkoxysilicon compound. The colloidal silica may be obtained by hydrolysis of purified silicon compounds in solution phase. Examples of the organic particles may include polyvinyl chloride, styrene (co)polymer, polyacetal, polyester, polyamide, polycarbonate, olefin (co)polymers, phenoxy resins, and acrylic (co)polymers. Examples of the olefin (co)polymers include polyethylene, polypropylene, poly-1-butene, and poly-4-methyl-1-pentene. Examples of the acrylic (co)polymers include polymethyl methacrylate and the like. An average particle diameter of the abrasive may be in the range 5 to 500 nm, more preferably 20 to 150 nm. An appropriate polishing rate can be achieved using the abrasive particles having an average diameter within this range. The colloidal silica may be obtained commercially (e.g., from Fuso Chemical Co., Ltd., Japan) with a primary particle diameter of, e.g., 35 nm. This colloidal silica abrasive is an example of a commercial silica abrasive and is used in that capacity in the examples mentioned herein.

b) pH modulator: The pH of the slurry according to the present embodiments is in the range 1 to 11 and preferably 2 to 6. An appropriate polish rate can be achieved by adjusting the pH of the slurry to a value within this range. Examples of pH modulators may include organic bases, inorganic bases, and inorganic acids. Examples of organic bases include tetramethylammonium hydroxide, triethylamine, and the like. Examples of the inorganic bases may include ammonium hydroxide, potassium hydroxide, and sodium hydroxide. Examples of the inorganic acids may include nitric acid, sulfuric acid, phosphoric acid, and hydrochloric acid.

c) Organic acid: Organic acid is used as an accelerator for nitride polishing. Various organic acids such as monobasic acids (e.g., monocarboxylic acids), dibasic acids (e.g., dicarboxylic acids), polybasic acids (e.g., polycarboxylic acids), and carboxylic acids with substituted groups (hydroxyl, amine) can be used. Examples of such organic acids may include saturated acids, unsaturated acids, aromatic acids, and aliphatic acids. Examples of the saturated acids may include formic acid, acetic acid, butyric acid, oxalic acid, malonic acid, succinic acid, glutaric acid, and adipic acid. Examples of the acids containing hydroxyl groups may include lactic acid, malic acid, tartaric acid, and citric acid. Examples of the unsaturated acids include maleic acid and fumaric acid. Examples of the aromatic acids may include benzoic acid and phthalic acid. It is preferable to use an organic acid having two or more carboxylic acid groups to obtain high polish rates of nitride. The potassium or ammonium salts of these organic acids may also be used.

Other components: The addition of other ingredients into the slurry may be provided to tune the oxide to nitride (and to polysilicon) selectivity. The slurry according to these embodiments may include a surfactant, if necessary. Examples of surfactants may include anionic, nonionic, and cationic surfactants. Examples of anionic surfactants may include a surfactant containing at least one functional group selected from a carboxyl group (—COOX), a sulfonic acid group (—SO 3 X), and a phosphate group (—HPO 4 X) (wherein X represents hydrogen, ammonium, or a metal). Examples of the anionic surfactants may include aliphatic and aromatic sulfates and sulfonates, and phosphate salts. Compounds such as potassium dodecylbenzenesulfonate, ammonium dodecylbenzenesulfonate, sodium alkylnaphthalenesulphonate, alkyl sulfosuccinate, potassium alkenylsuccinate may be used. Salts of fatty acids like potassium oleate may be employed. These anionic surfactants may be used either individually or in combination with other surfactants. Examples of the nonionic surfactants include polyoxyethylene alkyl ethers, ethylene oxide-propylene oxide block copolymers, acetylene glycol, ethylene oxide addition product of acetylene glycol, acetylene alcohol, and the like. Note that a nonionic polymer such as polyvinyl alcohol, cyclodextrin, polyvinyl methyl ether, or hydroxyethylcellulose may also be used. Examples of the cationic surfactants may include an aliphatic amine salts and aliphatic ammonium salts. In addition, polyelectrolytes such as poly (acrylic acid) and their salts such as sodium, potassium and ammonium can also be added during the polishing to control the selectivity. The present embodiments may include the functions of the components of the slurry which are further described below by way of examples. Note that the present invention is not limited to the following examples.