Power switch for decreased ramp rate

The present invention relates generally to an input power supply for an integrated circuit and more particularly, to a power switch for preventing a false electrostatic discharge (ESD) trigger in an input/output pad of an integrated circuit.

Recently, there has been a lot of development in the field of Integrated Circuit (IC) devices. The rapidly decreasing size of these devices has led to the development of System on Chip (SoC) designs. A SoC can be referred to as a system in which all the components of an electronic device are integrated on a single IC. These SoC designs can be packaged in various ways, where each package is designed for a particular function. This helps reduce cost as the same die can be sold in different packages, some with limited pin count.

Low power SoC designs as well as multi-package options have led to switchable supply requirements becoming an important consideration. Traditionally, the nonfunctional I/O segments of an IC were left unpowered. However, this resulted in significant loss of desired functionality of the device. Further, powering each I/O segment in an IC is avoided due to limitations in pin count and other packaging constraints.

Power switches may be used for providing power to the I/O segment, but these power switches operate on a resistive start-up, which is not ideal for use as I/O supply due to a fast ramp rate of the output potential. The fast ramp rate can activate a false trigger of the electrostatic discharge circuitry present within the pads of the IC, resulting in a large power loss. FIGS. 1A , 1 B AND 1 C illustrate the behavior of a traditional power switch, in particular the voltage-time characteristics of an input supply, an output supply and a control signal. The input signal, as illustrated in FIG. 1A , is a ramp signal that starts at time t 1 and attains a maximum value at time t 2 . At time t 3 , the input reaches a threshold value V th , which triggers the power switch. When triggered, the power switch produces the output signal at time t 4 as shown in FIG. 1B . A control signal, as illustrated in FIG. 1C , is activated externally to determine the threshold V th . The output signal generated by the power switch ramps up at a fast rate to attain its maximum value at t 5 . The short duration (t 4 -t 5 ) of the ramp up of output voltage can cause a false trigger due to ESD. The size of a power switch may be reduced to prevent the false trigger, but this reduces the drive capability and cause the output to drop when in operation.

It would be advantageous to have a switch that provides an output supply potential to the IC and prevents generation of a false trigger due to electrostatics discharge. It also would be advantageous if the power switch has good drive capability to ensure that the output does not drop during operation.

The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements.

FIG. 1A is a timing diagram illustrating variation of an input potential of a conventional power switch;

FIG. 1B is a timing diagram illustrating variation of an output potential of the conventional power switch;

FIG. 1C is a timing diagram illustrating variation of a control input of the conventional power switch;

FIG. 2 is a schematic block diagram of an exemplary environment in which various embodiments of the present invention may be practiced;

FIG. 3 is a schematic block diagram illustrating system elements for generating a stepped profile supply potential for an integrated circuit in accordance with an embodiment of the present invention;

FIG. 4 is a schematic block diagram illustrating a supply potential generation block and a control block in accordance with an embodiment of the present invention;

FIG. 5A is a timing diagram illustrating a supply potential output profile of a supply potential generation block in accordance with an embodiment of the present invention;

FIG. 5B is a timing diagram illustrating a control signal output of a control block in accordance with an embodiment of the present invention;

FIG. 6 is a flowchart illustrating the generation of a stepped profile supply potential for an integrated circuit in accordance with an embodiment of the present invention; and

FIG. 7 is a schematic block diagram illustrating system elements for providing a switchable supply potential for an integrated circuit in accordance with another embodiment of the present invention.

The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention.

In an embodiment of the present invention, a system for generating a stepped profile supply potential for an integrated circuit includes a supply potential generation block and a control block. The supply potential generation block includes a first plurality of switching devices that are connected in a predetermined manner to generate the stepped profile supply potential. The stepped profile can be characterized by a predetermined step size and predetermined step duration for each step. The control block generates a plurality of control signals that are provided to the supply potential generation block. The control signals determine the predetermined step duration of the stepped profile supply potential.

In another embodiment of the present invention, a system for providing a switchable supply potential for an integrated circuit is provided. The system includes an input power supply, a first power switch, a second power switch and a comparator circuit. The first power switch is connected to the input power supply and generates a first switchable supply potential. The second power switch is also connected to the input power supply and generates a second switchable supply potential with a stepped profile. Further, the comparator circuit is connected to the first power switch, the second power switch, and the input power supply. The comparator circuit switches between the first and second switchable supply potentials based on a predetermined criterion to generate the desired switchable supply potential.

In accordance with another embodiment of the invention, a method for generating a stepped profile supply potential for an integrated circuit is provided. The method includes generating a plurality of control signals by a control block. The control signals enable switching of at least one of a first plurality of switching devices of a supply potential generation block, wherein each of the plurality of switching devices is connected in a predetermined manner. The method further involves generating a stepped profile supply potential with the supply potential generation block. The stepped profile can further be characterized by a step size and a step duration. The step size corresponds to a potential drop across a switching device and the step duration is determined in accordance with the control signals.

The systems and method described above facilitate a reduction in the number of power pins in integrated circuits with pad limited designs. Further, each of the I/O segments of the IC can be connected to prevent any loss in functionality. In addition, the system can be used with a conventional power switch to ensure good drive and that the output does not droop under run conditions. The system also can be used in a System on Chip (SoC) to provide improved power sequencing. The system may be enabled or disabled based on the requirements of a particular package.

In accordance with the present invention, a system for generating a stepped profile supply potential for an integrated circuit (IC) is provided. FIG. 2 is a schematic block diagram of an exemplary environment in which various embodiments of the present invention may be practiced. The system 200 illustrates a power switch 202 that receives an input potential 204 and provides a supply potential 206 to a switchable Input/output (I/O) segment (not shown in the FIG.) of an integrated circuit. The power switch 202 may be used to supply a switchable I/O segment with an input potential that is different from the input potential supplied to powered I/O segment.

Referring back to the characteristics illustrated in FIG. 1A , the power switch 202 is inactive at t 1 , when the input is ramping at a slow ramp rate as this may lead to undesired power output at the I/O segment, which may cause problems in a package where the input potential 204 and the supply potential output 206 are different. Hence, to overcome the above problems, the power switch 202 is activated in accordance with the requirements of the respective switchable I/O segment. In accordance with the invention, a control signal 208 is provided for activating or deactivating the power switch 202 in accordance with the package to which power is being supplied.

FIG. 3 is a block diagram illustrating a system 300 for generating a stepped profile supply potential for integrated circuits in accordance with an embodiment of the present invention. The system 300 includes a power switching system 302 , an input potential 304 , a supply potential output switch 306 and supply potential output 308 . The power switching system 302 further includes a supply potential generation block 310 and a control block 312 .

The power switching system 302 receives the input potential 304 and provides the supply potential output 308 through the supply potential generation block 310 . In accordance with one embodiment of the invention, the supply potential generation block 310 includes a plurality of switching devices. In various embodiments, the switching devices may include NMOS devices, PMOS devices, transistors, diodes or other switching devices. Each of the plurality of switching devices may be connected in a predetermined manner to obtain an output having a stepped profile. The configuration and internal connections of the supply potential generation block 310 will be discussed in greater detail in conjunction with FIG. 4 . The switching devices are controlled by control signals provided by the control block 312 . The control signals switch the switching devices and hence determine the step duration of the stepped profile of the output 308 . A potential drop across each of the plurality of switching devices determines the step size of the stepped profile supply potential.

FIG. 4 is a schematic block diagram illustrating the supply potential generation block 310 and the control block 312 of FIG. 3 in accordance with an embodiment of the present invention. The supply potential generation block 310 includes a first plurality of switching devices 402 a , 402 b , to 402 n (referred to collectively as 402 ) and a second plurality of switching devices 404 a , 404 b , to 404 n (referred to collectively as 404 ). The control block 312 includes a clock generation circuit 406 and a plurality of flip flops 408 a , 408 b to 408 n (referred to collectively as 408 ). The clock generation circuit 406 includes a ring oscillator 410 and a clock divider 412 . The supply potential generation block 310 receives input power from the input potential 304 (i.e., Vdd) and provides the supply potential output 414 to the supply potential output switch 306 . In one embodiment, the output of the flip flops 408 is inverted with a set of inverters 416 . The inverted outputs are used as inputs for the second plurality of switching devices 404 .

The first plurality of switching devices 402 may include PMOS devices, NMOS devices, transistors, diodes or other switching devices. In one embodiment of the invention, as shown in FIG. 4 , each of the first plurality of switching devices 402 is an NMOS device. The NMOS devices are connected in series such that the source of NMOS device is connected to the gate of the subsequent NMOS device and so on. Further, as illustrated, the drain of each of the plurality of NMOS devices is connected to the input potential 304 . In one embodiment of the invention, the second plurality of switching devices 404 is used for switching each of the first plurality of switching devices 402 . The second plurality of switching devices 404 may include PMOS devices, NMOS devices, transistors, diodes or other switching devices. In an embodiment of the invention, PMOS devices are employed as the switching devices in the second plurality of switching devices 404 and are controlled using control signals e 1 , e 2 to en. Signals e 1 , e 2 to en are obtained by inverting the output of the flip-flops 408 a , 408 b to 408 n . Each of the second plurality of switching devices 404 switch the first plurality of switching devices 402 respectively, in accordance with the control signals e 1 , e 2 , to en. In another embodiment of the present invention, NMOS switching devices can be used for second plurality of switching devices (not shown in FIG. 4 ). In such an embodiment, inverters need not be connected to the flip flops 408 and the outputs of the flip flops 408 are provided directly to the second plurality of switching devices 404 .

The control block 312 includes a clock generation circuit 406 for generating a clock signal. The frequency of the clock signal is determined by the ring oscillator 410 and the clock divider circuit 412 . The clock signal is provided to the clock input of the flip flops 408 . In one embodiment of the invention, each of the plurality of flip flops 408 is a delay flip flop. The plurality of flip flops 408 is connected in series such that the output of each flip flop is provided to the input of a subsequent flip flop and the first flip flop 408 a receives an input from the input potential 304 . The series connection enables generation of the control signals e 1 to en at fixed intervals, the fixed interval being determined by the frequency of the clock signal generated by the clock generation circuit 406 .

Each of the plurality of flip flops 408 also is controlled by a reset control signal (not shown). The reset control signal ensures that when the switch is inactive, the output of each of the flip flops 408 is 0 and hence each of the switching devices of the second plurality of switching devices 404 is open. The frequency of the clock signal is determined by an ESD trigger timeout time. The ESD trigger timeout is a time interval for which the ESD trigger is active before it finally dies out. The switch control is spaced in accordance with ESD trigger timeout to ensure that every voltage step is spaced apart sufficient for any minor ESD trigger to subside before the next step arrives.

FIG. 5A is a timing diagram illustrating the supply potential output profile of the supply potential generation block 310 and FIG. 5B is a timing diagram illustrating the control signal output of the control block 312 .

At t=0, each of the plurality of switching devices 402 are switched ON. The supply potential output 414 at this stage is equal to a potential drop across n NMOS devices and can be represented as:

V outi =V dd −nV th ;

where V th is the threshold potential across each of the plurality of NMOS devices in an ON state. The number n of switching devices is fixed such that the above value V outi =0.

At t=t 0 , the control block 312 generates a control signal e 1 by activating the flip flop 408 a . The control signal e 1 enables switching OFF of the NMOS device 402 a , and enables generation of a potential drop V out −V dd −(n−1)V th , as represented in FIG. 5A , at the supply potential output 308 .

FIG. 5B illustrates the generation of control signals e 2 , e 3 , to en during subsequent intervals of duration 2t 0 , 3t 0 and so on. Corresponding to the control signals e 2 , e 3 , to en, each of the plurality of n switching devices is switched OFF one by one, at regular intervals of t 0 , resulting in a supply potential output 308 is illustrated by curve 502 in FIG. 5A . The output potential at any time pt 0 can be defined as V out =V dd −(n−p)V th , where p relates to switching OFF of the first p switching devices.

Referring now to FIG. 6 , a flowchart illustrating a method for generating a stepped profile supply potential for an integrated circuit in accordance with an embodiment of the present invention is shown. At a first step 602 , the control block 312 generates the control signal e 1 at time t=t 0 . The duration t=t 0 is determined by the clock generation circuit 406 , which generates a clock signal. The clock signal enables the flip flop 408 a to generate a first one of the plurality of control signals. As previously discussed, the plurality of NMOS devices 402 a , 402 b to 402 n are initially switched ON such that there is a potential drop of V dd −nV th =0 at the output of the supply generation block. At step 604 , the control signal e 1 enables the switching OFF of one of the first plurality of switching devices. In an embodiment of the invention, the control signal e 1 enables the first PMOS switching device 404 a of the second plurality of switching devices, which further enables the switching OFF (bypass) of the first NMOS switching device 402 a of the first plurality of switching devices. At step 606 , the output supply potential V out =V dd −(n−1)V th is obtained at the output supply potential switch 306 in accordance with the switching OFF of the first NMOS switching device 402 a of the first plurality of switching devices 402 . The above steps are repeated with the generation of a subsequent control signal e 2 at a time 2t 0 and so on. With subsequent switching OFF of the switching devices 402 b , 402 c to 402 n , the output signal continues to increase in accordance with the stepped profile as already discussed in conjunction with FIGS. 5A and 5B .

FIG. 7 is a block diagram illustrating a power switch 700 for providing a switched output potential for input to an integrated circuit in accordance with an embodiment of the present invention. The power switch 700 includes an input power supply 702 , a first power switch 704 , a second power switch 706 , a comparator 708 , a switchable supply potential output terminal 710 , a comparator output terminal 712 , a comparator output supply terminal 714 , and a package decode input terminal 716 .

In one embodiment of the invention, the first power switch 704 represents a conventional power switch and exhibits characteristics discussed in reference with FIGS. 1A , 1 B and 1 C. The first power switch 704 receives an input from the input power supply 702 and provides an output to an input terminal of the comparator 708 and the switchable supply potential output terminal 710 . The second power switch 706 exhibits stepped output characteristics as illustrated in FIG. 5A . The second power switch 706 receives an input from the input power supply 702 and provides an output to another input terminal of the comparator 708 and also to the switchable supply potential output terminal 710 . The comparator 708 is connected to the first output switch 704 , the second output switch 706 and the input power supply 702 .

The comparator 708 compares the inputs received from at least one of the first and second power switches and the power supply 702 and generates a comparator output (compout) 712 . Compout is provided to the power switch 700 at the comparator output supply terminal 714 . Note, compout also could be provided with a signal route directly to the first and second power switches 704 , 706 instead of via a terminal like the terminal 714 . In one embodiment of the invention, compout is active when the input received from at least one of the first and second power switches exceeds a predetermined threshold V th2 . When the input is below the predetermined threshold potential V th2 , compout is inactive. In this case, the first power switch 704 is inactive and the switchable supply potential output terminal 710 is operated in accordance with the active second power switch 706 . Further, when the comparator input is above the threshold potential V th2 , compout is active. In this case, the first power switch 704 is activated and the second power switch 706 is turned OFF. The switchable supply potential output terminal 710 is then operated in accordance with the active first power switch 704 .

In one embodiment of the invention, the power switch 700 further includes a package decode input terminal 716 for receiving a package decode bit. The package decode bit contains information to activate the power switch 700 and is further stored in an external memory. In an embodiment of the invention, an active package decode bit activates the power switch 700 to generate a controlled output at the switchable supply potential output terminal 710 . In another embodiment of the invention, an active package decode bit disables the power switch 700 and the integrated circuit I/O segment is operated directly from the power supply 702 .

While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.