Scan driver, method of driving the scan driver, and organic light-emitting display including the scan driver

This application claims priority to and the benefit of Korean Patent Application No. 10-2010-0043051, filed on May 7, 2010, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field

The present invention relates to a scan driver, a method of driving the scan driver, and an organic light-emitting display including the scan driver.

2. Description of the Related Art

Organic light-emitting displays are used as display devices for computers, mobile phones, personal digital assistants (PDAs), and other information devices. Compared to a cathode ray tube (CRT) device, an organic light-emitting display is relatively light and small and has excellent light emitting efficiency, brightness, viewing angle, and response speeds.

To drive a plurality of pixels, a scan driver included in an organic light-emitting display applies scan signals to scan lines, so that desired data is applied to pixels by a data driver.

Embodiments according to the present invention provide a scan driver, which includes a plurality of stages, and is capable of overlapped driving of scan signals output by each of the stages, a method of driving the scan driver, and an organic light emitting display device including the scan driver.

In one embodiment according to the present invention, a scan driver includes: a first stage having a clock terminal electrically coupled to a first clock line and a control terminal electrically coupled to a first control line; and a second stage having a clock terminal electrically coupled to a second clock line and a control terminal electrically coupled to a second control line.

The first stage may include an input terminal electrically coupled to an initial input line, a next stage start terminal electrically coupled to an input terminal of the second stage, and an output terminal electrically coupled to a first scan line.

The second stage may include an input terminal electrically coupled to a next stage start terminal of the first stage, a next stage start terminal electrically coupled to an input terminal of a next stage, and an output terminal electrically coupled to a second scan line.

Each of the first stage and the second stage may include: a first switching device having a control electrode electrically coupled to an input terminal, the first switching device being coupled between a first power voltage line and a first node; a second switching device having a control electrode electrically coupled to the input terminal, the second switching device being coupled between a second power voltage line and a second node; a third switching device having a control electrode electrically coupled to the first switching device; a fourth switching device having a control electrode electrically coupled to the first switching device, the fourth switching device being coupled between the third switching device and the second node, wherein the third switching device is coupled between the first power voltage line and the fourth switching device; a fifth switching device having a control electrode electrically coupled to the first control line, the fifth switching device being coupled between the second power voltage line and the first node; a sixth switching device having a control electrode electrically coupled to the first node, the sixth switching device being coupled between the first power voltage line and a third node; a seventh switching device having a control electrode electrically coupled to the second node, the seventh switching device being coupled between the third node and the clock terminal; an eighth switching device having a control electrode electrically coupled to the first node, the eighth switching device being coupled between the first power voltage line and an output terminal; a ninth switching device having a control electrode electrically coupled to the second node, the ninth switching device being coupled between the output terminal and the second power voltage line; a first capacitor coupled between the first power voltage line and the control electrode of the sixth switching device; a second capacitor coupled between the control electrode of the seventh switching device and the third node; and a third capacitor coupled between the control electrode of the ninth switching device and the output terminal.

The input terminal of the first stage may be electrically coupled to an initial input line, the output terminal of the first stage may be electrically coupled to a first scan line, and a next stage start terminal of the first stage may be electrically coupled to the input terminal of the second stage.

The input terminal of the second stage may be electrically coupled to a next stage start terminal of the first stage, the output terminal of the second stage may be electrically coupled to a second scan line, and a next stage start terminal of the second stage may be electrically coupled to the input terminal of a next stage.

The switching devices may include PMOS transistors.

The scan driver may further include a tenth switching device having a control electrode electrically coupled to a reset terminal, the tenth switching device being coupled between the first node and the second power voltage line.

The scan driver may further include a third stage, wherein a clock terminal of the third stage is electrically coupled to the first clock line, and a control terminal of the third stage is electrically coupled to a third control line.

The scan driver may further include a third stage, wherein a clock terminal of the third stage is electrically coupled to a third clock line, and a control terminal of the third stage is electrically coupled to a third control line.

In another embodiment according to the present invention, a method of driving a scan driver including a plurality of stages sequentially outputting output signals, is provided. The method includes: outputting a first output signal to a first scan line in response to an initial input signal and outputting a first next stage start signal to a next stage in response to a first clock signal; outputting a second output signal to a second scan line in response to the first next stage start signal; stopping the outputting of the first output signal in response to a first control signal while the second output signal is being output; and stopping the outputting of the second output signal in response to a second control signal, wherein the first output signal and the second output signal partially overlap each other.

The outputting the second output signal to the second scan line in response to the first next stage start signal may include outputting the second output signal to the second scan line in response to the first next stage start signal and outputting a second next stage start signal to a next stage in response to a second clock signal, wherein the method may further include outputting a third output signal to a third scan line in response to the second next stage start signal, wherein the stopping the outputting of the second output signal in response to the second control signal may include stopping the outputting of the second output signal in response to the second control signal while the third output signal is being output, wherein the method may further include stopping the outputting of the third output signal in response to a third control signal, and wherein the second output signal and the third output signal may partially overlap each other.

In another exemplary embodiment according to the present invention, an organic light emitting display device includes: an organic light emitting display panel; a scan driver configured to sequentially provide scan signals to the organic light emitting display panel via a plurality of scan lines; and a data driver configured to provide data signals to the organic light emitting display panel via a plurality of data lines, wherein the scan driver includes: a first stage having a clock terminal electrically coupled to a first clock line and a control terminal electrically coupled to a first control line; and a second stage having a clock terminal electrically coupled to a second clock line and a control terminal electrically coupled to a second control line.

The first stage may include an input terminal electrically coupled to an initial input line, a next stage start terminal electrically coupled to an input terminal of the second stage, and an output terminal electrically coupled to a first scan line of the plurality of scan lines.

The second stage may include an input terminal electrically coupled to a next stage start terminal of the first stage, a next stage start terminal electrically coupled to an input terminal of a next stage, and an output terminal electrically coupled to a second scan line of the plurality of scan lines.

Each of the first stage and the second stage may include: a first switching device having a control electrode electrically coupled to an input terminal, the first switching device being coupled between a first power voltage line and a first node; a second switching device having a control electrode electrically coupled to the input terminal, the second switching device being coupled between a second power voltage line and a second node; a third switching device having a control electrode electrically coupled to the first switching device; a fourth switching device having a control electrode electrically coupled to the first switching device, the fourth switching device being coupled between the third switching device and the second node, wherein the third switching device is coupled between the first power voltage line and the fourth switching device; a fifth switching device having a control electrode electrically coupled to the first control line, the fifth switching device being coupled between the second power voltage line and the first node; a sixth switching device having a control electrode electrically coupled to the first node, the sixth switching device being coupled between the first power voltage line and a third node; a seventh switching device having a control electrode electrically coupled to the second node, the seventh switching device being coupled between the third node and the clock terminal; an eighth switching device having a control electrode electrically coupled to the first node, the eighth switching device being coupled between the first power voltage line and an output terminal; a ninth switching device having a control electrode electrically coupled to the second node, the ninth switching device being coupled between the output terminal and the second power voltage line; a first capacitor coupled between the first power voltage line and the control electrode of the sixth switching device; a second capacitor coupled between the control electrode of the seventh switching device and the third node; and a third capacitor coupled between the control electrode of the ninth switching device and the output terminal.

The input terminal of the first stage may be electrically coupled to an initial input line, the output terminal of the first stage may be electrically coupled to a first scan line of the plurality of scan lines, and a next stage start terminal of the first stage may be electrically coupled to the input terminal of the second stage.

input terminal of the second stage may be electrically coupled to a next stage start terminal of the first stage, the output terminal of the second stage may be electrically coupled to a second scan line of the plurality of scan lines, and a next stage start terminal of the second stage may be electrically coupled to an input terminal of a next stage.

The switching devices may include PMOS transistors.

Each of the first stage and the second stage may further include a tenth switching device having a control electrode electrically coupled to a reset terminal, the tenth switching device being coupled between the first node and the second power voltage line.

The organic light emitting display device may further include a third stage, wherein a clock terminal of the third stage is electrically coupled to the first clock line, and a control terminal of the third stage is electrically coupled to a third control line.

The organic light emitting display device may further include a third stage, wherein a clock terminal of the third stage is electrically coupled to a third clock line, and a control terminal of the third stage is electrically coupled to the third control line.

The above and other features and aspects of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram showing a configuration of an organic light-emitting display according to an embodiment of the present invention;

FIG. 2 is a diagram of a scan driver shown in FIG. 1 , according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of the scan driver shown in FIG. 2 , according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating an example of an operation of the scan driver circuit shown in FIG. 3 ;

FIGS. 5 and 6 are circuit diagrams illustrating an example of an operation of the scan driver circuit shown in FIG. 3 ;

FIG. 7 is a diagram of a scan driver according to another embodiment of the present invention;

FIG. 8 is a timing diagram illustrating an example of an operation of the scan driver shown in FIG. 7 ;

FIG. 9 is a block diagram of a scan driver according to another embodiment of the present invention;

FIG. 10 is a timing diagram illustrating an example of an operation of the scan driver shown in FIG. 9 ;

FIG. 11 is a circuit diagram of the scan drivers of FIGS. 2 , 7 , and 9 , according to another embodiment of the present invention.

As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to particular modes of practice, and it is to be appreciated that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the present invention are encompassed in the present invention. In the description of the present invention, certain detailed explanations of related art are omitted when it is deemed that they may unnecessarily obscure the essence of the invention.

While such terms as “first,” “second,” etc., may be used to describe various components, such components are not limited to the above terms. The above terms are used only to distinguish one component from another.

The terms used in the present specification are merely used to describe particular embodiments, and are not intended to limit the present invention. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. In the present specification, it is to be understood that the terms such as “including” or “having,” etc., are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or may be added.

Embodiments of the invention will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number, and redundant explanations are generally omitted.

FIG. 1 is a block diagram showing a configuration of an organic light emitting display (e.g., an organic light emitting display device) 100 according to an embodiment of the present invention.

Referring to FIG. 1 , the organic light emitting display 100 includes a scan driver 110 , a data driver 120 , and an organic light emitting display panel (referred to hereinafter as a panel 130 ).

The scan driver 110 may sequentially provide scan signals to the panel 130 via scan lines Scan[ 1 ], Scan[ 2 ], . . . , Scan [n].

The data driver 120 may sequentially provide data signals to the panel 130 via data lines Data[ 1 ], Data[ 2 ], . . . , Data[m].

Furthermore, the panel 130 may include a plurality of scan lines Scan[ 1 ], Scan[ 2 ], . . . , Scan[ 3 n ], which are arranged in (e.g., extend in) a row direction, a plurality of data lines Data[ 1 ], Data[ 2 ], . . . , Data[m], which are arranged in (e.g., extend in) a column direction, and pixels 131 , which are located at crossing regions of the plurality of scan lines Scan[ 1 ], Scan[ 2 ], . . . , Scan[ 3 n ] and the plurality of data lines Data[ 1 ], Data[ 2 ], . . . , Data[m].

Here, the pixel 131 may be formed in a pixel region defined by two adjacent scan lines and two adjacent data lines. As described above, scan signals may be provided to the scan lines Scan[ 1 ], Scan[ 2 ], . . . , Scan[ 3 n ] by the scan driver 110 , whereas data signals may be provided to the data lines Data[ 1 ], Data[ 2 ], . . . , Data[m] by the data driver 120 .

The panel 130 receives a first power voltage (not shown) and a second power voltage (not shown) from outside and provides the first power voltage and the second power voltage to each of the pixels 131 . Each of the pixels 131 receiving the first power voltage and the second power voltage emits light from a light emitting device (e.g., organic light emitting diode (OLED)) included therein in accordance with data signals by controlling a current from the second power voltage to the first power voltage. For example, the second power voltage may be at a higher potential than the first power voltage.

FIG. 2 is a diagram of the scan driver 110 shown in FIG. 1 , according to an embodiment of the present invention.

Referring to FIG. 2 , the scan driver 110 includes a plurality of stages, including a first stage S 1 , a second stage S 2 , a third stage S 3 , a fourth stage S 4 , a fifth stage S 5 , and so on.

A clock terminal CLK of the first stage S 1 is electrically coupled to a first clock line CLK 1 , and a flmup terminal FLMUP (e.g., a control terminal) of the first stage S 1 is electrically coupled to a first FLMUP line FLMUP 1 (e.g., a first control line). Furthermore, an input terminal IN of the first stage S 1 is electrically coupled to an initial input line SP. The first stage S 1 receives an initial input signal from the initial input line SP through the input terminal IN, and outputs a first scan signal to a first scan line Scan[ 1 ] via an output terminal OUT. Furthermore, a next terminal NEXT (e.g., a next stage start terminal) of the first stage S 1 is electrically coupled to an input terminal IN of the second stage S 2 . The first stage S 1 provides a first next signal (e.g., a first next stage start signal) through the next terminal NEXT to the input terminal IN of the second stage S 2 .

A clock terminal CLK of the second stage S 2 is electrically coupled to a second clock line CLK 2 , and the flmup terminal FLMUP (e.g., the control terminal) of the second stage S 2 is electrically coupled to a second FLMUP line FLMUP 2 (e.g., a second control line). Furthermore, the input terminal IN of the second stage S 2 is electrically coupled to the next terminal NEXT of the first stage S 1 . The second stage S 2 receives the first next signal from the first stage S 1 through the input terminal IN, and outputs a second scan signal to a second scan line Scan[ 2 ] via an output terminal OUT. Furthermore, a next terminal NEXT (e.g., a next stage start terminal) of the second stage S 2 is electrically coupled to an input terminal IN of the third stage S 3 . The second stage S 2 outputs a second next signal (e.g., a second next stage start signal) to the input terminal IN of the third stage S 3 through the next terminal NEXT. In other words, a next terminal of a previous stage is electrically coupled to an input terminal of a current stage, so that the current stages receive a next signal from the previous stage and outputs a scan signal. According to embodiments of the present invention, a next signal is not affected (or substantially not affected) by the load of an output terminal, and thus a next signal from the current stage is provided to (or used by) the next stage without a delay (e.g., RC delay) or with a reduced delay (e.g., as compared to when the output signal is provided to the next stage).

The third through fifth stages S 3 through S 5 are electrically coupled and are driven in substantially the same manner as the first and second stages S 1 and S 2 described above, and thus detailed descriptions thereof will be omitted.

FIG. 3 is a circuit diagram of the scan driver 110 shown in FIG. 2 , according to an embodiment of the present invention. Each scan driver circuit described below refers to a scan driver circuit of each of the stages shown in FIG. 2 . In other words, scan driver circuits included in the first through fifth stages S 1 through S 5 according to one embodiment are each substantially equivalent to the scan driver circuit shown in FIG. 3 . Here, descriptions will be given with respect to the first stage S 1 .

Referring to FIG. 3 , the first stage S 1 includes first through ninth switching devices T 1 through T 9 and first through third capacitors C 1 through C 3 . In one embodiment, the first through ninth switching devices T 1 through T 9 may be p-type metal-oxide-semiconductor (PMOS) field effect transistors.

A control electrode (e.g., a gate electrode) of the first switching device T 1 is electrically coupled to the input terminal IN of the first stage S 1 , a first electrode corresponding to a drain electrode or a source electrode of the first switching device T 1 is electrically coupled to a first power voltage line VGH, and a second electrode (e.g., a source electrode or a drain electrode) of the first switching device T 1 is electrically coupled to a first node N 1 , which is electrically coupled to a control electrode of the third switching device T 3 , a control electrode of the fourth switching device T 4 , a control electrode of the sixth switching device T 6 , and a control electrode of the eighth switching device T 8 .

When a low-level input signal is applied to the control electrode of the first switching device T 1 , the first switching device T 1 is turned on and applies a first power voltage VGH to the control electrode of the third switching device T 3 , the control electrode of the fourth switching device T 4 , the control electrode of the sixth switching device T 6 , and the control electrode of the eighth switching device T 8 .

A control electrode of the second switching device T 2 is electrically coupled to the input terminal IN of the first stage S 1 , a first electrode of the second switching device T 2 is electrically coupled to a second node N 2 , which is electrically coupled to a control electrode of the seventh switching device T 7 , and a second electrode of the second switching device T 2 is electrically coupled to a second power voltage line VGL. When a low-level input signal is applied to the control electrode of the second switching device T 2 , the second switching device T 2 is turned on and applies a second power voltage VGL to the control electrode of the seventh switching device T 7 .

The control electrode of the third switching device T 3 is electrically coupled to the first node N 1 , which is electrically coupled to the second electrode of the first switching device T 1 . A first electrode of the third switching device T 3 is electrically coupled to the first power voltage line VGH, and a second electrode of the third switching device T 3 is electrically coupled to a first electrode of the fourth switching device T 4 .

A control electrode of the fourth switching device T 4 is electrically coupled to the first node N 1 , which is electrically coupled to the second electrode of the first switching device T 1 . The first electrode of the fourth switching device T 4 is electrically coupled to the second electrode of the third switching device T 3 , and a second electrode of the fourth switching device T 4 is electrically coupled to the second node N 2 . The second node N 2 is electrically coupled to the first electrode of the second switching device T 2 , the control electrode of the seventh switching device T 7 , and a control electrode of the ninth switching device T 9 . The third switching device T 3 and the fourth switching device T 4 may be formed as a single switching device in another embodiment.

A control electrode of the fifth switching device T 5 is electrically coupled to the flmup terminal FLMUP of the first stage S 1 , a first electrode of the fifth switching device T 5 is electrically coupled to the first node N 1 , and a second electrode of the fifth switching device T 5 is electrically coupled to the second power voltage line VGL. The first node N 1 is electrically coupled to the control electrode of the third switching device T 3 , the control electrode of the fourth switching device T 4 , the control electrode of the sixth switching device T 6 , and the control electrode of the eighth switching device T 8 .

When a low-level signal is applied to the flmup terminal FLMUP of the first stage S 1 , which is electrically coupled to the control electrode of the fifth switching device T 5 , the fifth switching device T 5 is turned on and applies a second power voltage VGL to the first node N 1 . When the second power voltage VGL is applied to the control electrode of the third switching device T 3 and the control electrode of the fourth switching device T 4 , the third switching device T 3 and the fourth switching device T 4 are turned on and apply a first power voltage VGH to the second node N 2 .

The control electrode of the sixth switching device T 6 is electrically coupled to the first node N 1 , a first electrode of the sixth switching device T 6 is electrically coupled to the first power voltage line VGH, and a second electrode of the sixth switching device T 6 is electrically coupled to a third node N 3 , which is electrically coupled to a first electrode of the seventh switching device 17 . When a low-level signal is applied to the first node N 1 , the sixth switching device T 6 is turned on and applies a first power voltage VGH to the third node N 3 .

The control electrode of the seventh switching device T 7 is electrically coupled to the second node N 2 , the first electrode of the seventh switching device 17 is electrically coupled to the third node N 3 , which is electrically coupled to the next terminal NEXT of the first stage S 1 , and a second electrode of the seventh switching device T 7 is electrically coupled to the clock terminal CLK of the first stage S 1 . When a low-level signal is applied to the second node N 2 , the seventh switching device 17 is turned on.

The control electrode of the eighth switching device T 8 is electrically coupled to the first node N 1 , a first electrode of the eighth switching device T 8 is electrically coupled to the first power voltage line VGH, and a second electrode of the eighth switching device T 8 is electrically coupled to the output terminal OUT of the first stage S 1 . When a low-level signal is applied to the first node N 1 , the eighth switching device T 8 is turned on and outputs a first power voltage VGH to the output terminal OUT of the first stage S 1 .

The control electrode of the ninth switching device T 9 is electrically coupled to the second node N 2 , a first electrode of the ninth switching device T 9 is electrically coupled to the output terminal OUT of the first stage S 1 , and a second electrode of the ninth switching device T 9 is electrically coupled to the second power voltage line VGL. When a low-level signal is applied to the second node N 2 , the ninth switching device T 9 is turned on and outputs a second power voltage VGL to the output terminal OUT of the first stage S 1 .

The first capacitor C 1 is coupled between the first power voltage line VGH and the first node N 1 . The first capacitor C 1 stores a voltage difference between the control electrode of the sixth switching device T 6 and the first electrode of the sixth switching device T 6 .

The second capacitor C 2 is coupled between the control electrode of the seventh switching device T 7 and the first electrode of the seventh switching device T 7 . The second capacitor C 2 stores a voltage difference between the control electrode of the seventh switching device T 7 and the first electrode of the seventh switching device T 7 .

The third capacitor C 3 is coupled between the control electrode of the ninth switching device T 9 and the output terminal OUT of the first stage S 1 . The third capacitor C 3 stores a voltage difference between the control electrode of the ninth switching device T 9 and the first electrode of the ninth switching device T 9 .

FIG. 4 is a timing diagram illustrating an example of an operation of the scan driver circuit shown in FIG. 3 .

FIGS. 5 and 6 are circuit diagrams illustrating an example of an operation of the scan driver circuit shown in FIG. 3 .

Referring to FIG. 4 , the timing diagram of the scan driver circuit includes a first operation period P 1 , a second operation period P 2 , a third operation period P 3 , and a fourth operation period P 4 .

The first operation period P 1 is related to the first stage S 1 . During the first operation period P 1 , a low-level initial input signal is applied to the input terminal IN of the first stage S 1 via the initial input line SP, and a high-level first FLMUP signal (e.g., a high-level first control signal) is applied to the flmup terminal FLMUP of the first stage S 1 via the first FLMUP line FLMUP 1 . Referring to FIG. 5 , a low-level initial input signal is applied to the input terminal IN of the first stage S 1 , and thus the first switching device T 1 and the second switching device T 2 are turned on. As the first switching device T 1 is turned on, a first power voltage VGH is applied to the first node N 1 . Furthermore, as the second switching device T 2 is turned on, a second power voltage VGL is applied to the second node N 2 . When the second power voltage VGL is applied to the second node N 2 , the ninth switching device T 9 is turned on and outputs a second power voltage VGL to the output terminal OUT of the first stage S 1 . Furthermore, when a second power voltage VGL is applied to the second node N 2 , the seventh switching device T 7 is turned on. In detail, the second node N 2 is pre-charged as much as the second power voltage VGL and the threshold voltage Vth of the seventh switching device T 7 by the third capacitor C 3 , and thus the seventh switching device T 7 is turned on. Furthermore, since a high-level first FLMUP signal is applied to the control electrode of the fifth switching device T 5 via the first FLMUP line FLMUP 1 , the fifth switching device T 5 stays turned off.

The second operation period P 2 is related to the first stage S 1 and the second stage S 2 . First, the operation of the first stage S 1 will be described. Referring to FIG. 5 , during the second first operation period P 2 , a first clock signal is applied to the clock terminal CLK of the first stage S 1 via the first clock line CLK 1 . At this point, if a low-level first clock signal is applied to the second electrode of the seventh switching device T 7 of the first'stage S 1 , the voltage level of the third node N 3 begins to drop to the voltage level of a second power voltage VGL via the seventh switching device T 7 . At this point, a bootstrap occurs via the third capacitor C 3 , and thus the voltage level of the second node N 2 drops to a point significantly lower than the voltage level of the second power voltage VGL. As a result, the seventh switching device T 7 is completely turned on. Therefore, the voltage level of the third node N 3 completely drops to the voltage level of the second power voltage VGL according to the low-level first clock signal. Here, for example in one embodiment, the low-level first clock signal has a voltage that is substantially the same as the voltage of the second power voltage VGL. At this point, the second power voltage VGL of the third node N 3 is output to the next terminal NEXT of the first stage S 1 as a first next signal and is applied to the input terminal IN of the second stage S 2 . As described above, a successive shift registering is performed between stages adjacent to each other.

The operation of the second stage S 2 during the second operation period P 2 will be described below. A low-level first next signal is applied to the input terminal IN of the second stage S 2 , and thus the first switching device T 1 and the second switching device T 2 of the second stage S 2 are turned on. As the first switching device T 1 is turned on, a first power voltage VGH is applied to the first node N 1 . Furthermore, as the second switching device T 2 is turned on, a second power voltage VGL is applied to the second node N 2 . When the second power voltage VGL is applied to the second node N 2 , the ninth switching device T 9 is turned on and outputs a second power voltage VGL to the output terminal OUT of the second stage S 2 . Furthermore, when a second power voltage VGL is applied to the second node N 2 , the seventh switching device T 7 is turned on.

During the second operation period P 2 , since a high-level first FLMUP signal is applied to the flmup terminal FLMUP of the first stage S 1 , the fifth switching device T 5 of the first stage S 1 stays turned off. Furthermore, since a high-level second FLMUP signal (e.g., a high-level second control signal) is applied to the flmup terminal FLMUP of the second stage S 2 , the fifth switching device T 5 of the second stage S 2 stays turned off.

The third operation period P 3 is related to the first stage S 1 . During the third operation period P 3 , a high-level initial input signal is applied to the input terminal IN of the first stage S 1 via the initial input line SP, and a high-level first clock signal is applied to the clock terminal CLK of the first stage S 1 via the first clock line CLK 1 . Furthermore, a low-level first FLMUP signal (e.g., a low-level first control signal) is applied to the flmup terminal FLMUP of the first stage S 1 via the first FLMUP line FLMUP 1 . Referring to FIG. 6 , a high-level initial input signal is applied to the input terminal IN of the first stage S 1 , and thus the first switching device T 1 and the second switching device T 2 are turned off. However, since the low-level first FLMUP signal is applied to the control electrode of the fifth switching device T 5 , the fifth switching device T 5 is turned on. When the fifth switching device T 5 is turned on, a second power voltage VGL is applied to the first node N 1 , and thus the eighth switching device T 8 is turned on and outputs a first power voltage VGH to the output terminal OUT of the first stage S 1 .

The fourth operation period P 4 is related to the second stage S 2 . During the fourth operation period P 4 , a high-level first next signal is applied to the input terminal IN of the second stage S 2 , and a high-level second clock signal is applied to the clock terminal CLK of the second stage S 2 via the second clock line CLK 2 . Furthermore, a low-level second FLMUP signal (e.g., a low-level second control signal) is applied to the flmup terminal FLMUP of the second stage S 2 via the second FLMUP line FLMUP 2 . As the high-level first next signal is applied to the input terminal IN of the second stage S 2 , the first switching device T 1 and the second switching device T 2 are turned off. However, since the low-level second FLMUP signal is applied to the control electrode of the fifth switching device T 5 , the fifth switching device T 5 is turned on. When the fifth switching device T 5 is turned on, a second power voltage VGL is applied to the first node N 1 , and thus the eighth switching device T 8 is turned on and outputs a first power voltage VGH to the output terminal OUT of the second stage S 2 .

Referring to FIG. 4 , the first power voltage VGH output by an output terminal OUT is a high-level voltage, whereas the second power voltage VGL output by an output terminal OUT is a low-level voltage.

FIG. 7 is a diagram of a scan driver 111 according to another embodiment of the present invention. The scan driver 111 , for example, may replace the scan driver 110 of FIG. 1 in some embodiments. Each of stages shown in FIG. 7 contains the circuit configuration shown in FIG. 3 .

According to the embodiment illustrated in FIG. 7 , the scan driver 111 may further include a third FLMUP line FLMUP 3 (e.g., a third control line), compared to the scan driver 111 of FIG. 2 . Referring to FIG. 7 , the clock terminal CLK of the third stage S 3 is electrically coupled to the first clock line CLK 1 , and the flmup terminal FLMUP of the third stage S 3 is electrically coupled to the third FLMUP line FLMUP 3 . The clock terminal CLK of the fourth stage S 4 is electrically coupled to the second clock line CLK 2 , and the flmup terminal FLMUP of the fourth stage S 4 is electrically coupled to the first FLMUP line FLMUP 1 . The clock terminal CLK of the fifth stage S 5 is electrically coupled to the first clock line CLK 1 , and the flmup terminal FLMUP of the fifth stage S 5 is electrically coupled to the second FLMUP line FLMUP 2 .

FIG. 8 is a timing diagram illustrating an example of an operation of the scan driver 111 shown in FIG. 7 .

Referring to FIGS. 7 and 8 , a low-level first FLMUP signal is applied to the flmup terminal FLMUP of the first stage S 1 , a low-level second FLMUP signal is applied to the flmup terminal FLMUP of the second stage S 2 , and a low-level third FLMUP signal (e.g., a low-level third control signal) is applied to the flmup terminal FLMUP of the third stage S 3 .

Referring to FIG. 8 , in response to an initial input signal from the initial input line SP, the first stage S 1 outputs a first output signal to the first scan line Scan[ 1 ] via the output terminal OUT of the first stage S 1 , and outputs a first next signal to the second stage S 2 in response to a first clock signal from the first clock line CLK 1 .

The second stage S 2 outputs a second output signal to the second scan line Scan[ 2 ] via the output terminal OUT of the second stage S 2 in response to the first next signal, and outputs a second next signal to the third stage S 3 in response to a second clock signal from the second clock line CLK 2 .

The third stage S 3 outputs a third output signal to the third scan line Scan[ 3 ] via the output terminal OUT of the third stage S 3 in response to the second next signal.

While the second output signal is being output, the first output signal is not output in response to the first FLMUP signal from the first FLMUP line FLMUP 1 . Furthermore, while the third output signal is being output, the second output signal is not output in response to the second FLMUP signal from the second FLMUP line FLMUP 2 . Furthermore, the third output signal is not output in response to the third FLMUP signal from the third FLMUP line FLMUP 3 . Here, the first output signal and the second output signal overlap each other, and the second output signal and the third output signal also overlap each other.

FIG. 9 is a block diagram of a scan driver 112 according to another embodiment of the present invention. The scan driver 112 , for example, may replace the scan driver 110 of FIG. 1 in some embodiments. Each of stages shown in FIG. 9 contains the circuit configuration shown in FIG. 3 .

According to the embodiment of FIG. 9 , the scan driver 112 may further include a third clock line CLK 3 and a third FLMUP line FLMUP 3 , compared to the scan driver 110 of FIG. 2 . Referring to FIG. 9 , the clock terminal CLK of the third stage S 3 is electrically coupled to the third clock line CLK 3 , and the flmup terminal FLMUP of the third stage S 3 is electrically coupled to the third FLMUP line FLMUP 3 . The clock terminal CLK of the fourth stage S 4 is electrically coupled to the first clock line CLK 1 , and the flmup terminal FLMUP of the fourth stage S 4 is electrically coupled to the first FLMUP line FLMUP 1 . The clock terminal CLK of the fifth stage S 5 is electrically coupled to the second clock line CLK 2 , and the flmup terminal FLMUP of the fifth stage S 5 is electrically coupled to the second FLMUP line FLMUP 2 .

FIG. 10 is a timing diagram illustrating an example of an operation of the scan driver 112 shown in FIG. 9 .

Referring to FIG. 10 , a low-level first FLMUP signal is applied to the flmup terminal FLMUP of the first stage S 1 , a low-level second FLMUP signal is applied to the flmup terminal FLMUP of the second stage S 2 , and a low-level third FLMUP signal is applied to the flmup terminal FLMUP of the third stage S 3 . However, compared to the embodiment shown in FIG. 8 , a low-level third clock signal is input to the clock terminal CLK of the third stage S 3 in the embodiment of FIG. 10 .

As shown in FIGS. 8 and 10 , since low-level first through third FLMUP signals are sequentially output by the first through third FLMUP lines FLMUP 1 through FLMUP 3 , overlapping portions of output signals become longer as a number of FLMUP lines increases. In other words, according to the described embodiments of the present invention, the length of overlapping portions of scan signals output by each stage may be controlled by adjusting a number of FLMUP lines. Therefore, a scan driver circuit according to the described embodiments of the present invention features a more simplified configuration and a less number of signal lines, as compared to other scan driver circuits.

FIG. 11 is a circuit diagram of the respective scan drivers 110 , 111 and 112 of FIGS. 2 , 7 , and 9 , according to another embodiment of the present invention.

According to the embodiment of FIG. 11 , a tenth switching device T 10 is additionally coupled between the first node N 1 and the second power voltage line VGL, compared to the circuit diagram of the scan drivers 110 , 111 and 112 of FIG. 3 .

A first electrode of the tenth switching device T 10 is electrically coupled to the first node N 1 , a second electrode of the tenth switching device T 10 is electrically coupled to the second power voltage line VGL, and a control electrode of the tenth switching device T 10 is electrically coupled to a reset terminal ESR. When a low-level reset signal is applied to the reset terminal ESR, the tenth switching device T 10 is turned on and applies a second power voltage VGL to the first node N 1 . As the second power voltage VGL is applied to the first node N 1 , the eighth switching device T 8 is turned on and outputs a first power voltage VGH to the output terminal OUT of each stage. A reset signal is applied before a clock signal is applied. In other words, by a reset signal, a scan signal at a high level is output before a clock signal is applied.

According to embodiments of the present invention, embodiment of overlapped driving of scan signals output by each stage of a scan driver including the stages enables high-speed driving of a large display device.

Furthermore, according to embodiments of the present invention, a scan driver may be configured with a simple circuit.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents.