Analog digital converting device

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2010-0089624, filed on Sep. 13, 2010, the entire contents of which are hereby incorporated by reference.

The present invention disclosed herein relates to an analog digital converting device, and more particularly, to a successive approximation analog digital converter.

Recently, as the use of a mixed-mode system increases, the necessity of an analog digital converter (hereinafter referred to as ADC) is in a progressively increasing trend. Particularly, in systems such as Digital Video Disk Players (DVDPs) and Direct Broadcasting for Satellite Receivers (DBSRs), research is being actively conducted for one chip based on a Complementary Metal-Oxide Semiconductor (CMOS) process for the effective-cost. For this, an ADC design technology for directly processing a Radio Frequency (RF) signal is becoming an increasingly important issue.

Up to date, various types of ADCs have been proposed. Flash ADCs, pipeline ADCs and successive approximation ADCs are used in appropriate application fields in accordance with their characteristics. Generally, the flash ADCs have fast operation characteristic, but have a high power consumption rate. The successive approximation ADCs have a low power consumption rate and a simple circuit configuration, but have slow operation characteristic. Comparing with the flash ADCs and the successive approximation ADCs, the pipeline ADCs have the operation characteristic of an intermediate speed and an intermediate power consumption rate. Recently, research is being conducted on hybrid ADCs for supplementing the advantages and disadvantages of the above-described ADCs.

The present invention provides an analog digital converting device which consumes a low power and guarantees fast operation characteristic.

Embodiments of the present invention provide an analog digital converting device including: a sub-Analog Digital Converter (ADC) converting an external analog signal into a first digital signal by using first and second reference voltages; and a successive approximation ADC comprising a plurality of bit streams, and converting the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The analog digital converting device may further include a reference voltage generation circuit generating the first and second reference voltages.

In some embodiments, the successive approximation ADC may receive the first digital signal, and convert the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

In other embodiments, the bit streams may include bit streams respectively corresponding to M bits (where M is an integer) configuring the first digital signal, and bit streams respectively corresponding to N bits (where N is an integer) configuring the second digital signal. The successive approximation ADC may apply one of the first and second reference voltages to the bit streams respectively corresponding to the M bits based on the first digital signal.

In still other embodiments, the successive approximation ADC may include a comparator connected to bit streams respectively corresponding to the M bits.

In even other embodiments, each of the bit streams may include a passive capacitor.

The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings:

FIG. 1 is a block diagram illustrating an analog digital converting device according to an embodiment of the present invention;

FIG. 2 is an exemplary diagram showing that an analog voltage of FIG. 1 is converted into a K-bit digital signal;

FIG. 3 is a block diagram illustrating a flash ADC of FIG. 1 ;

FIG. 4 is a block diagram illustrating a successive approximation ADC of FIG. 1 ; and

FIG. 5 is a flowchart illustrating an operation in which the analog digital converting device of FIG. 1 converts an analog voltage into a 6-bit digital signal.

Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, a portion irrelevant to a description of the present invention will be omitted for clarity. Like reference numerals refer to like elements throughout.

In this disclosure below, when one part (or element, device, etc.) is referred to as being ‘connected’ to another part (or element, device, etc.), it should be understood that the former can be ‘directly connected’ to the latter, or ‘electrically connected’ to the latter via an intervening part (or element, device, etc.). Furthermore, when it is described that one comprises (or includes or has) some elements, it should be understood that it may comprise (or include or has) only those elements, or it may comprise (or include or have) other elements as well as those elements if there is no specific limitation.

FIG. 1 is a block diagram illustrating an analog digital converting device 100 according to an embodiment of the present invention.

Referring to FIG. 1 , an analog digital converting device 100 according to an embodiment of the present invention includes a flash ADC 110 , a successive approximation ADC 120 , a reference voltage generation circuit 130 , and a controller 140 .

The flash ADC 110 is electrically connected to the successive approximation ADC 120 , the reference voltage generation circuit 130 and the controller 140 . The flash ADC 110 serves as a sub-ADC. That is, the analog digital converting device 100 includes the flash ADC 110 in FIG. 1 , but may include another ADC instead of the flash ADC 110 . For example, the analog digital converting device 100 may include a pipeline ADC (not shown) instead of the flash ADC 110 .

The flash ADC 110 operates in response to a flash control signal FC received from the controller 140 . The flash ADC 110 receives an analog voltage VIN from the outside. The flash ADC 110 receives first and second reference voltages VREFP and VREFN from the reference voltage generation circuit 130 .

The flash ADC 110 converts the analog voltage VIN into a digital signal and generates a flash output signal FOUT by using the first and second reference voltages VREFP and VREFN. Exemplarily, the flash output signal FOUT may be an m-bit digital signal. The flash ADC 110 compares the analog voltage VIN with comparison voltages having different voltage levels to generate a digital signal at one time. This will be described below in detail with reference to FIG. 3 .

The successive approximation ADC 120 is electrically connected to the flash ADC 110 , the reference voltage generation circuit 130 and the controller 140 . The successive approximation ADC 120 operates in response to an input sampling control signal ISC and a successive approximation control signal SC that are received from the controller 140 . The successive approximation ADC 120 includes a plurality of bit streams. Herein, each of the bit streams includes a passive capacitor.

The successive approximation ADC 120 converts the external analog voltage VIN into a digital signal. The successive approximation ADC 120 receives the flash output signal FOUT from the flash ADC 110 . The successive approximation ADC 120 converts the external analog voltage VIN into a digital signal on the basis of the flash output signal FOUT. For example, the successive approximation ADC 120 converts the received analog voltage VIN into an N-bit digital signal. At this point, the first and second reference voltages VREFP and VREFN may be used.

The successive approximation ADC 120 generates a digital output signal DOUT. The digital output signal DOUT may include the digital signal that has been converted in the successive approximation ADC 120 and the flash output signal FOUT. Exemplarily, the digital output signal DOUT may include the M-bit digital signal that has been determined in the flash ADC 110 , and the N-bit digital signal that has been determined in the successive approximation ADC 120 .

The reference voltage generation circuit 130 is electrically connected to the flash ADC 110 and the successive approximation ADC 120 . The reference voltage generation circuit 130 provides the first and second reference voltages VREFP and VREFN to the flash ADC 110 and the successive approximation ADC 120 . Furthermore, the reference voltage generation circuit 130 provides a common voltage VCM to the successive approximation ADC 120 .

Although not shown, the reference voltage generation circuit 130 may receive a power source voltage (not shown) from the outside, and generate the first and second reference voltages VREFP and VREFN by using the received power source voltage.

The controller 140 is electrically connected to the flash ADC 110 and the successive approximation ADC 120 . The controller 140 controls the overall operation of the analog digital converting device 100 . The controller 140 receives a clock signal CLK from the outside. The controller 140 generates the flash control signal FC, the input sampling control signal ISC and the successive approximation control signal SC by using the received clock signal CLK.

According to an embodiment of the present invention, when the analog digital converting device 100 converts the analog voltage VIN into a K-bit digital signal, the flash ADC 110 determines the values of upper M bits from among the K bits. Furthermore, base on the upper M bits determined by the flash ADC 110 , the successive approximation ADC 120 determines the values of lower N bits from among the K bits.

FIG. 2 shows that the analog voltage VIN of FIG. 1 is converted into the K-bit digital signal.

Referring to FIGS. 1 and 2 , the level of the analog voltage VIN corresponds to the K-bit digital signal with respect to the first and second reference voltages VREFP and VREFN. The K bits are configured with the upper M bits and the lower N bits. The upper M bits are determined in the flash ADC 110 . The lower N bits are determined in the successive approximation ADC 120 .

FIG. 3 is a block diagram illustrating the flash ADC 110 of FIG. 1 . In FIG. 3 , for convenience, the flash ADC 110 that converts the analog voltage VIN into a 3-bit digital signal is illustrated.

Referring to FIG. 3 , the flash ADC 110 includes a comparison voltage generator 111 , an amplifier 112 , and an encoder 113 . The comparison voltage generator 111 includes first to eighth resistors R 1 to R 8 . The comparison voltage generator 111 generates first to seventh comparison voltages VC 1 to VC 7 by using the first and second reference voltages VREFP and VREFN provided from the reference voltage generation circuit 130 . The first to seventh comparison voltages VC 1 to VC 7 are provided to the amplifier 112 .

The amplifier 112 includes first to seventh comparators CPR 1 to CPR 7 . The first to seventh comparators CPR 1 to CPR 7 receive the first to seventh comparison voltages VC 1 to VC 7 , respectively. The first to seventh comparators CPR 1 to CPR 7 receive the analog voltage VIN. Each of the first to seventh comparators CPR 1 to CPR 7 amplifies a difference between the analog voltage VIN and the level of a comparison voltage received to it, and outputs the amplified signal. That is, the first to seventh comparators CPR 1 to CPR 7 outputs first to seventh amplification signals Vamp 1 to Vamp 7 .

The encoder 113 is electrically connected to the amplifier 112 . The encoder 113 receives the first to seventh amplification signals Vamp 1 to Vamp 7 . The encoder 113 generates the flash output signal FOUT configured with upper 3 bits, based on the first to seventh amplification signals Vamp 1 to Vamp 7 . The zeroth to second bits D 0 to D 2 of FIG. 3 correspond to the upper 3 bits.

FIG. 4 is a block diagram illustrating the successive approximation ADC 120 of FIG. 1 . For convenience, FIG. 4 illustrates the successive approximation ADC 120 that determines lower 4 bits D 3 to D 6 on the basis of the upper 3 bits D 0 to D 2 of the flash output signal FOUT.

Referring to FIG. 4 , the successive approximation ADC 1120 includes first and second conversion arrays 210 and 220 , a logic unit 240 , and a comparator 230 . The first conversion array 210 includes a plurality of capacitors C 0 to C 6 , zeroth to sixth switches S 0 to S 6 , and a sampling switch SS. Zeroth to fifth capacitors C 0 to C 5 correspond to zeroth to fifth bits, respectively. From the fifth capacitor C 5 to the zeroth capacitor C 0 , a capacitance sequentially increases by the exponent of 2. For example, as illustrated in FIG. 4 , when the capacitance of the fifth capacitor C 5 is C, the capacitances of the fourth to zeroth capacitors C 4 to C 0 may be 2 C, 4 C, 8 C, 16 C and 32 C, respectively.

Zeroth to sixth capacitors C 0 to C 6 are connected to the comparator 230 . The zeroth to sixth capacitors C 0 to C 6 are connected to the zeroth to sixth switches S 0 to S 6 , respectively. The zeroth to sixth switches S 0 to S 6 operates in response to zeroth to sixth bit control signals BC 0 to BC 6 , respectively. The first and second reference voltages VREFP and VREFN and the analog voltage VIN may be selectively applied to the zeroth to sixth capacitors C 0 to C 6 , according to the operations of the zeroth to sixth switches S 0 to S 6 .

Each bit stream comprises each switch and each capacitor. In other words, zeroth to sixth bit streams 211 to 217 include the zeroth to sixth capacitors C 0 to C 6 respectively. Furthermore, the zeroth to sixth bit streams 211 to 217 include the zeroth to sixth switches S 0 to S 6 respectively.

The sampling switch SS applies the common voltage VCM to a terminal (a) in response to the input sampling control signal ISC. Exemplarily, the common voltage VCM corresponds to a value that is obtained by dividing the sum of the first and second reference voltages VREFP and VREFN by 2. When an input sampling operation is performed, the sampling switch SS applies the common voltage VCM to the terminal (a). When the input sampling operation is performed, the common voltage VCM is applied to the one side of each of the zeroth to sixth capacitors C 0 to C 6 , and the analog voltage VIN is applied to the other side of each of the zeroth to sixth capacitors C 0 to C 6 . As a result, as the input sampling operation is performed, the analog voltage VIN is stored in each of the zeroth to sixth capacitors C 0 to C 6 .

The second conversion array 220 has the same configuration as that of the first conversion array 210 . However, the analog voltage VIN is inverted and inputted to the second conversion array 220 . When some of the zeroth to sixth capacitors C 0 to C 6 are connected to the first reference voltage VREFP, the second reference voltage VREFN is applied to the corresponding capacitors of the second conversion array 220 . Likewise, when some of the zeroth to sixth capacitors C 0 to C 6 are connected to the second reference voltage VREFN, the first reference voltage VREFP is applied to the corresponding capacitors of the second conversion array 220 . That is, the successive approximation ADC 120 of FIG. 4 operates in a differential mode. However, the successive approximation ADC 120 according to an embodiment of the present invention may operate in a single mode.

The comparator 230 is connected to the first and second conversion arrays 210 and 220 . The comparator 230 outputs a comparison signal Vc that is generated by amplifying a level difference between voltages inputted from the first and second conversion arrays 210 and 220 .

The logic unit 240 receives the flash output signal FOUT, the successive approximation control signal SC and the comparison signal Vc. When the flash output signal FOUT is inputted, the logic unit 240 transmits zetoth to second bit control signals BC 0 to BC 2 to the first conversion array 210 . The zeroth to second bit control signals BC 0 to BC 2 are determined based on the zeroth to second bits D 0 to D 2 . In response to the zetoth to second bit control signals BC 0 to BC 2 , the zeroth to second switches S 0 to S 2 selectively apply the first and second reference voltages VREFP and VREFN to the zeroth to second capacitors C 0 to C 2 .

When the successive approximation control signal SC is received, the logic unit 240 transmits third to sixth bit control signals BC 3 to BC 6 to the first conversion array 210 . The third to sixth switches S 3 to S 6 performs a successive approximation operation while selectively applying the first and second reference voltages VREFP and VREFN to the third to sixth capacitors C 3 to C 6 .

While the successive approximation operation is being performed, the logic unit 240 determines lower 4 bits D 3 to D 6 on the basis of the comparison signal Vc. The third to sixth bits D 3 to D 6 of FIG. 4 correspond to the lower 4 bits, respectively. The logic unit 240 generates the third to sixth bit control signals BC 3 to BC 6 , based on the third to sixth bits D 3 to D 6 . This will be described below in more detail with reference to FIG. 5 .

The logic unit 240 generates the digital output signal DOUT according to the upper 3 bits D 0 to D 2 and the lower 4 bits D 3 to D 6 . At this point, the digital output signal DOUT may be configured with the zeroth to sixth bits D 0 to D 6 .

Unlike in FIG. 4 , the digital output signal DOUT may be configured with bits less than the 7 bits D 0 to D 6 . Exemplarily, the logic unit 240 may include a digital correction logic (not shown). The digital correction logic corrects the digital errors of the received zeroth to sixth bits D 0 to D 6 . The digital correction logic corrects a digital error and generates the digital output signal DOUT. That is, an error may be included in the zeroth to sixth bits D 0 to D 6 , and the digital correction logic generates the digital output signal DOUT from which an error has been removed.

Exemplarily, the digital correction logic includes a memory (not shown) storing a correction value, and corrects the digital errors of the zeroth to sixth bits D 0 to D 6 on the basis of the stored correction value. Also, the digital correction logic may correct the digital errors of the zeroth to sixth bits D 0 to D 6 , and generate the digital output signal DOUT configured with 5 bits.

In FIG. 4 , it is illustrated that each of the first and second conversion arrays includes a plurality of capacitors. However, this is merely an example, and each of the first and second conversion arrays may be configured with other impedance devices. Furthermore, for convenience, a converter using a binary capacitor array is illustrated in FIG. 4 , but even a converter using a split capacitor and a resistor and a converter using a unit capacitor array may be implemented in the same scheme.

FIG. 5 is a flowchart illustrating an operation in which the analog digital converting device 100 of FIG. 1 converts the analog voltage VIN into a 6-bit digital signal.

Referring to FIGS. 1 , 3 and 4 , in operation S 110 , the successive approximation ADC 120 performs the input sampling operation. The controller 140 transmits the input sampling control signal ISC to the successive approximation ADC 120 . In response to the input sampling control signal ISC, the sampling switch SS (see FIG. 4 ) applies the common voltage VCM to the terminal (a). Furthermore, the zeroth to sixth switches S 0 to S 6 apply the analog voltage VIN to the zeroth to sixth capacitors C 0 to C 6 , respectively. As a result, as the input sampling operation is performed, the analog voltage VIN is stored in the zeroth to sixth capacitors C 0 to C 6 . When the input sampling operation is ended, the sampling switch SS is opened.

In operation S 120 , the flash ADC 110 determines the zeroth to second bits D 0 to D 2 . As illustrated above with reference to FIG. 3 , the flash ADC 110 generates the first to seventh comparison voltages VC 1 to VC 7 by using the first and second reference voltages VREFP and VREFN. Furthermore, the flash ADC 110 receives the flash control signal FC. In response to the flash control signal FC, the flash ADC 110 compares the first to seventh comparison voltages VC 1 to VC 7 and the analog voltage VIN. The flash ADC 110 outputs the flash output signal FOUT that is a 3-bit digital signal, according to the compared result. The 3 bits may be configured with the zeroth to second bits D 0 to D 2 .

In operation S 130 , the successive approximation ADC 120 determines the third to sixth bits D 3 to D 6 . The successive approximation ADC 120 determines the third to sixth bits D 3 to D 6 , based on the zeroth to second bits D 0 to D 2 that have been converted in the flash ADC 110 . Operation S 130 includes operations S 131 and S 132 .

In operation S 131 , the first and second reference voltages VREFP and VREFN are selectively applied to the zeroth to second capacitors C 0 to C 2 respectively corresponding to the converted zeroth to second bits D 0 to D 2 . The logic unit 240 receives the flash output signal FOUT. The logic unit 240 generates the zeroth to second bit control signals BC 0 to BC 2 , based on the zeroth to second bits D 0 to D 2 . In response to the zeroth to second bit control signals BC 0 to BC 2 , the zeroth to second switches S 0 to S 2 select one of the first and second reference voltages VREFP and VREFN. As an example, when any one of the zeroth to second bits D 0 to D 2 corresponds to a logical value “1”, a corresponding switch selects the first reference voltage VREFP. As another example, when any one of the zeroth to second bits D 0 to D 2 corresponds to a logical value “0”, a corresponding switch selects the second reference voltage VREFN.

For example, it is assumed that the zeroth to second bits D 0 to D 2 that have been converted in the flash ADC 110 are logical values “1”, “0” and “1”, respectively. In this case, the first reference voltage VREFP is applied to the zeroth capacitor C 0 , the second reference voltage VREFN is applied to the first capacitor C 1 , and a third reference voltage VREFP is applied to the second capacitor C 2 .

In operation S 132 , the successive approximation ADC 120 determines the third to sixth bits D 3 to D 6 . That is, the successive approximation ADC 120 receives the successive approximation control signal SC. In response to the successive approximation control signal SC, the successive approximation ADC 120 determines the logical values of the third to sixth bits D 3 to D 6 . Logical values from the Most Significant Bit (MSB) to the Least Significant Bit (LSB) of the third to sixth bits D 3 to D 6 are sequentially determined through the successive approximation operation.

That is, the logical values of the third to fifth bits D 3 to D 5 are sequentially determined through the successive approximation operation. When the logical value of the third bit D 3 is determined, the first reference voltage VREFP is applied to the third capacitor C 3 . The second reference voltage VREFN is applied to capacitors corresponding to bits lower than the third bit D 3 . That is, the third switch S 3 selects the first reference voltage VREFP. The fourth and fifth switches S 4 and S 5 select the second reference voltage VREFN. The sixth switch S 6 is continuously connected to the second reference voltage VREFN during the successive approximation operation.

The comparator 230 generates the comparison signal Vc that is obtained by amplifying a level difference between voltages inputted from the first and second conversion arrays 210 and 220 . The voltage level of the terminal (a) is determined according to the voltage level of the one side of each of the zeroth to sixth capacitors C 0 to C 6 . For example, the voltage level of the terminal (a) may be determined according to the rate of the capacitances of capacitors receiving the first reference voltage VREFP to the capacitances of capacitors receiving the second reference voltage VREFN.

The logic unit 240 determines whether the third bit D 3 is a logical value “1” or “0”, based on the comparison signal Vc. When the third bit D 3 is the logical value “1”, the logic unit 240 generates the third bit control signal BC 3 in order for the third switch S 3 to maintain the selection of the first reference voltage VREFP. When the third bit D 3 is the logical value “0”, the logic unit 240 generates the third bit control signal BC 3 in order for the third switch S 3 to maintain the selection of the second reference voltage VREFN. At this point, the fourth and fifth switches S 4 and S 5 maintain the selection of the second reference voltage VREFN.

Like the third bit D 3 , the logical values of the fourth and fifth bits D 4 and D 5 are determined.

According to an embodiment of the present invention, the successive approximation ADC 120 controls a reference voltage applied to the zeroth to second capacitors C 0 to C 2 , based on the values of the upper M bits that have been determined in the flash ADC 110 . The successive approximation ADC 120 determines the values of the lower N bits. The flash ADC 110 and the successive approximation ADC 120 perform digital conversion, and thus the analog digital converting device consumes a low power and guarantees fast operation characteristic.

According to embodiments of the present invention, by performing analog-to-digital conversion with the successive approximation ADC and the flash ADC, the analog digital converting device consumes a low power and fast operation characteristic.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.