Display interface methods and systems

This application claims the benefit of U.S. Provisional Application No. 61/291,532 entitled “Method of Glue-less Interface to Digital or Analog VGA LCD Display” filed on Dec. 31, 2009, which is incorporated herein by reference in its entirety.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Various devices, ranging from computers to DVD players to scientific instrumentation, are configured to use a display. Furthermore, oftentimes a device needs to be able to support multiple types of displays. For example, in order to be competitive, a laptop computer typically needs to support its built-in screen as well as various digital and analog displays, such as a desktop CRT or LCD display, or a projection display. Other devices have similar requirements to be compatible with multiple different types of displays.

The large number of different displays available to consumers, however, often use incompatible standards. Digital interface standards and analog interface standards are so dissimilar that some manufacturers conventionally use separate controllers for separate interface standards. Other manufactures have resorted to using a single display controller with a host of electronic “glue” to make the single controller serve multiple displays. Such approaches tend to be costly and therefore undesirable in a highly-competitive market.

Aspects of the disclosure provide a System on a Chip (SoC) for driving a plurality of different types of video devices. In an embodiment, the SoC includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

Aspects of the disclosure also provide a method for driving a plurality of different types of video devices. In an embodiment, the method includes generating on a System on a Chip (SoC) digital video data, a first synchronization signal, and a second synchronization signal. The first synchronization and the second synchronization signals correspond to the digital video data. Further, the method includes delaying the first synchronization signal and the second synchronization signal relative to the digital video data to generate on the SoC a delayed first synchronization signal and a delayed second synchronization signal.

Aspects of the disclosure provide a system. The system includes a Liquid Crystal Display (LCD) panel, and integrated circuits for generating video signals for the LCD panel to display. The integrated circuits include a LCD controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. Further, the integrated circuits include a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal. The LCD panel can display any suitable video signal. In an example, the LCD panel is configured to display a Video Graphic Array (VGA) compliant video signal. In another example, the LCD panel is configured to display at least one of a Digital Visual Interface (DVI) signal and a High-Definition Multimedia Interface (HDMI) signal. The delay circuit suitably delays the first synchronization signal and the second synchronization signal according to the different video signals for the LCD panel to display.

Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

FIG. 1 depicts an example of an electronic system capable of being configured to drive both a digital and an optional analog display.

FIG. 2 is a flowchart outlining an example operation of the disclosed methods and systems for driving digital and analog displays.

The disclosed methods and systems below are described generally, as well as in terms of specific examples and/or specific embodiments. For instances where references are made to detailed examples and/or embodiments, it is noted that any of the underlying principles described are not to be limited to a single embodiment, but may be expanded for use with any of the other methods and systems described herein as will be understood by one of ordinary skill in the art unless otherwise stated specifically.

FIG. 1 depicts an example of an electronic system suitable for being configured to drive both a digital display and an optional analog display. As seen in FIG. 1 , the electronic system, which in the example is fabricated on a Printed Circuit Board (PCB) or some other suitable substrate, includes a System on a Chip (SoC) 110 , a digital video transmission circuit 120 and a Digital-to-Analog Converter (DAC) 130 . The SoC 110 seen in FIG. 1 includes an LCD controller circuit 112 , a digital delay circuit 114 , a first power rail circuit 116 and a second power rail circuit 118 . Note that FIG. 1 depicts one specific architecture. However, it is noted that other architectures may also be suitable.

In an example operation, the LCD controller circuit 112 generates a number of signals according to one of various digital video standards suitable for driving digital displays. Such suitable standards include, without limitation, the Digital Visual Interface (DVI) standard and the High-Definition Multimedia Interface (HDMI) standard. As seen in FIG. 1 , the generated signals include pixel data (on the pixel data bus), a pixel data valid signal, a pixel data clock signal, a first vertical synchronization (VSYNC) signal, and a first horizontal synchronization (HSYNC) signal. The pixel data, pixel data valid signal, and pixel data clock signal can be collectively referred to as “digital video data.”

In an embodiment, the LCD controller circuit 112 , which is coupled to the second power rail 118 as seen, outputs the digital video data, the VSYNC signal and the HSYNC signal. The digital video data, the VSYNC signal and the HSYNC signal are received by the second power rail 118 where they are suitably “conditioned” (i.e., buffered and amplified to appropriate voltage and current levels, and with appropriate impedances) to generate conditioned digital video data, VSYNC and HSYNC signals. In an embodiment, the resulting conditioned digital video data, VSYNC and HSYNC signals have functional voltage levels, relative timing, current levels, and output impedances that are compliant with the inputs of the digital video transmission circuit 120 . The digital video transmission circuit 120 is configured to receive the digital video signals VSYNC and HSYNC signals, and further condition them to be in compliance with an appropriate digital video standard, such as the DVI or HDMI standard, and then export the fully conditioned signals to an appropriate digital display. In an embodiment, the digital video transmission circuit 120 includes, for example, various suitable active or passive electrical/electronic components such as transformers, resistors, varistors, capacitors and the like.

Simultaneously, in an example, the DAC 130 receives the digital video data and converts the digital video data to analog form to derive analog video signals compliant with the Video Graphics Array (VGA) standard—or perhaps another known or later derived analog video standard.

Returning to the SoC 110 , in an embodiment, as the LCD controller circuit 112 generates the above-mentioned digital video signals, the digital delay circuit 114 receives a portion of the digital video signals including the VSYNC signal, the HSYNC signal and the pixel clock. Using the VSYNC signal, the HSYNC signal and the pixel clock the digital delay circuit 114 can generate a set of delayed VSYNC and HSYNC signals that have waveforms identical to the received VSYNC and HSYNC signals but delayed by some desired amount of time. In various embodiments, the digital delay circuit 114 can delay the VSYNC and HSYNC signals according to a given setting, such as a first delay control setting that generates a delayed VSYNC signal and a delayed HSYNC signal that are both suitably delayed relative to the analog video data of the DAC 130 so as to generate a Video Graphics Array (VGA) compliant video signal—or perhaps a video signal compliant with another analog video standard.

In various embodiments, the digital delay circuit 114 is configured to support a plurality of delay settings to enable the digital delay circuit 114 to generate delayed VSYNC and HSYNC signals to complement different types of DACs. For example, a “simple” DAC with no internal delays might use a first delay setting, while a more sophisticated DAC with an onboard queue might use a second delay setting, while a third DAC capable of providing delays for VSYNC and HSYNC signals may use a third delay setting.

It is noted that, in an example, as the delayed VSYNC and HSYNC signals are generated, the delayed VSYNC and HSYNC signals are received and conditioned by the first power rail circuit 116 to produce conditioned VSYNC and HSYNC signals that have functional voltage levels, functional current levels, and appropriate impedances that are compliant with a video signal, such as a VGA compliant signal. Accordingly, when the SoC 110 is used with the analog output of the DAC, a complete analog video signal is created.

It is noted that the arrangement of components 112 - 118 on the SoC 110 are strategically placed on the SoC, as opposed to being placed on a PCB, in order to minimize costs in view of the current demands of electronic systems and the trend of consumer needs to be less reliant on analog video standards. For example, placing a delay circuit and a plurality of power rail circuits on an SoC comes at a very small increase in chip resources while placing a DAC off an SoC reflects a negligible increase in cost, and possibly a decrease in cost as the DAC is less likely to be needed as analog systems are phased out over time.

FIG. 2 is a flowchart outlining an example operation of the disclosed methods and systems for driving digital and analog displays. While the below-described steps are described as occurring in a particular sequence for convenience, it is noted that the order of various steps may be changed from embodiment to embodiment. It is also noted that various disclosed steps may occur simultaneously or be made to occur in an overlapping fashion.

The process starts in step S 202 where an LCD controller circuit located on an SoC is configured to generate an appropriate set of digital video signals including pixel data, a pixel data valid signal, a pixel data clock signal, a first VSYNC signal, and a first HSYNC signal. Next, in step S 204 , a digital delay circuit located on the SoC is configured (based on a delay control signal) to receive the first VSYNC signal, the first HSYNC signal, and the pixel data clock to generate delayed VSYNC and HSYNC signals. Control continues to step S 206 .

In step S 206 , the digital video data and the VSYNC and HSYNC signals mentioned in step S 202 are generated by the LCD controller circuit while the delayed VSYNC and HSYNC signals mentioned in step S 204 are generated by the digital delay circuit. Next, in step S 208 , the delayed VSYNC and HSYNC signals are received, buffered and conditioned by a first power rail circuit on the SoC to generate conditioned VSYNC and HSYNC signals that electrically comply with the VGA or similar analog standard, while the digital video signals generated by the LCD controller circuit are received, buffered and conditioned by a second power rail circuit to generate conditioned video signals that electrically comply with the requirements of transmission circuitry for the DVI standard, the HMDI standard, or perhaps another digital video standard. Control continues to step S 210 .

In step S 210 , the digital video signals of the second power rail are sent to the appropriate digital video transmission circuit necessary to drive a digital display, as well as to a DAC so as to provide an analog video signal compliant with the VGA or another video standard. Next, in step S 212 , the digital video transmission circuit sends its output signals off-board to an appropriate digital display system. Control continues to step S 214 .

In step S 214 , the conditioned and delayed HSYNC and VSYNC signals generated in step S 208 are sent off-chip, i.e., off the SoC to the PCB containing the SoC. Next, in step S 216 , the conditioned and delayed HSYNC and VSYNC signals, along with the analog video signal of step S 210 , are sent off-board to an appropriate analog display. Control then jumps back to step S 206 whereby steps S 206 -S 216 may be repeated as desired.

The flowchart of FIG. 2 outlines a number of steps for the generation of both analog and digital video signals. However, the various steps of FIG. 2 are not necessarily conducted in the sequential order as suggested by the flowchart. While the flowchart of FIG. 2 is structured in a fashion representative of a single flow for simplicity of explanation, it is noted that this flowchart can be characterized as describing two separate flows—one for digital video signal and one for analog video signals—generally operating in parallel and capable of having some common operations. Accordingly, no particular limitation should be inferred by the suggested sequence of steps of FIG. 2 .

While the invention has been described in conjunction with the specific embodiments thereof that are proposed as examples, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the invention as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the scope of the invention.