Reception device and apparatus having the same

1. Field of the Invention

The present invention relates to transfer control of serial data, and to data transfer between apparatuses.

2. Description of the Related Art

Communication between devices employs serial transfer because the serial transfer allows a multi-bit data signal to be transferred by using a small number of signal lines and terminals which are interfaces between the devices. Japanese Patent Laid-Open No. 7-256883 discloses serial transfer in the communication between a recording device and a recording head. In this serial transfer, information that determines a driving period for the recording head and recording data are transferred.

However, in order to support a high-speed and complex driving control of the recording head, an increase in the amount of information used for controlling the recording head and an increase in the transfer speed are required. Meanwhile, reduction in size and cost of devices such as recording devices is also required.

A driving device includes a driving unit configured to supply a driving element with a pulse signal that determines a driving period to drive the driving element, an input unit configured to receive, in synchronization with a trigger signal, a data signal containing first information, second information, a first flag and a second flag that determine a waveform of the pulse signal, a first setting unit configured to set in the driving unit the first information that is input to the input unit, a retaining unit configured to read and retain the second information on the basis of the first flag, and a second setting unit configured to set in the driving unit the second information that is retained in the retaining unit on the basis of the second flag.

Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

FIGS. 1A and 1B are diagrams illustrating a circuit configuration of an apparatus.

FIG. 2 is a diagram illustrating data transfer.

FIG. 3 is a diagram illustrating processing of input data.

FIG. 4 is a diagram illustrating a circuit configuration of an apparatus.

FIG. 5 is a diagram illustrating a signal that drives a recording element.

FIG. 6 is a diagram illustrating data transfer.

FIG. 7 is a diagram illustrating processing of input data.

FIG. 8 is a diagram illustrating a circuit configuration of an apparatus.

FIG. 9 is a diagram illustrating a circuit configuration of an apparatus.

FIG. 10 is a diagram illustrating data transfer.

FIG. 11 is a diagram illustrating processing of input data.

FIG. 12 is a diagram illustrating the appearance of a device in which an embodiment is applied.

First Embodiment

FIGS. 1A and 1B are diagrams illustrating a circuit configuration of an apparatus that performs data transfer in a serial format. An apparatus 10 serially receives a data signal (DATA) by using a clock signal (CLK) and a trigger signal (Lat). The clock signal (CLK), the trigger signal (Lat) and the data signal (DATA) are input to the apparatus 10 by using a first signal line, a second signal line and a third signal line, respectively.

The apparatus 10 includes a reception circuit that receives signals from the outside and a driving circuit (DRV) 1 that drives a driving element by using received data. The reception circuit includes a control circuit 2 , a shift register 3 , a latch circuit (LT) 4 , a shift register 5 and a latch circuit 6 . The shift register 3 (first shift register) receives the data signal (DATA) on the basis of the clock signal (CLK). The data signal (DATA) is composed of information of 10 bits B 0 to B 9 . The latch circuit 4 (first latch circuit) latches, on the basis of the trigger signal (Lat), data of eight bits B 0 to B 7 input from the shift register 3 by using a signal line 101 . The data latched by the latch circuit (LT) 4 is output to the driving circuit (DRV) 1 . The shift register 5 (second shift register) receives data of bit B 8 input from the shift register 3 on the basis of a pulse signal output from the control circuit 2 . The shift register 5 retains (holds) data for four bits. The latch circuit 6 (second latch circuit) latches data of four bits input from the shift register 5 . The data latched by the latch circuit 6 is output to the driving circuit (DRV) 1 . The control circuit 2 (reception control circuit) controls operation of the shift register 5 and the latch circuit 6 . The control circuit 2 receives data of bit B 9 input from the shift register 3 upon the input of the trigger signal (Lat).

An apparatus 20 includes a control circuit 21 and a transmission control circuit 22 . The control circuit 21 includes a register 21 a that retains (holds) first information consisting of multiple bits (eight bits, for example) and a register 21 b that retains second information consisting of four bits, as shown in FIG. 1B . The control circuit 21 transmits the information retained in the register 21 a and the register 21 b to the transmission control circuit 22 . The transmission control circuit 22 transfers the data to the apparatus 10 in a manner shown in FIG. 2 . In other words, the configuration of FIG. 1A is a system having a transmission device (transmission apparatus) 20 and a reception device (reception apparatus) 10 .

In this embodiment, it may be sufficient to set the second information for the driving circuit of the apparatus 10 once every four times the setting of the first information is made. Therefore, the apparatus 20 transfers part of the second information when transferring the first information. Thus, the control is carried out in such a manner that the second information is transferred in several batches, and this allows the apparatus 20 to reduce the number of bits to be transferred in each serial transfer.

FIG. 2 is a diagram illustrating timings of the data signal (DATA), the clock signal (CLK) and the trigger signal (Lat). In the data signal (DATA), information of 10 bits BO to B 9 is transferred. The shift register 3 detects and receives a rising edge and a falling edge of the clock signal (CLK). A pulse P of the trigger signal (Lat) is transferred in a period T. The data signal (DATA) is composed of eight bits of the first information B 0 (D 0 ) to B 7 (D 7 ), one bit of the second information B 8 (Cx where x is 0, 1, 2 or 3), and one bit of third information B 9 (F). The first information and the second information are set for the driving circuit of the apparatus 10 . The third information is control information to be used in the control of the reception circuit. B 9 (F) is a flag. The flag value “1” indicates that the flag is set, and the flag value “0” indicates that the flag is reset.

Data transfer in the apparatus 10 will be explained with reference to FIGS. 1A , 1 B and 3 . Suppose the data signal (DATA) has been input to the shift register 3 before timing t 1 . When a pulse signal P of the timing t 1 is input, B 0 (D 0 ) to B 7 (D 7 ) of the data signal (DATA) are latched by the latch circuit 4 , and then output to the driving circuit (DRV) 1 .

When B 9 of the data signal (DATA), which has been input to the shift register 3 , is “1” (that is, when the flag is set), the control circuit 2 retains the logic level of a signal line 104 at a high level for a predetermined period upon the detection of a rising edge of the trigger signal (Lat). Then, the control circuit 2 sets the logic level of the signal line 104 to a low level. When the control circuit 2 performs these operations, a pulse signal P 1 (first pulse signal) is transferred to the shift register 5 . The shift register 5 receives data in the shift register 3 upon the detection of a rising edge of the pulse signal P 1 . Meanwhile, when B 9 of the data signal (DATA), which has been input to the shift register 3 , is “0” (that is, when the flag is reset), the control circuit 2 retains the logic level of a signal line 105 at a high level for a predetermined period upon the detection of a rising edge of the trigger signal (Lat). Then, the control circuit 2 sets the logic level of the signal line 105 to a low level. When the control circuit 2 performs these operations, a pulse signal P 2 is transferred to the latch circuit 6 .

Therefore, when the pulse P of the timing t 1 is input, the control circuit 2 receives B 9 having “1” and outputs the pulse P 1 at timing t 2 . The shift register 5 receives “C 0 ” from the shift register 3 via a signal line 102 in response to the pulse P 1 of the timing t 2 . The latch circuit 6 receives “C 0 ” from the shift register 5 via a signal line 107 in response to the pulse P 1 of the timing t 2 . Next, when the pulse P of the timing t 2 is input, the control circuit 2 receives B 9 having “1” and outputs the pulse P 1 at timing t 3 . The shift register 5 receives “C 1 ” from the shift register 3 via the signal line 102 in response to the pulse P 1 of the timing t 3 . The latch circuit 6 receives “C 1 ” from the shift register 5 via the signal line 107 in response to the pulse P 1 of the timing t 3 . The control circuit 2 afterward repeats the same operation until B 9 having “0” is received, and “C 2 ” and “C 3 ” are transferred to the shift register 5 in sequence. Then, when the pulse P of timing t 5 is input, the control circuit 2 receives B 9 having “0”, and outputs the pulse P 2 at timing t 6 . When the pulse signal P 2 (second pulse signal) is transferred to the latch circuit 6 , four-bit data is latched in the latch circuit 6 and output to the driving circuit (DRV) 1 .

As described above, data which has been input four separate times in a unit of nine bits (D 0 to D 7 , Cx) from the apparatus 20 can be processed in a period from the timing t 1 to t 7 . The shaded portions of B 8 and B 9 indicate the data transition period. “X” of B 8 and B 9 is a value that is not related to control.

When the above circuit configuration is expressed differently, an input unit such as the shift register 3 receives serial data, and a setting unit such as the latch circuit 4 sets part of information (D 0 to D 7 ) in the driving circuit 1 . Meanwhile, when the value of the flag (B 9 in FIG. 2 ) is “1”, a data retaining unit such as the shift register 5 retains information (Cx where x=0 to 3). When the value of the flag is “0”, a setting unit such as the latch circuit 6 performs setting in the driving circuit (DRV) 1 .

Second Embodiment

FIG. 4 is a diagram illustrating the apparatus 10 in a second embodiment. In the second embodiment, the apparatus 10 is a recording head and the apparatus 20 is a recording device. In FIG. 4A , a shift register (SR) 401 corresponds to the shift register (SR) 3 of FIG. 1 . A latch circuit (LT) 403 corresponds to the latch circuit (LT) 4 of FIG. 1 . A shift register (SR) 402 A and a shift register (SR) 402 B correspond to the shift register (SR) 5 of FIG. 1 . A latch circuit (LT) 405 A and a latch circuit (LT) 405 B correspond to the control circuit 2 of FIG. 1 . A signal generation circuit 406 and a driving circuit 407 correspond to the driving circuit (DRV) 1 of FIG. 1 .

The shift register 401 receives a data signal (DATA) at timings of both edges of a clock signal (CLK).

The latch circuit 403 retains data output from the shift register 401 upon the input of a trigger signal (Lat). The latch circuit 403 outputs, to the driving circuit 407 , 128 bits (D 0 to D 127 ) of data among the data input from the shift register 401 , and outputs, to the signal generation circuit 406 , 18 bits (PT 1 D 0 to PT 1 D 8 and PT 2 D 0 to PT 2 D 8 ) of data among the data input from the shift register 401 . The latch circuit 405 A generates a signal 104 S on the basis of the value of PTCLK retained in the shift register 401 . The latch circuit 405 B generates a signal 105 S on the basis of the value of PTLT retained in the shift register 401 . The shift register 402 A receives PT 0 Dx retained in the shift register 401 on the basis of the signal 104 S. The shift register 402 B receives PT 3 Dx retained in the shift register 401 on the basis of the signal 104 S. A latch circuit 404 A latches data of shift register 402 A on the basis of the input (rising) of the signal 105 S. Also, a latch circuit 404 B latches data of shift register 402 B on the basis of the input (rising) of the signal 105 S. The latch circuit 404 A and the latch circuit 404 B output latched data to the signal generation circuit 406 .

FIG. 5 is a diagram illustrating an HE signal that the signal generation circuit 406 generates. The value of each of PT 0 (PT 0 D 0 to PT 0 D 8 ), PT 1 (PT 1 D 0 to PT 1 D 8 ), PT 2 (PT 2 D 0 to PT 2 D 8 ), and PT 3 (PT 3 D 0 to PT 3 D 8 ) is information of the clock signal (CLK). PT 0 , PT 1 , PT 2 , and PT 3 are parameters to determine pulse width of the HE signal or timing of the HE signal. In this case, the information is the number of edges in the clock signal (CLK). For example, the value expressed by PT 3 D 0 to PT 3 D 8 is seven and the value expressed by PT 2 D 0 to PT 2 D 8 is 12 . With the information, a prepulse 103 P is generated from the 7th edge timing to the 12th edge timing. Similarly, the value of PT 1 D 0 to PT 1 D 8 is 23 and the value of PT 0 D 0 to PT 0 D 8 is 255 . With the information, a main pulse 104 P is generated from the 23rd edge timing to the 255th edge timing. Driving the recording element on the basis of such HE signals causes ink to be ejected.

FIG. 6 is a diagram illustrating information contained in the data signal (DATA). The data signal (DATA) contains a total of 150 bits of data including 128 bits of image data, 20 bits of data composed of PT 0 Dx, PT 1 D 0 to PT 1 D 8 , PT 2 D 0 to PT 2 D 8 and PT 3 Dx, and two bits of data composed of PTCLK and PTLT.

FIG. 7 is a diagram illustrating the processing inside the recording head. The data transfer process is the same as that of the first embodiment. For simplicity, the explanations for the clock signal (CLK) and image data contained in the data signal (DATA) are omitted. First, processing of PT 0 D 0 to PT 0 D 8 and PT 3 D 0 to PT 3 D 8 will be explained. As described in the first embodiment, data of PT 0 D 0 to PT 0 D 8 and data of PT 3 D 0 to PT 3 D 8 are received on a bit-by-bit basis. When the value of PTCLK contained in the data signal (DATA) is “1”, the latch circuit 405 A outputs a pulse signal P 1 to the signal line 104 on the basis of the trigger signal (Lat) that has been input at timing t 10 . The shift register 402 A receives PT 0 D 0 (signal 305 ) on the basis of the pulse signal P 1 . Similarly, the shift register 402 B receives PT 3 D 0 (signal 306 ). Next, since the value of PTCLK contained in the data signal (DATA) received during a period from timing t 10 to timing t 11 is “ 1 ”, similarly on the basis of the pulse signal P 1 , the shift register 402 A receives PT 0 D 1 and the shift register 402 B receives PT 3 D 1 . Finally, the shift register 402 A receives PT 0 D 8 and the shift register 402 B receives PT 3 D 8 during a period from timing t 18 to timing t 19 .

Then, since the value of PTLT contained in the data received during a period from the timing t 18 to the timing t 19 is “1”, which is a first value, the latch circuit 405 B outputs a pulse signal P 2 to the signal line 105 . If the value of PTLT is “0”, which is a second value, the latch circuit 405 B does not output a pulse signal P 2 to the signal line 105 . On the basis of the pulse signal P 2 , the latch circuit 404 A outputs PT 0 D 0 to PT 0 D 8 to the signal generation circuit 406 via a signal line 106 A. The latch circuit 404 B outputs PT 3 D 0 to PT 3 D 8 to the signal generation circuit 406 via a signal line 106 B. With these operations, timing of PTO and timing of PT 3 of the HE signal after t 19 are set. The timing for the next setting occurs when a signal in which the value of PTLT is “1” is received.

Next, processing of PT 1 (PMT 1 D 0 to PT 1 D 8 ) and PT 2 (PT 2 D 0 to PT 2 D 8 ) will be explained. For convenience of illustration, explanation of an example of a data signal (DATA) received during a period t 19 to t 20 will be given. Data of PT 1 and PT 2 contained in the data signal (DATA) is output to the signal generation circuit 406 via a signal line 101 B by the latch circuit 403 when a trigger signal (Lat) of the timing t 20 is input. As described above, whenever a trigger signal (Lat) is input, setting of the signal generation circuit 406 is performed.

When the above circuit configuration is expressed differently, an input unit such as the shift register 401 receives serial data, and a setting unit such as the latch circuit 403 sets part of information (D 0 to D 127 ) in the driving circuit 407 . Meanwhile, when the value of the flag (PTCLK in FIG. 6 ) is “1”, data retaining units such as the shift registers 402 A and 402 B retain information (PT 0 Dx and PT 3 Dx where x=0 to 3). When the value of the flag (PTLT in FIG. 6 ) is “1”, setting units such as the latch circuits 404 A and 404 B perform setting in the signal generation circuit 406 .

Third Embodiment

FIG. 8 is a diagram illustrating the apparatus 10 (recording head) in a third embodiment. The recording head 10 includes, for example, four sensors 8 a, 8 b, 8 c and 8 d. These sensors are temperature sensors. A sensor control circuit 7 selects a sensor from which information is obtained on the basis of the value contained in a data signal, and outputs the information about the sensor.

The apparatus 20 transfers four bits (C 0 , C 1 , C 2 and C 3 ) of data on a bit-by-bit basis in order to select any one of the sensors. This data processing method is the same as that shown in FIG. 3 .

FIG. 9 is an example of the circuit configuration of FIG. 8 . The sensor control circuit 7 includes a decoder circuit 605 and a multiplexer 609 . The multiplexer 609 is composed of 32 analog switches 608 , and thus up to 32 sensors can be selected. An analog signal such as substrate temperature or voltage output from each sensor is output to a control unit of the recording device via the multiplexer 609 . The decoder circuit 605 receives a signal from a latch circuit (LT) 604 to control the multiplexer 609 .

FIG. 10 is a diagram illustrating data transfer. Three bits of multiplexer output selection data are transferred along with 128 bits of image data. FIG. 11 is a diagram illustrating the data transfer of FIG. 10 and the processing thereof.

In FIG. 11 , since MPCLK contained in data received during a period from timing t 31 to timing t 32 is “1”, a pulse signal P 1 is input as a clock signal to a shift register 602 . Consequently, MPD 0 is transferred during a period from timing t 32 to timing t 33 and input to the shift register 602 shown in FIG. 9 . Afterward MPD 1 , MPD 2 and MPD 3 are input in sequence to the shift register 602 . Then, during a period from timing t 36 to timing t 37 , data in which MPLT is “1” is received, and thus the latch circuit (LT) 405 A outputs a pulse P 2 to the signal line 105 . With this operation, the data from MPD 0 to MPD 3 are output to a signal line 106 in parallel from the latch circuit (LT) 604 . As described above, on the basis of the data (MPDx) transferred in four transfer sequences, the decoder circuit 605 outputs a selection signal.

Explanations of Apparatuses

The embodiments applied in the data transfer in a serial format were explained above. FIG. 12 is a diagram illustrating a line head (recording head) H as an example of the apparatus 10 described above. Multiple recording element substrates 1101 are arranged on the line head H. The numeral 1102 indicates a head substrate which is a wiring substrate having an electrical wiring structure such as that of a flexible printed circuit (FPC), a printed circuit board (PCB) or ceramic wiring. The recording element substrates 1101 are electrically connected to the head substrate 1102 by wire bonding or the like. For example, the circuits shown in FIG. 1 are arranged on the recording element substrates 1101 . A connection electrode 1104 includes terminals by which the data signal (DATA), the trigger signal (Lat) and the clock signal (CLK) shown in FIG. 1 are input.

The apparatus 20 includes a conveying unit that conveys a recording medium. The apparatus 20 is a recording device including a feeding unit that feeds the recording medium to the conveying unit, a discharging unit that discharges the recording medium on which recording has been performed, and the like.

Other Embodiments

While the data transfer in a serial format has been described, the driving elements described above are not limited to a recording element but may be a light emitting device that is used in a display device, a line sensor that is applied in a reading device, a DC motor, a stepping motor, or the like. Therefore, the driving circuit is not limited to a circuit that drives a recording element but may be a circuit that drives a light emitting device that is used in a display device, a line sensor that is applied in a reading device, a DC motor, a stepping motor, or the like. Meanwhile, the HE signal shown in FIG. 5 is used to determine the period in which the recording element is driven, but may be applied to the control of the period in which the light emitting device is driven or the control of the period in which a coil of the motor is excited. In addition, the HE signal shown in FIG. 5 is composed of a prepulse and a main pulse, but may be composed of three or more pulses.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No. 2010-108790 filed May 10, 2010, which is hereby incorporated by reference herein in its entirety.