Pixel and organic light emitting display device using the same

This application claims priority to and the benefit of Korean Patent Application No. 10-2009-0122490, filed on Dec. 10, 2009, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

1. Field

Embodiments relate to a pixel and an organic light emitting display device, and more specifically, to a pixel that is useful for implementing high resolution and high frequencies, and an organic light emitting display device using the pixel.

2. Description of the Related Technology

Various flat panel display devices that have advantages over cathode ray tubes, that is, the weight and size, have been developed. Flat panel display devices, liquid crystal display devices, field emission display devices, plasma display panels, and organic light emitting display devices have been proposed.

The organic light emitting display devices display images using OLEDs (organic light emitting diodes) that generate light by recombination of electrons and holes.

The field of application of such organic light emitting display devices has increasingly expanded to include PDAs, MP3 players, mobile phones, etc. due to various advantages, such as high color reproduction and a small thickness.

The organic light emitting diodes used for the organic light emitting display devices include an anode electrode, a cathode electrode, and a light emitting layer formed therebetween. The organic light emitting diode emits light, when electric current flows from the anode electrode and the cathode electrode, and the amount of emitted light changes in accordance with changes in the amount of electric current, such that luminance is controlled.

FIG. 1 is a circuit diagram illustrating a pixel employed in some light emitting display devices. Referring to FIG. 1 , the pixel includes an organic light emitting diode OLED, a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , a fifth transistor T 5 , a sixth transistor T 6 , and a capacitor Cst. The first to sixth transistors T 1 to T 6 have a gate electrode, a source electrode, and a drain electrode, and the capacitor Cst is composed of a first electrode and a second electrode.

Regarding the first transistor T 1 , the source electrode is connected to a first node A, the drain electrode is connected to a second node B, and the gate electrode is connected to a third node C.

Regarding the second transistor T 2 , the source electrode is connected to a data line Dm and the drain electrode is connected to the first node A. Further, the gate electrode is connected to a first scanning line Sn. Therefore, a data signal is transmitted to the first node A by a first scanning signal that is inputted through the first scanning line Sn.

Regarding the third transistor T 3 , the source electrode is connected to the second node B, the drain electrode is connected to the third node C, and the gate electrode is connected to the first scanning line Sn. The potentials of the second node B and the third node C become the same, when the third transistor T 3 is turned on by the first scanning signal that is transmitted through the first scanning line.

Regarding the fourth transistor T 4 , the source is connected to an initialization power supply VINT, the drain electrode is connected to the third node C, and the gate electrode is connected to a second scanning line Sn−1. In this configuration, a scanning signal that is transmitted to the second scanning line Sn−1 is a scanning signal that allows a data signal to be transmitted to the pixel of the previous row.

Regarding the fifth transistor T 5 , the source electrode is connected to a first pixel power supply ELVDD, the drain electrode is connected to the first node A, and the gate electrode is connected to a light emitting control line En. Therefore, the first pixel power supply ELVDD is selectively supplied to the first transistor T 1 , in accordance with a light emitting control signal that is transmitted through the light emitting control line.

Regarding the sixth switching transistor T 6 , the source electrode is connected to the third node C, the drain electrode is connected to the organic light emitting diode OLED, and the gate electrode is connected to the light emitting control line En. Therefore, the electric current flowing from the source electrode of the first transistor to the drain electrode is selectively transmitted to the organic light emitting diode OLED, in accordance with the light emitting control signal that is transmitted through the light emitting control line En.

Regarding the capacitor Cst, the first electrode is connected to the first pixel power supply ELVDD and the second electrode is connected to the third node C. Therefore, when an initialization signal is transmitted to the third node C by the fourth transistor T 4 , the capacitor Cst stores the initialization voltage so that the third node C maintains the initialization voltage. Further, when a data signal is transmitted to the first transistor T 1 by the second transistor T 2 and the third transistor T 3 , the third node C stores voltage corresponding to the data signal.

The current in the OLED is represented by the following Formula 1:

I OLED = β 2 ⁢ ( V ⁢ gs - V ⁢ th ) 2 = ⁢ β 2 ⁢ ⁢ ( Vdata - EL ⁢ V ⁢ DD + V ⁢ th - V ⁢ th ) 2 = ⁢ β 2 ⁢ ( V ⁢ data - EL ⁢ V ⁢ DD ) 2 [ Formula ⁢ ⁢ 1 ]

where I OLED is electric current flowing to the organic light emitting diode OLED, Vgs is voltage applied in between the gate electrode and the source electrode of the first transistor T 1 , EVDDD is voltage of the first pixel power supply, Vth is threshold voltage of the first transistor T 1 , and Vdata is voltage of a data signal.

Referring to Formula 1, the electric current flowing to the organic light emitting diode OLED by the first transistor corresponds to the voltage of the data signal and the voltage of the first pixel power ELVDD, and is independent of the threshold voltage Vth of the first transistor. Therefore, the threshold voltage is compensated.

However, since the electric current flows according to the voltage of the first pixel power ELVDD and the data signal, and the first pixel power transmitted to each pixel is different by voltage drop, uniform electric current does not flow to the pixels.

Further, when the organic light emitting display device has high resolution and receives a high-frequency driving signal, the length of one horizontal time is reduced. For example, the organic light emitting display device is driven at FHD resolution and 60 Hz, the length of one horizontal time is 14.8 μs, while it is driven at FHD resolution and 120 Hz, the length of one horizontal time decreases to 7.4 μs.

As the length of one horizontal time reduces, the time for compensating the threshold voltage reduces, such that the picture quality is deteriorated.

One aspect is a pixel including an organic light emitting diode configured to emit light according to a pixel electric current flowing from a first pixel power supply to a second pixel power supply, a first transistor including a first electrode connected to the first pixel power supply, a second electrode connected to a first node, and a gate connected to a second node, where the pixel electric current flows from the first electrode to the second electrode, according to a voltage of the gate, a second transistor configured to selectively supply a data signal to a third node, a third transistor configured to selectively connect the second electrode of the first transistor with the gate of the first transistor, a fourth transistor configured to selectively supply a voltage of an initialization power supply to the second node, a fifth transistor configured to selectively supply a voltage of a first compensation power supply to the third node, a sixth transistor configured to selectively supply a voltage to a fourth node, a seventh transistor configured to selectively supply the pixel electric current to the organic light emitting diode, a first capacitor connected to the second node and the fourth node, and a second capacitor connected to the third node and the fourth node.

Another aspect is an organic light emitting display device, including a pixel unit including a plurality of pixels circuits, a data driving unit configured to supply a data signal to the pixel unit, a power supply unit configured to supply a first pixel power, a second pixel power, a first compensation power, and a second compensation power to the pixel unit, and a scanning driving unit configured to selectively supply the data signal, the first pixel power, the second pixel power, the first compensation power, and the second compensation power to the pixel unit such that pixel electric current corresponding to the data signal flows to the pixel, where each of the pixel circuits includes an organic light emitting diode configured to emit light according to a pixel electric current flowing from a first pixel power supply to a second pixel power supply, a first transistor including a first electrode connected to the first pixel power supply, a second electrode connected to a first node, and a gate connected to a second node, where the pixel electric current flows from the first electrode to the second electrode, according to a voltage of the gate, a second transistor configured to selectively supply a data signal to a third node, a third transistor configured to selectively connect the second electrode of the first transistor with the gate of the first transistor, a fourth transistor configured to selectively supply a voltage of an initialization power supply to the second node, a fifth transistor configured to selectively supply a voltage of a first compensation power supply to the third node, a sixth transistor configured to selectively supply a voltage to a fourth node, a seventh transistor configured to selectively supply the pixel electric current to the organic light emitting diode, a first capacitor connected to the second node and the fourth node, and a second capacitor connected to the third node and the fourth node.

FIG. 1 is a circuit diagram illustrating a pixel employed in a common organic light emitting display device;

FIG. 2 is a diagram illustrating the structure of a first embodiment of an organic light emitting display device;

FIG. 3 is a circuit diagram illustrating an embodiment of a pixel employed in the organic light emitting display device shown in FIG. 2 ;

FIG. 4 is a timing diagram illustrating the operation of the pixel shown in

FIG. 3 ;

FIG. 5 is a circuit diagram illustrating an embodiment of a pixel employed in the organic light emitting display device shown in FIG. 2 ;

FIG. 6 is a circuit diagram illustrating an embodiment of a pixel employed in the organic light emitting display device shown in FIG. 2 ;

FIG. 7 is a diagram illustrating the structure of an embodiment of an organic light emitting display device;

FIG. 8 is a circuit diagram illustrating an embodiment of a pixel employed in the organic light emitting display device shown in FIG. 6 ;

FIG. 9 is a timing diagram illustrating the operation of the pixel show in FIG. 8 ;

FIG. 10 is a circuit diagram illustrating an embodiment of a pixel employed in the organic light emitting display device shown in FIG. 6 ; and

FIG. 11 is a circuit diagram illustrating an embodiment of pixel employed in the organic light emitting display device shown in FIG. 7 .

Hereinafter, certain exemplary embodiments will be described with reference to the accompanying drawings. Herein, when a first element is described as being coupled to a second element, the first element may not only be directly coupled to the second element but may be indirectly coupled to the second element via a third element. Further, some of the elements that are not essential to the complete understanding of the invention are omitted for clarity. Also, like reference numerals generally refer to like elements throughout.

Embodiments are generally described with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating the structure of an organic light emitting display device. Referring to FIG. 2 , an organic light emitting display device includes a pixel unit 100 a , a data driving unit 200 a , a scanning driving unit 300 a , and a power supply unit 400 a.

The pixel unit 100 a includes m data lines D 1 , D 2 , . . . Dm−1, and Dm, n first scanning lines S 11 , S 12 , . . . S 1 n− 1, and S 1 n, n first sub-scanning lines S 11 b , S 12 b , . . . S 1 n− 1b, and S 1 nb , n second sub-scanning lines S 21 , S 22 , . . . S 2 n− 1, and S 2 n, n third sub-scanning lines S 31 , S 32 , . . . S 3 n− 1, and S 3 n , and n light emitting control lines E 1 , E 2 , . . . En−1, and En, and further includes a plurality of pixels 101 a that are formed in the regions near intersections of the m data lines D 1 , D 2 , . . . Dm−1, and Dm, the n first scanning lines S 11 , S 12 , . . . S 1 n− 1, and S 1 n , the n second sub-scanning lines S 21 , S 22 , . . . S 2 n− 1, and S 2 n , the n third sub-scanning lines S 31 , S 32 , . . . S 3 n− 1, and S 3 n , the first sub-scanning lines S 11 b , S 12 b , S 1 n− 1b, and S 1 nb , and the n light emitting control lines E 1 , E 2 , . . . En−1, and En. The pixel 101 a includes a pixel circuit with an organic light emitting element (not shown), generates pixel electric current that flows to the pixels according to data signals transmitted through the m data lines D 1 , D 2 , . . . Dm−1, and Dm, and scanning signal, sub-scanning signals, and light emitting control signals that are transmitted through the n first scanning lines S 11 , S 12 , . . . S 1 n− 1, and S 1 n , the n first sub-scanning lines S 11 b , S 12 b , . . . S 1 n− 1b, and S 1 nb , the n second sub-scanning lines S 21 , S 22 , . . . S 2 n− 1, and S 2 n , and the n third sub-scanning lines S 31 , S 32 , . . . S 3 n− 1, and S 3 n in the pixel circuit, and controls the flow of the pixel current to the organic light emitting elements. In this configuration, the second scanning signals that are transmitted to the pixels in the previous rows may be used instead of the third scanning signals transmitted through the third scanning lines S 31 , S 32 , . . . S 3 n− 1, and S 3 n.

Further, electric current corresponding to the data signals is made flow to the pixel from a first pixel power supply ELVDD, to a second pixel power supply ELVSS, with use of a first compensation power supply VSUS 1 , a second compensation power supply VSUS 2 , and an initialization power supply VINT. In some embodiments, the voltage of the first compensation power supply VSUS 1 is substantially equal to the voltage of the first pixel power supply ELVDD.

The data driving unit 200 a is connected to the m data lines D 1 , D 2 , . . . Dm−1, and Dm, and generates data signals for one row and sequentially transmits them to the m data lines D 1 , D 2 , . . . Dm−1, and Dm.

The scanning driving unit 300 a is connected with the n first scanning lines S 11 , S 12 , . . . S 2 n− 1, and S 1 n , the n first sub-scanning lines S 11 , S 12 , . . . S 1 n− 1, and S 1 n , the n second scanning lines S 21 , S 22 , . . . S 2 n− 1, and S 2 n , and the n third scanning lines S 31 , S 32 , . . . S 3 n− 1, and S 3 n , and generates and transmits first scanning signals, first sub-scanning signals, second scanning signals, and third scanning signals to the n first scanning lines S 11 , S 12 , . . . S 1 n− 1, and S 1 n , the n first sub-scanning lines S 11 , S 12 , . . . S 1 n− 1, and S 1 n , the n second scanning lines S 21 , S 22 , . . . S 2 n− 1, and S 2 n , and the n third scanning lines S 31 , S 32 , . . . S 3 n− 1, and S 3 n , respectively.

Further the scanning driving unit 300 a is connected with the n light emitting control lines E 1 , E 2 , . . . En−1, and En, and generates and transmits light emitting control signals to the n light emitting control lines E 1 , E 2 , . . . En−1. Although, the light emitting control signals are shown to be generated by the scanning driving unit 300 a , the light emitting control signals may be generated by another driving unit and transmitted to the n light emitting control lines E 1 , E 2 , . . . En−1.

The power supply unit 400 a generates and transmits the first pixel power ELVDD, the second pixel power ELVSS, the first compensation power VSUS 1 , the second compensation power VSUS 2 , and the initialization power VINT to the pixel unit 100 a.

FIG. 3 is a circuit diagram illustrating an embodiment of a pixel employed in the organic light emitting display device shown in FIG. 2 . Referring to FIG. 3 , the pixel 101 a includes a first to seventh transistors M 11 to M 71 , first and second capacitors C 11 and C 21 , and an organic light emitting diode OLED. Further, the first pixel power ELVDD and the second pixel power ELVSS having lower voltage than the first pixel power ELVDD are transmitted to the pixel 101 a . In addition, the first compensation power VSUS 1 and the initialization power VINT are transmitted to the pixel 101 a.

The pixel 101 a is connected to the data line Dm, the first scanning line S 1 n , the second scanning line S 2 n , the third scanning line S 3 n , the first sub-scanning line S 1 nb , and the light emitting control line En. Further, each of the transistors includes threes electrodes of source, drain, and gate, and assuming that the source is a first electrode, the drain may be a second electrode.

Regarding the first transistor M 11 , the source is connected to the first power supply ELVDD, the drain is connected to the first node N 11 , and the gate is connected to the second node 21 .

Regarding the second transistor M 21 , the source is connected to the data line Dm, the drain is connected to the third node N 31 , and the gate is connected to the first scanning line S 1 n.

Regarding the third transistor M 31 , the source is connected to the first node N 11 , the drain is connected to the second node N 21 , and the gate is connected to the second scanning line S 2 n.

Regarding the fourth transistor M 41 , the source is connected to the initialization power supply VINT, the drain is connected to the second node N 21 , and the gate is connected to the third scanning line S 3 n.

Regarding the fifth transistor M 51 , the source is connected to the first compensation power supply VSUS 1 , the drain is connected to the third node N 31 , and the gate is connected to the first sub-scanning line S 1 nb.

Regarding the sixth transistor M 61 , the source is connected to the first pixel power supply ELVDD, the drain is connected to the fourth node N 41 , and the gate is connected to the first scanning line S 1 n.

Regarding the seventh transistor M 71 , the source is connected to the first node N 11 , the drain is connected to the organic light emitting diode OLED, and the gate is connected to the light emitting control line En.

Regarding the first capacitor C 11 , the first electrode is connected to the second node N 21 and the second electrode is connected to the fourth node N 41 .

Regarding the second capacitor C 21 , the first electrode is connected to the fourth node N 41 and the second electrode is connected to the third node N 31 .

Regarding the organic light emitting diode OLED, the anode is connected to the seventh transistor M 71 and the cathode is connected to the second pixel power supply ELVSS.

FIG. 4 is a timing diagram illustrating the operation of the pixel shown in FIG. 3 . Referring to FIG. 4 , signals that are inputted to the pixel 101 a include a first scanning signal SS 1 n , a second scanning signal SS 2 n , a third scanning signal SS 3 n , a first sub-scanning signal SS 1 nb , and a light emitting control signal ESn.

First, in the first period TD 1 , the first scanning signal SS 1 n , the second scanning signal SS 2 n , and the third scanning signal SS 3 n are at the high state, and the first sub-scanning signal SS 1 nb and the light emitting control signal ESn are at the low state. Therefore, the second transistor M 21 , the third transistor M 31 , the fourth transistor M 41 , and the sixth transistor M 61 are at the off-state, and the fifth transistor M 51 and the seventh transistor M 71 are at the on-state. Accordingly, the first compensation power VSUS 1 is transmitted to the third node N 31 . The voltage of the first compensation power VSUS 1 is set to correspond to the voltage of a data signal displaying black, such that electric current does not flow from the source to the drain of the first transistor M 11 , when the first compensation power VSUS 1 is transmitted to the third node N 31 and the second node N 21 changes in voltage. Therefore, electric current does not flow to the organic light emitting diode OLED, even if the seventh transistor M 71 is in the on-state.

In the second period TD 2 , the first scanning signal SS 1 n is maintained at the low state, the second scanning signal SS 2 n is maintained at the high state, the third scanning signal SS 3 n and the first sub-scanning signal SS 1 nb are maintained at the high state, and the light emitting control signal ESn is maintained at the low state. Therefore, the second transistor M 21 , the sixth transistor M 61 , and the seventh transistor M 71 are at the on-state, and the third transistor M 31 , the fourth transistor M 41 , and the fifth transistor M 51 are at the off-state. When the second transistor M 21 , the sixth transistor M 61 , and the seventh transistor M 71 are at the on-state, a data signal Vdata is transmitted to the third node N 31 and the first power ELVDD is transmitted to the fourth node N 41 The voltage of the first power ELVDD is high, such that electric current does not flow to the organic light emitting diode OLED, even if the seventh transistor M 71 are in the on-state.

In the third period TD 3 , the first scanning signal SS 1 n is maintained at the low state, and the first sub-scanning signal SS 1 nb , the second scanning signal SS 2 n , and the light emitting control signal ESn are maintained at the high state. Further, the third scanning signal SS 3 n changes from the high state to the low state. Therefore, the second transistor M 21 , the fourth transistor M 41 , and the sixth transistor M 61 are in at the on-state, and the third transistor M 31 , the fifth transistor M 51 , and the seventh transistor M 71 are in the off-state. Accordingly, the voltage of the data signal Vdata and the voltage of the first pixel power supply ELVDD are maintained. Further, the initialization power VINT is transmitted to the second node N 21 by the fourth transistor M 41 .

In the fourth period TD 4 , the first scanning signal SS 1 n and the second scanning signal SS 2 n are maintained at the low state and the third scanning signal SS 3 n is maintained at the high state. Further, the first sub-scanning signal SS 1 nb and the light emitting control signal are maintained at the high state. Therefore, the second transistor M 21 , the third transistor M 31 , and the sixth transistor M 61 are in the on-state, and the fourth transistor M 41 , the fifth transistor M 51 , and the seventh transistor M 71 become off-state. Since the second transistor M 21 and the sixth transistor M 61 are at the on-state, the voltage of the data signal Vdata and the voltage of the first pixel power supply ELVDD are maintained at the third node N 31 and the fourth node 41 , respectively. Further, since the third transistor M 31 is at the on-state, the first transistor M 11 is diode connected, such that electric current flows from the source to the drain of the first transistor M 11 . In this process, since the seventh transistor M 71 is at the off-state by the light emitting control signal, the flow of electric current to the organic light emitting diode OLED is blocked. Furthermore, as the first transistor M 11 is diode connected, a voltage corresponding to the following Formula 2 is transmitted to the gate of the first transistor M 11 ,

Vg=ELVDD+Vth   [Formula 2]

where, Vg is gate voltage of the first transistor M 11 , ELVDD is voltage of the first pixel power supply ELVDD, and Vth is threshold voltage of the first transistor M 11 .

The length of the fourth period TD 4 can change, and it is possible to ensure sufficient time that is taken to transmit the voltage corresponding to Formula 2 to the second node N 21 by adjusting the length of the fourth period TD 4 .

In the fifth period TD 5 , the first scanning signal SS 1 n , the second scanning signal SS 2 n , the third scanning signal SS 3 n , and the light emitting control signal are maintained at the high state, and the first sub-scanning signal SS 1 nb is at the low state. The second transistor M 21 , the third transistor M 31 , the fourth transistor M 41 , the sixth transistor M 61 , and the seventh transistor M 71 become off-state, and the fifth transistor M 51 becomes the on-state. Therefore, the voltage of the third node N 31 is changed from the voltage of the data signal Vdata to the voltage of the first compensation power supply VSUS 1 . Further, since the fourth transistor M 41 and the sixth transistor M 61 are in the off-state, the voltage of the fourth node N 41 and the second node N 21 changes by the difference between the voltage of the data signal and the voltage of the first compensation power supply VSUS 1 .

Therefore, the voltage of the second node N 21 changes to the voltage corresponding to the following Formula 3, in which the voltage of the second node N 21 is the voltage of the gate of the first transistor M 11 ,

Vg=ELVDD+Vth− ( V data−VSUS1)  [Formula 3]

where, Vg is the gate voltage of the first transistor M 11 , ELVDD is the voltage of the first pixel power supply ELVDD, Vth is the threshold voltage of the first transistor M 11 , Vdata is the voltage of the data signal Vdata, and VSUS 1 is the voltage of the first compensation power supply VSUS 1 .

In the sixth period TD 6 , the first scanning signal SS 1 n , the second scanning signal SS 2 n , and the third scanning signal SS 3 n are maintained at the high state, and the first sub-scanning signal SS 1 nb and the light emitting control signal ESn are maintained at the low state. Therefore, the second transistor M 21 , the third transistor M 31 , the fourth transistor M 41 , and the sixth transistor M 61 are in the off-state, and the fifth transistor M 51 and the seventh transistor M 71 are in the on-state. Since the seventh transistor M 71 is in the on-state, electric current corresponding to the voltage transmitted to the gate of the first transistor M 11 flows to the organic light emitting diode OLED. Further, since the first compensation power VSUS 1 is still transmitted to the third node N 31 , there is no change in voltage of the gate of the first transistor M 11 during the fifth period TD 5 .

Therefore, the current flowing to the organic light emitting diode OLED is represented by the following Formula 4,

Ids = β ⁡ ( V ⁢ gs - V ⁢ th ) 2 = ⁢ β ( EL ⁢ V ⁢ DD - ( EL ⁢ V ⁢ DD + V ⁢ th + ⁢ V ⁢ SUS ⁢ ⁢ 1 - V ⁢ data ) + V ⁢ th ) 2 = ⁢ β ⁡ ( V ⁢ data - V ⁢ sus ⁢ ⁢ 1 ) 2 [ Formula ⁢ ⁢ 4 ]

where, Ids is electric current flowing to the organic light emitting diode OLED, 13 is a constant, and Vgs is voltage between the source and the gate of the first transistor M 11 .

Therefore, the electric current flowing to the organic light emitting diode OLED corresponds to the voltage of the first compensation power supply VSUS 1 and the data signal Vdata. That is, the current is independent of variation of the threshold voltage of the first transistor M 11 and the voltage of the first pixel power supply ELVDD. Accordingly, the circuit of FIG. 3 compensates for variation of the threshold voltage of the first transistor M 11 and the voltage of the first pixel power supply ELVDD.

Further, the gate voltage of the first transistor M 11 is not changed even if the voltage of the data signal Vdata flowing to the data line Dm changes. A change in the voltage of the data signal Vdata does not affect the gate voltage of the first transistor M 11 because the voltage of the first compensation power supply VSUS 1 is applied to node N 31 while the organic light emitting diode OLED emits light. Therefore, it is possible to prevent cross-talk that would otherwise be generated by a change in voltage of the data signal Vdata.

FIG. 5 is a circuit diagram illustrating an embodiment of a pixel circuit employed in the organic light emitting display device shown in FIG. 2 . Referring to FIG. 5 , the pixel circuit includes first to seventh transistors M 12 to M 72 , first and second capacitors C 12 and C 22 , and an organic light emitting diode OLED. Further, the first pixel power ELVDD and the second pixel power ELVSS having lower voltage than the first pixel power ELVDD are transmitted to the pixel circuit. Furthermore, the first compensation power VSUS 1 , the second compensation power VSUS 2 , and the initialization power VINT are transmitted to the pixel circuit. In addition, the pixel circuit is connected to the first scanning line S 1 n , the second scanning line S 2 n , the third scanning line S 3 n , the first sub-scanning line S 1 nb , and the light emitting control line En.

Regarding the first transistor M 12 , the source is connected to the first pixel power supply ELVDD and the drain is connected to the first node N 12 . Further, the gate is connected to the second node N 22 .

Regarding the second transistor M 22 , the source is connected to the data line Em, the drain is connected to the third node N 32 , and the gate is connected to the first scanning line S 1 n.

Regarding the third transistor M 32 , the source is connected to the first node N 12 , the drain is connected to the second node N 22 , and the gate is connected to the second scanning line S 2 n.

Regarding the fourth transistor M 42 , the source is connected to the initialization power supply VINT, the drain is connected to the second node N 22 , and the gate is connected to the third scanning line S 3 n.

Regarding the fifth transistor M 52 , the source is connected to the first compensation power supply VSUS 1 , the drain is connected to the third node N 32 , and the gate is connected to the first sub-scanning line S 1 nb.

Regarding the sixth transistor M 62 , the source is connected to the second compensation power supply VSUS 2 , the drain is connected to the fourth node N 42 , and the gate is connected to the first scanning line S 1 n.

Regarding the seventh transistor M 72 , the source is connected to the first node N 12 , the drain is connected to the organic light emitting diode OLED, and the gate is connected to the light emitting control signal En.

Regarding the first capacitor C 12 , the first electrode is connected to the second node N 22 and the second node is connected to the fourth node N 42 .

Regarding the second capacitor C 22 , the first electrode is connected to the fourth node N 42 and the second electrode is connected to the third node N 32 .

Regarding the organic light emitting diode OLED, the anode is connected to the seventh transistor M 72 and the cathode is connected to the second pixel power supply ELVSS.

The pixel circuit of FIG. 5 has a difference from the pixel shown in FIG. 3 , in that not the pixel power ELVDD, but the second compensation power VSUS 2 is transmitted to the source of the sixth transistor M 62 . However, the circuit of FIG. 5 generally operates the same as the pixel circuit shown in FIG. 3 , and has similar beneficial aspects.

Referring FIG. 6 , the pixel circuit includes first to seventh transistors M 13 to M 73 , first and second capacitor C 13 and C 23 , and an organic light emitting diode OLED. Further, the first pixel power ELVDD and the second pixel power ELVSS having voltage less than the first pixel power ELVDD are transmitted to the pixel circuit. Furthermore, the first compensation power VSUS 1 and the initialization power VINT are transmitted to the pixel circuit. In addition, the pixel circuit is connected with the data line Dm, the first scanning line S 1 n , the second scanning line S 2 n , the third scanning line S 3 n , the first sub-scanning line S 1 nb , and the light emitting control line En.

Regarding the first transistor M 13 , the source is connected to the first pixel power supply ELVDD and the drain is connected to the first node N 13 . Further, the gate is connected to the second node N 23 .

Regarding the second transistor M 23 , the source is connected to the data line Dm, the drain is connected to the third node N 33 , and the gate is connected to the first scanning line S 1 n.

Regarding the third transistor M 33 , the source is connected to the first node N 13 , the drain is connected to the second node N 23 , and the gate is connected to the second scanning line S 2 n.

Regarding the fourth transistor M 43 , the source is connected to the initialization power supply VINT, the drain is connected to the second node N 23 , and the gate is connected to the third scanning line S 3 n.

Regarding the fifth transistor M 53 , the source is connected to the first compensation power supply VSUS 1 , the drain is connected to the third node N 33 , and the gate is connected to the first sub-scanning line S 1 nb.

Regarding the sixth transistor M 63 , the source is connected to the second pixel power supply ELVSS, the drain is connected to the fourth node N 43 , and the gate is connected to the first scanning line S 1 n.

Regarding the seventh transistor M 73 , the source is connected to the first node N 13 , the drain is connected to the organic light emitting diode OLED, and the gate is connected to the light emitting control line En.

Regarding the first capacitor C 13 , the first electrode is connected to the second node N 23 and the second node is connected to the fourth node N 43 .

Regarding the second capacitor C 23 , the first electrode is connected to the fourth node N 43 and the second electrode is connected to the third node N 33 .

Regarding the organic light emitting diode OLED, the anode is connected to the seventh transistor M 73 and the cathode is connected to the second pixel power supply ELVSS.

The pixel circuit connected as described above has a difference from the pixel shown in FIG. 3 in that not the pixel power supply ELVDD, but the second pixel power supply ELVSS is connected to the source of the sixth transistor M 63 . However, the circuit of FIG. 6 generally operates the same as the pixel circuit shown in FIG. 3 , and has similar beneficial aspects.

FIG. 7 is a diagram illustrating the structure of a second embodiment of an organic light emitting display device. Referring to FIG. 7 , the organic light emitting display device includes a pixel unit 100 b , a data driving unit 200 b , a scanning driving unit 300 b , and a power supply unit 400 b.

The pixel unit 100 b includes m data lines D 1 , D 2 , . . . Dm−1, and Dm, n+1 scanning lines S 0 , S 1 , . . . Sn−1, and Sn, n light emitting control lines E 1 , E 2 , . . . En−1, and En, and n sub-light emitting control lines E 1 b , E 2 b , . . . En−1b, and Enb. Further, it includes a plurality of pixels 101 b that are formed in regions near intersections of the m data lines D 1 , D 2 , . . . Dm−1, and Dm, the n+1 scanning lines S 0 , S 1 , Sn−1, and Sn, the n light emitting control lines E 1 , E 2 , . . . En−1, and En, and the n sub-light emitting control lines E 1 b , E 2 b , . . . En−1b, and Enb. A pixel 101 b includes a pixel circuit with an organic light emitting diode, generates in the pixel electric current corresponding to data signals, using data signals transmitted through the m data lines D 1 , D 2 , . . . Dm−1, and Dm, scanning signals, light emitting control signals, and sub-light emitting control signals that are transmitted through the n+1 scanning lines S 0 , S 1 , . . . Sn−1, and Sn, the n light emitting control lines E 1 , E 2 , . . . En−1, and En, and the n sub-light emitting control lines E 1 b , E 2 b , . . . En−1b, and Enb, respectively, and controls flow of the electric current to the organic light emitting diode. Further, it allows electric current corresponding to the data signals to flow to the pixel by receiving the first pixel power ELVDD, the second pixel power ELVSS, the compensation power VSUS, and the initialization power VINT.

The data driving unit 200 b is connected with the m data lines D 1 , D 2 , . . . Dm−1, and Dm, generates data signals for each row, and sequentially transmits them to the m data lines D 1 , D 2 , . . . Dm−1, and Dm.

The scanning driving unit 300 b is connected to the n+1 scanning lines. S 0 , S 1 , . . . Sn−1, and Sn, the n light emitting control lines E 1 , E 2 , . . . En−1, and En, and the n sub-light emitting control lines E 1 b , E 2 b , . . . En−1b, and Enb, and generates and transmits scanning signals, light emitting control signals, and sub-light emitting control signals to the n scanning lines S 0 , S 1 , . . . Sn−1, and Sn, the n light emitting control lines E 1 , E 2 , . . . En−1, and En, and the n sub-light emitting control lines E 1 b , E 2 b , . . . En−1b, and Enb.

Although the light emitting control signals and the sub-light emitting control signals are shown to be generated by the scanning driving unit 300 b , it is possible to generate the light emitting control signals and the sub-light emitting control signals at another driving unit and to transmit them to the n light emitting control lines E 1 , E 2 , . . . En−1, and En and n sub-light emitting control lines E 1 b , E 2 b , . . . En−1b, and Enb.

The power supply unit 400 b generates and transmits the first pixel power ELVDD, the second pixel power ELVSS, the compensation power VSUS, and the initialization power VINT to the pixel unit 100 b.

FIG. 8 is a circuit diagram illustrating an embodiment of a pixel circuit employed in the organic light emitting display device shown in FIG. 7 . Referring to FIG. 8 , the pixel circuit includes first to seventh transistors M 14 to M 74 , first and second capacitors C 14 and C 24 , and an organic light emitting diode OLED. Further, the first pixel power ELVDD and the second pixel power ELVSS having lower voltage than the first pixel power ELVDD are transmitted to the pixel circuit. Further, the compensation power VSUS and the initialization power VINT are transmitted to the pixel circuit. Furthermore, the pixel circuit is connected with the data line Dm, the first scanning line Sn, the second scanning line Sn−1, the light emitting control line En, and the sub-light emitting control line Enb. In addition, each of the transistors include three electrodes of a source, a drain, and a gate, and when the source is a first electrode, the drain may be a second electrode.

Regarding the first transistor M 14 , the source is connected to the first pixel power supply ELVDD and the drain is connected to the first node N 14 . Further, the gate is connected to the second node N 24 .

Regarding the second transistor M 24 , the source is connected to the data line Dm, the drain is connected to the third node N 34 , and the gate is connected to the sub-light emitting control line Enb.

Regarding the third transistor M 34 , the source is connected to the first node N 14 , the drain is connected to the second node N 24 , and the gate is connected to the first scanning line Sn.

Regarding the fourth transistor M 44 , the source is connected to the initialization power supply VINT, the drain is connected to the second node N 24 , and the gate is connected to the second scanning line Sn−1.

Regarding the fifth transistor M 54 , the source is connected to the compensation power supply VSUS, the drain is connected to the third node N 34 , and the gate is connected to the light emitting control lines En.

Regarding the sixth transistor M 64 , the source is connected to the firs pixel power supply ELVDD, the drain is connected to the fourth node N 44 , and the gate is connected to the sub-light emitting control line Enb.

Regarding the seventh transistor M 74 , the source is connected to the first node N 14 , the drain is connected to the organic light emitting diode OLED, and the gate is connected to the first light emitting control line En.

Regarding the first capacitor C 14 , the first electrode is connected to the second node N 24 and the second electrode is connected to the fourth node N 44 .

Regarding the second capacitor C 24 , the first electrode is connected to the fourth node N 44 and the second electrode is connected to the third node N 34 .

Regarding the organic light emitting diode OLED, the anode is connected to the seventh transistor M 74 and the cathode is connected to the second pixel power supply ELVSS.

FIG. 9 is a timing diagram illustrating the operation of the pixel show in FIG. 8 . Referring to FIG. 9 , signals that are inputted to the pixel circuit include a first scanning signal SSn, a second scanning signal SSn−1, a light emitting control signal ESn, and a sub-light emitting control signal ESnb.

During the first period TD 1 , the first scanning signal SSn, the second scanning signal SSn−1, and the sub-light emitting control signal ESnb are at the high state and the light emitting control signal ESn is at the low state. Therefore, the fifth transistor M 54 and the seventh transistor M 74 are in the on-state, and the second transistor M 24 , the third transistor M 34 , the fourth transistor M 44 , and the sixth transistor M 64 are in the off-state. Accordingly, the compensation power VSUS is transmitted to the third node N 34 . The voltage of the compensation power VSUS is set to correspond to the voltage of a data signal displaying black, such that electric current does not flow from the source to the drain of the first transistor M 14 , when the compensation power VSUS is transmitted to the third node N 34 and the second node N 24 changes in voltage. Therefore, electric current does not flow to the organic light emitting diode OLED, even if the seventh transistor M 73 is in the on-state.

In the second period TD 2 , the first scanning signal SSn and the light emitting control signal ESn are in the high state, and the second scanning signal SSn−1 and the sub-light emitting control signal ESnb are in the low state. Therefore, the second transistor M 24 , the fourth transistor M 44 , and the sixth transistor M 64 are in the on-state, and the third transistor M 34 , the fifth transistor M 54 , and the seventh transistor M 74 are in the off-state. As a result, a data signal is transmitted to the third node N 34 through the second transistor M 24 and the voltage of the initialization power supply VINT is transmitted to the second node N 24 by the fourth transistor M 44 . Further, the voltage of the first pixel power supply ELVDD is transmitted to the fourth node N 44 by the sixth transistor M 64 .

In the third period TD 3 , the first scanning signal SSn and the sub-light emitting control signal ESnb are in the low state, and the second scanning signal SSn and the light emitting control signal ESn are in the high state. In this configuration, the second transistor M 24 , the third transistor M 34 , and the sixth transistor M 64 are in the on-state, and the fourth transistor M 44 and the fifth transistor M 54 are in the off-state. Therefore, the data signal is still transmitted to the third node 34 by the second transistor M 24 and the first node N 14 and the second node N 24 are connected by the third transistor M 34 , such that the first transistor M 14 is diode connected. In this configuration, flow of electric current to the organic light emitting diode OLED is blocked by the seventh transistor M 74 . Because the first transistor M 14 is diode connected, a voltage corresponding to Formula 2 is maintained at the gate of the first transistor M 14 .

In the fourth period TD 4 , the light emitting control signal ESn is in the low state and the first scanning signal SS 1 n , the second scanning signal SSn−1, and the sub-light emitting control signal ESnb are in the high state. Therefore, the second transistor M 24 , the third transistor M 34 , and the sixth transistor are in the off-state, and the fifth transistor M 54 and the seventh transistor M 73 are in the on-state. Accordingly, the voltage of the third node N 34 is changed from the voltage of the data signal to the voltage of the compensation power supply VSUS, and the voltage of the second node N 24 is changed from the voltage of the initialization power supply VINT by the first capacitor C 14 and the second capacitor C 24 , such that the voltage of the second node N 24 changes to a voltage represented by the following Formula 5,

Vg=ELVDD+V th−( V data− VSUS )  [Formula 5]

where, Vg is gate voltage of the first transistor M 14 , ELVDD is voltage of the first pixel power supply ELVDD, Vth is threshold voltage of the first transistor M 14 , Vdata is voltage of the data signal Vdata, and VSUS is voltage of the compensation power supply VSUS.

Further, since the seventh transistor M 74 is in the on-state, electric current flows from the first power supply to the second power supply, such that electric current represented by the following Formula 6 flows to the organic light emitting diode OLED,

Ids = β ⁡ ( V ⁢ gs - V ⁢ th ) 2 = ⁢ β ( EL ⁢ V ⁢ DD - ( EL ⁢ V ⁢ DD + V ⁢ th + ⁢ V ⁢ SUS ⁢ - V ⁢ data ) + V ⁢ th ) 2 = ⁢ β ( V ⁢ data - V ⁢ sus ⁢ ) 2 [ Formula ⁢ ⁢ 6 ]

where, Ids is electric current flowing to the organic light emitting diode OLED, β is a constant, and Vgs is voltage between the source and the gate of the first transistor M 14 .

Therefore, the electric current flowing to the organic light emitting diode OLED flows according to the voltage of the voltage of the compensation power supply VSUS and the data signal Vdata. That is, variation in the threshold voltage of the first transistor M 14 and an IR-drop in the voltage of the first pixel power supply ELVDD do not affect the current.

Further, the gate voltage of the first transistor M 14 is not changed even if the voltage of the data signal Vdata flowing to the data line Dm changes. A change in the voltage of the data signal Vdata does not affect the gate voltage of the first transistor M 14 because the voltage of the compensation power supply VSUS is applied to node N 34 while the organic light emitting diode OLED emits light. Therefore, it is possible to prevent cross-talk which would otherwise be generated by changes in the data signal Vdata flowing to the data line Dm.

FIG. 10 is a circuit diagram illustrating an embodiment of a pixel circuit employed in the organic light emitting display device shown in FIG. 7 . Referring to FIG. 10 , the pixel circuit includes first to seventh transistors M 15 to M 17 , first to third capacitors C 15 to C 35 , and on organic light emitting diode OLED. Further, the first pixel power ELVDD and the second pixel power ELVSS having a lower voltage to the first pixel power ELVDD are transmitted to the pixel circuit. In addition, the compensation power VSUS is transmitted to the pixel circuit. Furthermore, the pixel circuit is connected with the data line Dm, the first scanning line S 1 n , the second scanning line S 2 n , the light emitting control line En, and the sub-light emitting control line Enb. In addition, each of the transistors includes three electrodes of a source, a drain, and a gate, and when that the source is a first electrode, the drain may be a second electrode.

Regarding the first transistor M 15 , the source is connected to the first pixel power supply ELVDD and the drain is connected to the first node N 15 . Further, the gate is connected to the second node N 25 .

Regarding the second transistor M 25 , the source is connected to the data line Dm, the drain is connected to the third node N 35 , and the gate is connected to the sub-light emitting control line Enb.

Regarding the third transistor M 35 , the source is connected to the first node N 15 , the drain is connected to the second node N 25 , and the gate is connected to the first scanning line Sn.

Regarding the fourth transistor M 45 , the source is connected to the initialization power supply VINT, the drain is connected to the second node N 25 , and the gate is connected to the second scanning line Sn−1.

Regarding the fifth transistor M 55 , the source is connected to the compensation power supply VSUS, the drain is connected to the third node N 35 , and the gate is connected to the light emitting control line En.

Regarding the sixth transistor M 65 , the source is connected to the first pixel power supply ELVDD, the drain is connected to the fourth node N 45 , and the gate is connected to the sub-light emitting control line Enb.

Regarding the seventh transistor M 75 , the source is connected to the first node N 15 , the drain is connected to the organic light emitting diode OLED, and the gate is connected to the light emitting control line En.

Regarding the first capacitor C 15 , the first electrode is connected to the second node N 25 and the second electrode is connected to the fourth node N 45 .

Regarding the second capacitor C 25 , the first electrode is connected to the fourth node N 45 and the second electrode is connected to the third node N 35 .

Regarding the third capacitor C 35 , the first electrode is connected to the first pixel power supply ELVDD and the second electrode is connected to the second node N 25 .

Regarding the organic light emitting diode OLED, the anode is connected to the seventh transistor M 75 and the cathode is connected to the second pixel power supply ELVSS.

FIG. 11 is a circuit diagram illustrating another embodiment of a pixel circuit employed in the organic light emitting display device shown in FIG. 7 . Referring to FIG. 11 , the pixel circuit includes a first to seventh transistors M 16 to M 76 , first to third capacitors C 16 to C 36 , and an organic light emitting diode OLED. Further, the first pixel power ELVDD and the second pixel power ELVSS having a lower voltage than the first pixel power ELVDD are transmitted to the pixel 101 b . Further, the compensation power VSUS is transmitted to the pixel circuit. Furthermore, the pixel circuit is connected with the data line Dm, the first scanning line S 1 n , the second scanning line S 2 n , the light emitting control line En, and the sub-light emitting control line Enb

Regarding the first transistor, the source is connected to the first pixel power supply ELVDD and the drain is connected to the first node N 16 . Further, the gate is connected to the second node N 26 .

Regarding the second transistor M 26 , the source is connected to the data line Dm, the drain is connected to the third node N 36 , and the gate is connected to the second scanning line Sn−1.

Regarding the third transistor M 36 , the source is connected to the first node N 15 , the drain is connected to the second node N 26 , and the gate is connected to the first scanning line Sn.

Regarding the fourth transistor M 46 , the source is connected to the initialization power supply VINT, the drain is connected to the second node N 26 , and the gate is connected to the second scanning line Sn−1.

Regarding the fifth transistor M 56 , the source is connected to the compensation power supply VSUS, the drain is connected to the third node N 36 , and the gate is connected to the light emitting control line En.

Regarding the sixth transistor M 66 , the source is connected to the first pixel power supply ELVDD, the drain is connected to the fourth node N 46 , and the gate is connected to the sub-light emitting control line Enb.

Regarding the seventh transistor M 76 , the source is connected to the first node N 16 , the drain is connected to the organic light emitting diode OLED, and the gate is connected to the light emitting control line En.

Regarding the first capacitor C 16 , the first electrode is connected to the second node N 26 and the second electrode is connected to the fourth node N 46 .

Regarding the second capacitor C 26 , the first electrode is connected to the fourth node N 46 and the second electrode is connected to the third node N 36 .

Regarding the third capacitor C 36 , the first electrode is connected to the first pixel power supply ELVDD and the second electrode is connected to the second node N 26 .

Regarding the organic light emitting diode OLED, the anode is connected to the seventh transistor M 76 and the cathode is connected to the second pixel power supply ELVSS.

The pixel circuits of FIGS. 10 and 11 have operation and advantages which are similar to those of pixel circuits described above.

While certain exemplary embodiments have been described, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements.