Display device and method of driving the same

This application claims priority to and the benefit of Korean Patent Application No. 10-2009-0123320, filed in the Korean Intellectual Property Office on Dec. 11, 2009, the entire content of which is incorporated herein by reference.

1. Field

Aspects of embodiments according to the present invention relate to a display device and a method of driving the same.

2. Description of the Related Art

A display device includes a display unit that is formed with a plurality of pixels that are arranged in a matrix form. A display unit includes a plurality of scan lines that are formed to extend in a row direction and a plurality of data lines that are formed to extend in a column direction, and the plurality of scan lines and the plurality of data lines are arranged to cross each other. Each of a plurality of pixels is driven by a scan signal and a data signal that are transferred from a corresponding scan line and data line.

A display device may be classified, for example, as a passive matrix light emitting display or an active matrix light emitting display according to a driving method of a pixel. An active matrix light emitting display that selectively emits light from each unit pixel is more desirable from a resolution, contrast, and operation speed viewpoint.

Such a display device can be used as a display device for a portable information terminal such as a personal computer, a mobile phone, or a personal digital assistant (PDA), or as a monitor for various information appliances. A liquid crystal display (LCD) that uses a liquid crystal panel, an OLED display that uses an organic light emitting element, and a plasma display panel (PDP) that uses a plasma panel are widely known examples of such display devices. Various light emitting display devices having a small weight and volume when compared with comparable cathode ray tube (CRT) devices have been developed, and particularly, an OLED display having relatively high light emitting efficiency, luminance, and viewing angle as well as a rapid response speed has been in the spotlight.

However, in a display unit of a display device, a period in which the display unit is divided into a display area and a non-display area may exist. However, during the period, scan signals and data signals may still be supplied to all scan lines and data lines in the display unit. This can cause unnecessary power consumption and thus, there may be a problem that power consumption increases compared to the power needed to drive the display area.

The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Aspects of embodiments of the present invention are directed toward a display device and a method of driving the same capable of reducing power consumption and simplifying a manufacturing process.

In an exemplary embodiment according to the present invention, a display device is provided. The display device includes a display unit and a scan driver. The display unit includes a plurality of scan lines configured to receive a plurality of scan signals, a plurality of data lines configured to receive a plurality of data signals, and a plurality of pixels coupled to the plurality of scan lines and the plurality of data lines. The scan driver is configured to receive a synchronization signal generated in synchronization with a vertical synchronization signal, a first light emitting clock signal, a second light emitting clock signal representing the first light emitting clock signal shifted by a half cycle, a first initialization signal having a first phase delay relative to the second light emitting clock signal, and a second initialization signal having a second phase delay relative to the first light emitting clock signal. The scan driver is configured to generate a plurality of sequential driving signals and the plurality of scan signals. The scan driver is further configured to generate respective ones of the plurality of scan signals as an on-voltage level by respective ones of the plurality of sequential driving signals corresponding to a display area according to an area selection signal that divides the display unit into the display area and a non-display area. The scan driver is also further configured to generate respective ones of the plurality of scan signals as an off-voltage level corresponding to the non-display area according to an inverted area selection signal.

The plurality of scan signals may include a plurality of first scan signals and a plurality of second scan signals. The plurality of sequential driving signals may include a plurality of first sequential driving signals and a plurality of second sequential driving signals. The scan driver may include a plurality of first sequential drivers, a plurality of second sequential drivers, a plurality of first output selection portions, and a plurality of second output selection portions. Each of the plurality of first sequential drivers is configured to be synchronized with the first light emitting clock signal and configured to output one of the second light emitting clock signal or a voltage of a first power source as a respective one of the plurality of first sequential driving signals according to a first input signal and the first initialization signal. Each of the plurality of second sequential drivers is configured to be synchronized with the second light emitting clock signal and configured to output one of the first light emitting clock signal or the first power source voltage as a respective one of the plurality of second sequential driving signals according to a second input signal and the second initialization signal. Each of the plurality of first output selection portions is configured to output one of the first light emitting clock signal or the first power source voltage as a respective one of the plurality of first scan signals according to a corresponding one of the plurality of first sequential driving signals, the area selection signal, the inverted area selection signal, and the second initialization signal. Each of the plurality of second output selection portions is configured to output one of the second light emitting clock signal or the first power source voltage as a respective one of the plurality of second scan signals according to a corresponding one of the plurality of second sequential driving signals, the area selection signal, the inverted area selection signal, and the first initialization signal.

Each of the plurality of first sequential drivers may be configured to receive, as the first input signal, the synchronization signal or a corresponding immediately preceding one of the plurality of second sequential driving signals.

Each of the plurality of first sequential drivers may include first through sixth transistors and first and second capacitors. The first transistor includes a gate terminal configured to receive the first light emitting clock signal, a first terminal, and a second terminal configured to receive the first input signal. The second transistor includes a gate terminal configured to receive the first input signal, a first terminal coupled to the first power source, and a second terminal. The third transistor includes a gate terminal coupled to the second terminal of the second transistor, a first terminal coupled to the first power source, and a second terminal. The first capacitor includes one terminal coupled to the first power source and an other terminal coupled to the gate terminal of the third transistor. The fourth transistor includes a gate terminal coupled to the other terminal of the first capacitor, a first terminal coupled to the first power source, and a second terminal. The fifth transistor includes a gate terminal configured to receive the first initialization signal, a first terminal coupled to the other terminal of the first capacitor, and a second terminal coupled to a second power source. The second capacitor includes one terminal coupled to the second terminal of the fourth transistor and an other terminal coupled to the second terminal of the third transistor. The sixth transistor includes a gate terminal coupled to the one terminal of the second capacitor, a first terminal coupled to the other terminal of the second capacitor, and a second terminal configured to receive the second light emitting clock signal.

Each of the plurality of second sequential drivers may be configured to receive, as the second input signal, a corresponding immediately preceding one of the plurality of first sequential driving signals.

Each of the plurality of second sequential drivers may include first through sixth capacitors and first and second capacitors. The first transistor includes a gate terminal configured to receive the second light emitting clock signal, a first terminal, and a second terminal configured to receive the second input signal. The second transistor includes a gate terminal configured to receive the second input signal, a first terminal coupled to the first power source, and a second terminal. The third transistor includes a gate terminal coupled to the second terminal of the second transistor, a first terminal coupled to the first power source, and a second terminal. The first capacitor includes one terminal coupled to the first power source and an other terminal coupled to the gate terminal of the third transistor. The fourth transistor includes a gate terminal coupled to the other terminal of the first capacitor, a first terminal coupled to the first power source, and a second terminal. The fifth transistor includes a gate terminal configured to receive the second initialization signal, a first terminal coupled to the other terminal of the first capacitor, and a second terminal coupled to a second power source. The second capacitor includes one terminal coupled to the second terminal of the fourth transistor and an other terminal coupled to the second terminal of the third transistor. The sixth transistor includes a gate terminal coupled to the one terminal of the second capacitor, a first terminal coupled to the other terminal of the second capacitor, and a second terminal configured to receive the first light emitting clock signal.

Each of the plurality of first output selection portions may include first through ninth transistors and first and second capacitors. The first transistor includes a gate terminal configured to receive the area selection signal, a first terminal configured to receive a corresponding one of the first sequential driving signals, and a second terminal. The second transistor includes a gate terminal configured to receive the inverted area selection signal, a first terminal coupled to the first power source, and a second terminal coupled to the second terminal of the first transistor. The third transistor includes a gate terminal coupled to the second terminal of the second transistor, a first terminal coupled to the first power source, and a second terminal. The fourth transistor includes a gate terminal configured to receive the second light emitting clock signal, a first terminal coupled to the second terminal of the second transistor, and a second terminal. The fifth transistor includes a gate terminal coupled to the second terminal of the third transistor, a first terminal coupled to the first power source, and a second terminal coupled to the second terminal of the fourth transistor. The sixth transistor includes a gate terminal configured to receive the inverted area selection signal, a first terminal coupled to the gate terminal of the fifth transistor, and a second terminal coupled to a second power source. The first capacitor includes one terminal coupled to the first power source and an other terminal coupled to the first terminal of the sixth transistor. The seventh transistor includes a gate terminal configured to receive the second initialization signal, a first terminal coupled to the other terminal of the first capacitor, and a second terminal coupled to the second power source. The eighth transistor includes a gate terminal coupled to the other terminal of the first capacitor, a first terminal coupled to the first power source, and a second terminal. The second capacitor includes one terminal coupled to the second terminal of the fifth transistor and an other terminal coupled to the second terminal of the eighth transistor. The ninth transistor includes a gate terminal coupled to the one terminal of the second capacitor, a first terminal coupled to the other terminal of the second capacitor, and a second terminal configured to receive the second light emitting clock signal.

Each of the plurality of first output selection portions may include first through eighth transistors and first and second capacitors. The first transistor includes a gate terminal configured to receive a corresponding one of the first sequential driving signals, a first terminal, and a second terminal coupled to a second power source. The second transistor includes a gate terminal configured to receive the area selection signal, a first terminal, and a second terminal coupled to the first terminal of the first transistor. The third transistor includes a gate terminal configured to receive the corresponding one of the first sequential driving signals, a first terminal coupled to the first power source, and a second terminal. The fourth transistor includes a gate terminal coupled to the second terminal of the third transistor, a first terminal coupled to the first power source, and a second terminal coupled to the first terminal of the second transistor. The fifth transistor includes a gate terminal configured to receive the inverted area selection signal, a first terminal coupled to the gate terminal of the fourth transistor, and a second terminal coupled to the second power source. The sixth transistor includes a gate terminal configured to receive the second initialization signal, a first terminal coupled to the gate terminal of the fourth transistor, and a second terminal coupled to the second power source. The first capacitor includes one terminal coupled to the first power source and an other terminal coupled to the first terminal of the sixth transistor. The seventh transistor includes a gate terminal coupled to the other terminal of the first capacitor, a first terminal coupled to the first power source, and a second terminal. The second capacitor includes one terminal coupled to the second terminal of the fourth transistor and an other terminal coupled to the second terminal of the seventh transistor. The eighth transistor includes a gate terminal coupled to the one terminal of the second capacitor, a first terminal coupled to the other terminal of the second capacitor, and a second terminal configured to receive the second light emitting clock signal.

Each of the plurality of second output selection portions may include first through ninth transistors and first and second capacitors. The first transistor includes a gate terminal configured to receive the area selection signal, a first terminal configured to receive a corresponding one of the second sequential driving signals, and a second terminal. The second transistor includes a gate terminal configured to receive the inverted area selection signal, a first terminal coupled to the first power source voltage, and a second terminal coupled to the second terminal of the first transistor. The third transistor includes a gate terminal coupled to the second terminal of the second transistor, a first terminal coupled to the first power source voltage, and a second terminal. The fourth transistor includes a gate terminal configured to receive the first light emitting clock signal, a first terminal coupled to the second terminal of the second transistor, and a second terminal. The fifth transistor includes a gate terminal coupled to the second terminal of the third transistor, a first terminal coupled to the first power source, and a second terminal coupled to the second terminal of the fourth transistor. The sixth transistor includes a gate terminal configured to receive the inverted area selection signal, a first terminal coupled to the gate terminal of the fifth transistor, and a second terminal coupled to a second power source. The first capacitor includes one terminal coupled to the first power source and an other terminal coupled to the first terminal of the sixth transistor. The seventh transistor includes a gate terminal configured to receive the first initialization signal, a first terminal coupled to the other terminal of the first capacitor, and a second terminal coupled to the second power source. The eighth transistor includes a gate terminal coupled to the other terminal of the first capacitor, a first terminal coupled to the first power source, and a second terminal. The second capacitor includes one terminal coupled to the second terminal of the fifth transistor and an other terminal coupled to the second terminal of the eighth transistor. The ninth transistor includes a gate terminal coupled to the one terminal of the second capacitor, a first terminal coupled to the other terminal of the second capacitor, and a second terminal configured to receive the second light emitting clock signal.

Each of the plurality of second output selection portions may include first through eighth transistors and first and second capacitors. The first transistor includes a gate terminal configured to receive a corresponding one of the second sequential driving signals, a first terminal, and a second terminal coupled to a second power source. The second transistor includes a gate terminal configured to receive the area selection signal, a first terminal, and a second terminal coupled to the first terminal of the first transistor. The third transistor includes a gate terminal configured to receive the corresponding one of the second sequential driving signals, a first terminal coupled to the first power source, and a second terminal. The fourth transistor includes a gate terminal coupled to the second terminal of the third transistor, a first terminal coupled to the first power source, and a second terminal coupled to the first terminal of the second transistor. The fifth transistor includes a gate terminal configured to receive the inverted area selection signal, a first terminal coupled to the gate terminal of the fourth transistor, and a second terminal coupled to the second power source. The sixth transistor includes a gate terminal configured to receive the second initialization signal, a first terminal coupled to the gate terminal of the fourth transistor, and a second terminal coupled to the second power source. The first capacitor includes one terminal coupled to the first power source and an other terminal coupled to the first terminal of the sixth transistor. The seventh transistor includes a gate terminal coupled to the other terminal of the first capacitor, a first terminal coupled to the first power source, and a second terminal. The second capacitor includes one terminal coupled to the second terminal of the fourth transistor and an other terminal coupled to the second terminal of the seventh transistor. The eighth transistor includes a gate terminal coupled to the one terminal of the second capacitor, a first terminal coupled to the other terminal of the second capacitor, and a second terminal configured to receive the second light emitting clock signal.

The display device may further include a data driver configured to transfer valid data to the plurality of data lines of the display area and to transfer invalid data to the plurality of data lines of the non-display area.

The data driver may be configured to transfer the valid data to the plurality of data lines for a period in which the area selection signal corresponding to the display area is applied, and to transfer the invalid data to the plurality of data lines for a period in which the inverted area selection signal corresponding to the non-display area is applied.

In accordance with another exemplary embodiment according to the present invention, a method of driving a display device is provided. The display device includes a display unit having a plurality of scan lines configured to receive a plurality of scan signals, a plurality of data lines configured to receive a plurality of data signals, and a plurality of pixels coupled to the plurality of scan lines and the plurality of data lines. The method includes receiving a synchronization signal that is generated in synchronization with a vertical synchronization signal, a first light emitting clock signal, a second light emitting clock signal representing the first light emitting clock signal shifted by a half cycle, a first initialization signal having a first phase delay relative to the second light emitting clock signal, and a second initialization signal having a second phase delay relative to the first light emitting clock signal; generating a plurality of sequential driving signals; and generating the plurality of scan signals. The generating of the plurality of scan signals includes generating respective ones of the plurality of scan signals as an on-voltage level by respective ones of the plurality of sequential driving signals corresponding to a display area according to an area selection signal that divides the display unit into the display area and a non-display area; and generating respective ones of the plurality of scan signals as an off-voltage level corresponding to the non-display area according to an inverted area selection signal.

The generating of the plurality of sequential driving signals may include generating a plurality of first sequential driving signals and a plurality of second sequential driving signals. The generating of each of the plurality of first sequential driving signals may include outputting one of the second light emitting clock signal or a voltage of a first power source according to a first input signal and the first initialization signal that are input in synchronization with the first light emitting clock signal. The generating of each of the plurality of second sequential driving signals may include outputting one of the first light emitting clock signal or the first power source voltage according to a second input signal and the second initialization signal that are input in synchronization with the second light emitting clock signal.

The first input signal may be the synchronization signal or a corresponding one of the plurality of second sequential driving signals.

The second input signal may be a corresponding one of the plurality of first sequential driving signals.

The generating of the respective ones of the plurality of scan signals as the on-voltage level may include outputting one of the first or second light emitting clock signals as the respective ones of the plurality of scan signals according to corresponding ones of the plurality of sequential driving signals and the area selection signal.

The generating of the respective ones of the plurality of scan signals as the off-voltage level may include outputting a first power source voltage as the respective ones of the plurality of scan signals according to corresponding ones of the plurality of sequential driving signals and the inverted area selection signal.

The method may further include transferring valid data to the plurality of data lines for a period in which the area selection signal corresponding to the display area is applied; and transferring invalid data to the plurality of data lines for a period in which the inverted area selection signal corresponding to the non-display area is applied.

As described above, according to embodiments of the present invention, power consumption can be reduced and a manufacturing process can be simplified.

The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of aspects of the present invention.

FIG. 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a pixel PX that is shown in FIG. 1 .

FIG. 3 is a diagram illustrating an image that is displayed in a display unit 100 that is shown in FIG. 1 .

FIG. 4 is a block diagram illustrating a scan driver 200 that is shown in FIG. 1 .

FIG. 5 is a detailed circuit diagram illustrating a configuration of the scan driver 200 that is shown in FIG. 1 .

FIG. 6 is a waveform diagram illustrating an operation of the scan driver 200 that is shown in FIG. 1 .

FIG. 7 is a detailed circuit diagram illustrating another configuration of the scan driver 200 that is shown in FIG. 1 .

In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

Throughout this specification and the claims that follow, when it is described that an element is “coupled” to another element, the element may be “directly coupled” to the other element or “electrically coupled” to the other element through a third element. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

FIG. 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel PX that is shown in FIG. 1 . FIG. 3 is a diagram illustrating an image that is displayed in a display unit 100 that is shown in FIG. 1 .

Referring to FIG. 1 , the display device according to the present exemplary embodiment includes a display unit 100 , a scan driver 200 , a data driver 300 , and a controller 400 . The display unit 100 includes a plurality of signal lines S 1 -Sn and D 1 -Dm, and a plurality of pixels PX that are coupled thereto and that are arranged in an approximately matrix form from an equivalent circuit perspective. The signal lines S 1 -Sn and D 1 -Dm include a plurality of scan lines S 1 -Sn that transfer scan signals and a plurality of data lines D 1 -Dm that transfer data signals. The plurality of scan lines S 1 -Sn extend in an approximately row direction and are substantially parallel to each other, and the plurality of data lines D 1 -Dm extend in an approximately column direction and are substantially parallel to each other.

At different points in time, the display unit 100 may include a display area DA in which an image is displayed and a non-display area NDA in which an image is not displayed, as shown in FIG. 3 . The display unit 100 of FIG. 3 illustrates a standby screen of a mobile phone. In an exemplary embodiment of the present invention, in a standby screen of the mobile phone, the display area is referred to as an area in which icons, etc., display a state of the mobile phone, and the non-display area NDA is referred to as the remaining area of the display unit 100 . In an exemplary embodiment of the present invention, the display area DA is illustrated as an area corresponding to, for example, scan lines S 4 -S 8 .

Referring to FIG. 2 , each pixel PX, for example, a pixel PXij coupled to an i-th (i=1, 2, . . . , n) scan line Si and a j-th (j=1, 2, . . . , m) data line Dj includes an OLED, a driving transistor M 1 , a capacitor Cst, and a switching transistor M 2 . The driving transistor M 1 receives a driving voltage VDD at a source terminal, and a drain terminal thereof is coupled to an anode terminal of the OLED. A gate terminal of the driving transistor M 1 is coupled to a drain terminal of the switching transistor M 2 . The driving transistor M 1 allows a driving current I OLED having a varying intensity according to a voltage that is applied between the gate terminal and the drain terminal to flow to the OLED. A gate terminal of the switching transistor M 2 is coupled to the scan line Si, and a source terminal thereof is coupled to the data line Dj. The switching transistor M 2 performs a switching operation in response to a scan signal that is applied to the scan line Si, and when the switching transistor M 2 is turned on, a data voltage, i.e., a data signal applied to the data line Dj, is transferred to the gate terminal of the driving transistor M 1 .

The capacitor Cst is coupled between the source terminal and the gate terminal of the driving transistor M 1 . The capacitor Cst charges a data voltage that is applied to the gate terminal of the driving transistor M 1 , and even after the switching transistor M 2 is turned off, the capacitor Cst sustains the data voltage charge.

The OLED has an anode coupled to an output terminal of the driving transistor M 1 and a cathode coupled to a common voltage VSS. The OLED displays an image by emitting light with different intensities according to a current I OLED that is supplied by the driving transistor M 1 .

The OLED can emit light of one of the primary colors. The primary colors may include, for example, the three primary colors of red (R), green (G), and blue (B), and a desired color can be displayed with a spatial or temporal combination of the three primary colors. In this case, some OLEDs can emit white light, thereby increasing luminance. Alternatively, the OLEDs of all pixels PX can emit white light and some pixels PX can further include a color filter that changes white light that is emitted from an OLED to a colored light (e.g., a red light, a green light, or a blue light).

In the embodiment of FIG. 2 , the driving transistor M 1 and the switching transistor M 2 are p-channel field effect transistors (FET). However, at least one of the switching transistor M 2 and the driving transistor M 1 may be an n-channel FET. Further, a coupling relationship of the transistors M 1 and M 2 , the capacitor Cst, and the OLED can be changed. The pixel PXij that is shown in FIG. 2 is an example of a pixel of a display device, and a pixel of another form including at least two transistors and one or more capacitors can be used.

Referring again to FIG. 1 , the scan driver 200 is coupled to the scan lines S 1 -Sn of the display unit 100 and sequentially applies scan signals to the scan lines S 1 -Sn according to scan control signals CONT 1 . The scan driver 200 according to the present exemplary embodiment applies scan signals of an on-voltage Von level to scan lines corresponding to the display area DA of the display unit 100 from among the plurality of scan lines S 1 -Sn and applies scan signals of an off-voltage Voff level to scan lines corresponding to the non-display area NDA. Here, the on-voltage Von is a voltage that can turn on the switching transistor M 2 , and the off-voltage Voff is a voltage that can turn off the switching transistor M 2 . Therefore, a pixel PX corresponding to the display area DA emits light and a pixel PX corresponding to the non-display area NDA does not emit light. The scan driver 200 is embodied with P-mos transistors, and a detailed configuration thereof will be described with reference to FIG. 4 .

The data driver 300 is coupled to data lines D 1 -Dm of the display unit 100 . The data driver 300 converts image data DR, DG, and DB that are input from the signal controller 400 to data voltages according to data control signals CONT 2 , and applies the data voltages to the data lines D 1 -Dm.

The data driver 300 is synchronized with a plurality of scan signals that are input to the display area DA to transfer a plurality of data voltages corresponding to the image data DR, DG, and DB to the plurality of data lines D 1 -Dm. Further, the data driver 300 transfers a plurality of non-light emitting data voltages to the plurality of data lines for a period in which data voltages are transferred to the non-display area NDA. The data driver 300 can divide a period in which a plurality of data voltages are transferred to the display area DA and the non-display area NDA according to an area selection signal PTA.

For example, the data driver 300 transfers a plurality of data voltages to a plurality of data lines D 1 -Dm for a period in which a low level area selection signal PTA is input. Similarly, the data driver 300 transfers a plurality of non-light emitting data voltages to a plurality of data lines D 1 -Dm for a period in which a high level area selection signal PTA (or a low level inverted area selection signal PTB) is input. Hereinafter, a plurality of data voltages that are transferred to the display area DA are referred to as valid data VD, and a plurality of data voltages that are transferred to the non-display area NDA are referred to as invalid data NVD.

A pixel PX structure of an embodiment of the present invention is a voltage-writing type of pixel structure. As such, the data driver 300 generates a plurality of data voltages corresponding to the image data DR, DG, and DB and transfers the data voltages to the plurality of data lines D 1 -Dm. However, the present invention is not limited thereto. For example, in one embodiment, when the OLED includes a current-writing type of pixel structure, the data driver 300 generates a plurality of data currents corresponding to the image data DR, DG, and DB and transfers the data currents to the plurality of data lines D 1 -Dm.

The controller 400 receives input signals IS including R, G, and B data, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK from the outside to generate image data DR, DG, and DB, scan control signals CONT 1 , and data control signals CONT 2 .

The scan control signals CONT 1 according to an exemplary embodiment includes a synchronization signal FLM, a first light emitting clock signal CLK 1 , a second light emitting clock signal CLK 2 , a first initialization signal INT 1 , a second initialization signal INT 2 , an area selection signal PTA, and an inverted area selection signal PTB (as shown in FIG. 4 ).

The synchronization signal FLM is a signal generated in synchronization with the vertical synchronization signal Vsync, and indicates a starting point of a frame. Here, the vertical synchronization signal Vsync is a signal having a period in which an image of a frame is displayed, and includes a low level pulse that instructs the start of a frame. The synchronization signal FLM includes a low level pulse that is synchronized with a low level pulse of the first light emitting clock signal CLK 1 that is first generated at a time point when a low level pulse of the vertical synchronization signal Vsync is generated (as shown in FIG. 6 ).

The first light emitting clock signal CLK 1 includes a plurality of low level pulses that are generated according to a cycle (for example, a set or predetermined cycle). The second light emitting clock signal CLK 2 is a clock signal representing the first light emitting clock signal CLK 1 shifted by a half cycle. The first and second light emitting clock signals CLK 1 and CLK 2 have the same frequency.

The first initialization signal INT 1 is generated with a phase delay (e.g., a set or predetermined phase delay) relative to the second light emitting dock signal CLK 2 , and has the same frequency as that of the second light emitting clock signal CLK 2 . The second initialization signal INT 2 is generated with a phase delay (e.g., a set or predetermined phase delay) relative to the first light emitting clock signal CLK 1 , and has the same frequency as that of the first light emitting clock signal CLK 1 .

The area selection signal PTA includes information about a display area DA, and is a signal that is generated when scan signals are applied to scan lines corresponding to a display area DA of a plurality of scan lines S 1 -Sn. The inverted area selection signal PTB is a signal in which the area selection signal PTA is inverted. In an exemplary embodiment of the present invention, for example, when the display area DA is an area corresponding to the scan lines S 4 -S 8 , after a synchronization signal FLM is generated, the area selection signal PTA has a low level from a time point when a fourth clock pulse is generated to a time point when an eighth clock pulse is generated.

The data control signals CONT 2 include a horizontal synchronization start signal STH that notifies the start of transmitting image data signals DR, DG, and DB for a row of pixels PX to the data driver 300 , and a load signal LOAD that instructs the data driver 300 to apply data voltages to the data lines D 1 -Dm. Further, the data control signals CONT 2 according to an exemplary embodiment of the present invention includes a partial data driving signal PD for outputting valid data according to the area selection signal PTA.

FIG. 4 is a block diagram illustrating a scan driver 200 that is shown in FIG. 1 .

Referring to FIG. 4 , the scan driver 200 includes a plurality of sequential drivers 210 _ 1 - 210 — n and a plurality of output selection portions 220 _ 1 - 220 — n.

The plurality of sequential drivers 210 _ 1 - 210 — n includes a plurality of sequential drivers ( 210 — x ; x is an odd number) (hereinafter referred to as first sequential drivers) that generates odd-numbered (first) sequential driving signals and a plurality of sequential drivers ( 210 — y ; y is an even number) (hereinafter referred to as second sequential drivers) that generates even-numbered (second) sequential driving signals among a plurality of sequential driving signals G 1 -Gn.

Each first sequential driver 210 — x of the plurality of first sequential drivers receives a first initialization signal INT 1 and first and second light emitting clock signals CLK 1 and CLK 2 . Further, each first sequential driver 210 — x receives a second sequential driving signal Gx−1 output from a second sequential driver 210 — x− 1 among the plurality of second sequential drivers that immediately precedes (e.g. is earlier than and adjacent to) the first sequential driver 210 — x . First sequential driver 210 — x is synchronized with the first light emitting clock signal CLK 1 to output one of the second light emitting clock signal CLK 2 or a first power source voltage VDD as a first sequential driving signal Gx according to a corresponding second sequential driving signal Gx−1 and the first initialization signal INT 1 .

Here, a first sequential driver 220 _ 1 of the plurality of first sequential drivers receives a synchronization signal FLM instead of a second sequential driving signal. Therefore, the first sequential driver 220 _ 1 is synchronized with the first light emitting clock signal CLK 1 to output one of the second light emitting clock signal CLK 2 or the first power source voltage VDD as a first sequential driving signal G 1 according to the synchronization signal FLM and the first initialization signal INT 1 .

Each second sequential driver 210 — y of the plurality of second sequential drivers receives a second initialization signal INT 2 and the first and second light emitting clock signals CLK 1 and CLK 2 . Each second sequential driver 210 — y receives a first sequential driving signal Gy−1 output from a first sequential driver 210 — y− 1 among the plurality of first sequential drivers that immediately precedes (e.g., is earlier than and adjacent to) the second sequential driver 210 — y . Second sequential driver 210 — y is synchronized with the second light emitting clock signal CLK 2 to output one of the first light emitting clock signal CLK 1 or the first power source voltage VDD as a second sequential driving signal Gy according to a corresponding first sequential driving signal Gy−1 and the second initialization signal INT 2 .

The plurality of output selection portions 220 _ 1 - 220 — n includes a plurality of output selection portions ( 220 — x ; x is an odd number) (hereinafter referred to as first output selection portions) that generates odd-numbered (first) scan signals and a plurality of output selection portions ( 220 — y ; y is an even number) (hereinafter referred to as second output selection portions) that generates even-numbered (second) scan signals among a plurality of scan signals SS 1 -SSn.

Each first output selection portion 220 — x of the plurality of first output selection portions receives an area selection signal PTA, an inverted area selection signal PTB, the second initialization signal INT 2 , and the first and second light emitting clock signals CLK 1 and CLK 2 . Further, each first output selection portion 220 — x receives a first sequential driving signal Gx output from a corresponding first sequential driver 210 — x . The first output selection portion 220 — x outputs one of the first light emitting clock signal CLK 1 or the first power source voltage VDD as a first scan signal SSx according to the corresponding first sequential driving signal Gx, area selection signal PTA, inverted area selection signal PTB, and second initialization signal INT 2 .

Each second output selection portion 220 — y of the plurality of second output selection portions receives the area selection signal PTA, the inverted area selection signal PTB, the first initialization signal INT 1 , and the first and second light emitting clock signals CLK 1 and CLK 2 . Further, each second output selection portion 220 — y receives a second sequential driving signal Gy output from a corresponding second sequential driver 210 — y . The second output selection portion 220 — y outputs one of the second light emitting clock signal CLK 2 or the first power source voltage VDD as a second scan signal SSy according to the corresponding second sequential driving signal Gy, area selection signal PTA, inverted area selection signal PTB, and first initialization signal INT 1 .

FIG. 5 is a detailed circuit diagram illustrating a configuration of the scan driver 200 that is shown in FIG. 1 . For better understanding and ease of description, FIG. 5 illustrates only first and second sequential drivers 210 _ 1 and 210 _ 2 and first and second output selection portions 220 _ 1 and 220 _ 2 , but the circuit configuration of the remaining sequential drivers and output selection portions is substantially identical to that of the first and second sequential drivers 210 _ 1 and 210 _ 2 and the first and second output selection portions 220 _ 1 and 220 _ 2 .

Referring to FIG. 5 , the first sequential driver 210 _ 1 includes a plurality of transistors P 1 -P 6 and a plurality of capacitors C 1 and C 2 . Here, the plurality of transistors P 1 -P 6 are formed as P-mos transistors. The P-mos transistor includes a gate terminal, a source terminal, and a drain terminal, and an electrical connection degree is determined according to a difference between a voltage that is input to the gate terminal and a voltage of the source terminal.

The transistor P 1 includes a gate terminal configured to receive a synchronization signal FLM and a source terminal coupled to the first power source VDD. The transistor P 2 includes a drain terminal coupled to the gate terminal of the transistor P 1 and configured to receive the synchronization signal FLM, a gate terminal configured to receive the first light emitting clock signal CLK 1 , and a source terminal.

The transistor P 3 includes a gate terminal coupled to a drain terminal of the transistor P 1 , a drain terminal coupled to the source terminal of the transistor P 2 , and a source terminal coupled to the first power source VDD. The source terminal of the transistor P 2 and the drain terminal of the transistor P 3 are coupled to a gate terminal of the transistor P 6 . When the transistor P 2 is electrically connected by the first clock signal CLK 1 , if the synchronization signal FLM is in a low level, the transistor P 6 is electrically connected. When the transistor P 3 is electrically connected, the transistor P 6 is turned off by the first power source voltage VDD.

One terminal (e.g., end or side) of the capacitor C 1 is coupled to the first power source VDD. The transistor P 4 includes a gate terminal configured to receive a first initialization signal INT 1 , a drain terminal coupled to a second power source VSS, and a source terminal coupled to an other terminal of the capacitor C 1 . The transistor P 5 includes a gate terminal coupled to the source terminal of the transistor P 4 and the other terminal of the capacitor C 1 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 6 .

The transistor P 6 includes a gate terminal coupled to the one terminal of the capacitor C 2 and a drain terminal configured to receive the second light emitting clock signal CLK 2 . An other terminal of the capacitor C 2 is coupled to a source terminal of the transistor P 6 . A contact point of the drain terminal of the transistor P 5 and the source terminal of the transistor P 6 becomes an output terminal of the first sequential driving signal G 1 .

The second sequential driver 210 _ 2 includes a plurality of transistors P 7 -P 12 and a plurality of capacitors C 3 and C 4 . Here, the plurality of transistors P 7 -P 12 are formed as P-mos transistors.

The transistor P 7 includes a gate terminal configured to receive the first sequential driving signal G 1 and a source terminal coupled to the first power source VDD. The transistor P 8 includes a drain terminal coupled to the gate terminal of the transistor P 7 and configured to receive the first sequential driving signal G 1 , a gate terminal configured to receive the second light emitting clock signal CLK 2 , and a source terminal.

The transistor P 9 includes a gate terminal coupled to a drain terminal of the transistor P 7 , a drain terminal coupled to the source terminal of the transistor P 8 , and a source terminal coupled to the first power source VDD. The source terminal of the transistor P 8 and the drain terminal of the transistor P 9 are coupled to a gate terminal of the transistor P 12 . When the transistor P 8 is electrically connected by the second clock signal CLK 2 , if the first sequential driving signal G 1 is in the low level, the transistor P 12 is electrically connected. When the transistor P 9 is electrically connected, the transistor P 12 is turned off by the first power source voltage VDD.

One terminal of the capacitor C 3 is coupled to the first power source VDD. The transistor P 10 includes a gate terminal configured to receive a second initialization signal INT 2 , a drain terminal coupled to the second power source VSS, and a source terminal coupled to an other terminal of the capacitor C 3 . The transistor P 11 includes a gate terminal coupled to the source terminal of the transistor P 10 and the other terminal of the capacitor C 3 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 12 .

The transistor P 12 includes a gate terminal coupled to the one terminal of the capacitor C 4 and a drain terminal configured to receive the first light emitting clock signal CLK 1 . An other terminal of the capacitor C 4 is coupled to a source terminal of the transistor P 12 . A contact point of the drain terminal of the transistor P 11 and the source terminal of the transistor P 12 becomes an output terminal of the second sequential driving signal G 2 .

The first output selection portion 220 _ 1 includes a plurality of transistors P 13 -P 21 and a plurality of capacitors C 5 and C 6 . Here, the plurality of transistors P 13 -P 21 are formed as P-mos transistors.

The transistor P 13 includes a gate terminal configured to receive the inverted area selection signal PTB, a source terminal coupled to the first power source voltage VDD, and a drain terminal coupled to a drain terminal of the transistor P 14 . The transistor P 14 includes a source terminal configured to receive the first sequential driving signal G 1 and a gate terminal configured to receive the area selection signal PTA. The transistor P 15 includes a gate terminal coupled to the drain terminal of the transistor P 13 and a source terminal coupled to the first power source VDD. The transistor P 16 includes a source terminal coupled to the drain terminal of the transistor P 14 and a gate terminal configured to receive the second light emitting clock signal CLK 2 .

The transistor P 17 includes a gate terminal coupled to a drain terminal of the transistor P 15 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a drain terminal of the transistor P 16 . The transistor P 18 includes a gate terminal configured to receive the inverted area selection signal PTB, a drain terminal coupled to the second power source VSS, and a source terminal coupled to the drain terminal of the transistor P 15 . One terminal of the capacitor C 5 is coupled to the first power source VDD. The transistor P 19 includes a gate terminal configured to receive the second initialization signal INT 2 , a drain terminal coupled to the second power source VSS, and a source terminal coupled to an other terminal of the capacitor C 5 .

The transistor P 20 includes a gate terminal coupled to the other terminal of the capacitor C 5 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 21 . The transistor P 21 includes a gate terminal coupled to one terminal of the capacitor C 6 and a drain terminal configured to receive the first light emitting clock signal CLK 1 . A contact point of the drain terminal of the transistor P 20 and the source terminal of the transistor P 21 becomes an output terminal of the first scan signal SS 1 . One terminal of the capacitor C 6 is coupled to the gate terminal of the transistor P 21 , and the other terminal thereof is coupled to the source terminal of the transistor P 21 .

The second output selection portion 220 _ 2 includes a plurality of transistors P 22 -P 30 and a plurality of capacitors C 7 and C 8 . Here, the plurality of transistors P 22 -P 30 are formed as P-mos transistors.

The transistor P 22 includes a gate terminal configured to receive the inverted area selection signal PTB, a source terminal coupled to the first power source VDD, and a drain terminal coupled to a drain terminal of the transistor P 23 . The transistor P 23 includes a source terminal configured to receive the second sequential driving signal G 2 and a gate terminal configured to receive the area selection signal PTA. The transistor P 24 includes a gate terminal coupled to the drain terminal of the transistor P 22 and a source terminal coupled to the first power source VDD. The transistor P 25 includes a source terminal coupled to the drain terminal of the transistor P 23 and a gate terminal configured to receive the first light emitting clock signal CLK 1 .

The transistor P 26 includes a gate terminal coupled to a drain terminal of the transistor P 24 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a drain terminal of the transistor P 25 . The transistor P 27 includes a gate terminal configured to receive the inverted area selection signal PTB, a drain terminal coupled to the second power source voltage VSS, and a source terminal coupled to the drain terminal of the transistor P 24 . One terminal of the capacitor C 7 is coupled to the first power source VDD. The transistor P 28 includes a gate terminal configured to receive the first initialization signal INT 1 , a drain terminal coupled to the second power source voltage VSS, and a source terminal coupled to an other terminal of the capacitor C 7 .

The transistor P 29 includes a gate terminal coupled to the other terminal of the capacitor C 7 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 30 . The transistor P 30 includes a gate terminal coupled to one terminal of the capacitor C 8 and a drain terminal configured to receive the second light emitting clock signal CLK 2 . A contact point of the drain terminal of the transistor P 29 and the source terminal of the transistor P 30 becomes an output terminal of the second scan signal SS 2 . One terminal of the capacitor C 8 is coupled to the gate terminal of the transistor P 30 , and the other terminal thereof is coupled to the source terminal of the transistor P 30 .

FIG. 6 is a waveform diagram illustrating an operation of the scan driver 200 that is shown in FIG. 1 . FIG. 6 is described in relation to a detailed circuit diagram of the scan driver 200 that is shown in FIG. 5 . In FIG. 6 , a segment T 1 and a segment T 3 each represent a cycle of the first initialization signal INT 1 , and a segment T 2 and a segment T 4 each represent a cycle of the second initialization signal INT 2 .

Referring to FIG. 6 , at a time point A 1 , when the first initialization signal INT 1 is generated in a low level, the transistor P 4 is turned on. Accordingly, as the transistor P 5 is turned on by the second power source voltage VSS, the first sequential driving signal G 1 is generated as the first power source voltage VDD level.

Next, at a time point A 2 , when the synchronization signal FLM is generated as a pulse of a low level, the first light emitting clock signal CLK 1 is generated in a low level. Accordingly, the transistor P 2 is turned on, and the transistor P 6 is turned on by the synchronization signal FLM. Accordingly, the second light emitting clock signal CLK 2 is generated as the first sequential driving signal G 1 . The first sequential driving signal G 1 is generated as the second light emitting clock signal CLK 2 for a segment T 1 , i.e., a cycle of the first initialization signal INT 1 .

At a time point A 3 , when the second initialization signal INT 2 is generated in a low level, the transistor P 10 is turned on. As the transistor P 11 is turned on by the second power source voltage VSS, the second sequential driving signal G 2 is generated as the first power source voltage VDD level.

Next, at a time point A 4 , the transistor P 8 is turned on by the second light emitting clock signal CLK 2 and the transistor P 12 is turned on by the first sequential driving signal G 1 . Accordingly, the first light emitting clock signal CLK 1 is generated as the second sequential driving signal G 2 . The second sequential driving signal G 2 is generated as the first light emitting clock signal CLK 1 for a segment T 2 , i.e., a cycle of the second initialization signal INT 2 . In this way, the sequential driving signals G 1 -Gn are sequentially output.

For the segment T 1 and the segment T 2 , because the inverted area selection signal PTB is in a low level, the transistor P 18 and the transistor P 27 are turned on. Accordingly, as the transistor P 20 and the transistor P 29 are turned on by the second power source voltage VSS, first and second scan signals SS 1 and SS 2 are generated in the first power source voltage VDD level. In this way, a first scan signal SS 3 is generated in the first power source voltage VDD level.

In this state, at a time point A 5 , when the area selection signal PTA becomes a low level, the transistor P 23 is turned on. The transistor P 25 is turned on by the first light emitting clock signal CLK 1 . Accordingly, as the transistor P 30 is turned on by a second sequential driving signal G 4 , the second light emitting clock signal CLK 2 is outputted as a second scan signal SS 4 for a segment T 3 .

Likewise, at a time point A 6 , while the area selection signal PTA remains in the low level (and transistor P 14 is turned on), the transistor P 16 is turned on by the second light emitting clock signal CLK 2 . Accordingly, as the transistor P 21 is turned on by a first sequential driving signal G 5 , the first light emitting clock signal CLK 1 is generated as a first scan signal SS 5 for a segment T 4 . Continuing in this fashion, for segments in which the area selection signal PTA is in the low level, scan signals SS 4 -SS 8 are sequentially generated.

Therefore, as the scan signal is transferred to only the scan lines S 4 -S 8 corresponding to the display area DA, only the corresponding pixels PX emit light. Further, as the data driver 300 transfers data voltages corresponding to valid data VD to the plurality of data lines D 1 -Dm only for a segment in which the area selection signal PTA is in a low level, power consumption can be reduced. The display area DA and the non-display area NDA can be arbitrarily selected and driven by the area selection signal PTA.

FIG. 7 is a detailed circuit diagram illustrating another configuration of the scan driver 200 that is shown in FIG. 1 . FIG. 7 illustrates another configuration of first and second sequential drivers 210 ′_ 1 and 210 ′_ 2 and first and second output selection portions 220 ′_ 1 and 220 ′_ 2 . For better understanding and ease of description, FIG. 7 illustrates only the first and second sequential drivers 210 ′_ 1 and 210 ′_ 2 and the first and second output selection portions 220 ′_ 1 and 220 ′_ 2 , but the circuit configuration of the remaining sequential drivers and output selection portions is substantially identical to that of the first and second sequential drivers 210 ′_ 1 and 210 ′_ 2 and the first and second output selection portions 220 ′_ 1 and 220 ′_ 2 .

Referring to FIG. 7 , the first sequential driver 210 ′_ 1 includes a plurality of transistors P 31 -P 36 and a plurality of capacitors C 9 and C 10 . Here, the plurality of transistors P 31 -P 36 are formed as P-mos transistors.

The transistor P 31 includes a gate terminal configured to receive a synchronization signal FLM and a source terminal coupled to a first power source VDD. The transistor P 32 includes a drain terminal coupled to the gate terminal of the transistor P 31 and configured to receive the synchronization signal FLM, a gate terminal configured to receive the first light emitting clock signal CLK 1 , and a source terminal.

The transistor P 33 includes a gate terminal coupled to a drain terminal of the transistor P 31 , a drain terminal coupled to the source terminal of the transistor P 32 , and a source terminal coupled to the first power source VDD. The source terminal of the transistor P 32 and the drain terminal of the transistor P 33 are coupled to a gate terminal of the transistor P 36 . When the transistor P 32 is electrically connected by the first clock signal CLK 1 , if the synchronization signal FLM is in a low level, the transistor P 36 is electrically connected. When the transistor P 33 is electrically connected, the transistor P 36 is turned off by the first power source voltage VDD.

One terminal of the capacitor C 9 is coupled to the first power source VDD. The transistor P 34 includes a gate terminal configured to receive a first initialization signal INT 1 , a drain terminal coupled to a second power source VSS, and a source terminal coupled to an other terminal of the capacitor C 9 . The transistor P 35 includes a gate terminal coupled to the source terminal of the transistor P 34 and the other terminal of the capacitor C 9 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 36 .

The transistor P 36 includes a gate terminal coupled to one terminal of the capacitor C 10 and a drain terminal configured to receive the second light emitting clock signal CLK 2 . An other terminal of the capacitor C 10 is coupled to the source terminal of the transistor P 36 . A contact point of the drain terminal of the transistor P 35 and the source terminal of the transistor P 36 becomes an output terminal of a first sequential driving signal G 1 .

The second sequential driver 210 ′_ 2 includes a plurality of transistors P 37 -P 42 and a plurality of capacitors C 11 and C 12 . Here, the plurality of transistors P 37 -P 42 are formed as P-mos transistors.

The transistor P 37 includes a gate terminal configured to receive the first sequential driving signal G 1 and a source terminal coupled to the first power source VDD. The transistor P 38 includes a drain terminal coupled to the gate terminal of the transistor P 37 and configured to receive the first sequential driving signal G 1 , a gate terminal configured to receive the second light emitting clock signal CLK 2 , and a source terminal.

The transistor P 39 includes a gate terminal coupled to a drain terminal of the transistor P 37 , a drain terminal coupled to the source terminal of the transistor P 38 , and a source terminal coupled to the first power source voltage VDD. The source terminal of the transistor P 38 and the drain terminal of the transistor P 39 are coupled to a gate terminal of the transistor P 42 . When the transistor P 38 is electrically connected by the second clock signal CLK 2 , if the synchronization signal FLM is in the low level, the transistor P 42 is electrically connected. When the transistor P 39 is electrically connected, the transistor P 42 is turned off by the first power source voltage VDD.

One terminal of the capacitor C 11 is coupled to the first power source VDD. The transistor P 40 includes a gate terminal configured to receive a second initialization voltage INT 2 , a drain terminal coupled to the second power source VSS, and a source terminal coupled to an other terminal of the capacitor C 11 . The transistor P 41 includes a gate terminal coupled to the source terminal of the transistor P 40 and the other terminal of the capacitor C 11 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 42 .

The transistor P 42 includes a gate terminal coupled to one terminal of the capacitor C 12 and a drain terminal configured to receive the first light emitting clock signal CLK 1 . An other terminal of the capacitor C 12 is coupled to the source terminal of the transistor P 42 . A contact point of the drain terminal of the transistor P 41 and the source terminal of the transistor P 42 becomes an output terminal of a second sequential driving signal G 2 .

The first output selection portion 220 ′_ 1 includes a plurality of transistors P 43 -P 50 and a plurality of capacitors C 13 and C 14 . Here, the plurality of transistors P 43 -P 50 are formed as P-mos transistors.

The transistor P 43 includes a gate terminal configured to receive the first sequential driving signal G 1 , a source terminal coupled to a drain terminal of the transistor P 44 , and a drain terminal coupled to the second power source VSS. The transistor P 44 includes a gate terminal configured to receive an area selection signal PTA and a source terminal coupled to a drain terminal of the transistor P 47 . The transistor P 45 includes a gate terminal configured to receive the first sequential driving signal G 1 and a source terminal coupled to the first power source voltage VDD. The transistor P 46 includes a gate terminal configured to receive an inverted area selection signal PTB, a source terminal coupled to a drain terminal of the transistor P 45 , and a drain terminal coupled to the second power source VSS.

The transistor P 47 includes a gate terminal coupled to the drain terminal of the transistor P 45 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to the source terminal of the transistor P 44 . The transistor P 48 includes a gate terminal configured to receive the second initialization signal INT 2 , a source terminal coupled to the gate terminal of the transistor P 47 , and a drain terminal coupled to the second power source VSS.

One terminal of the capacitor C 13 is coupled to the first power source VDD. The transistor P 49 includes a gate terminal coupled to an other terminal of the capacitor C 13 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to a source terminal of the transistor P 50 . The transistor P 50 includes a gate terminal coupled to the source terminal of the transistor P 44 and a drain terminal configured to receive the first light emitting clock signal CLK 1 is input. A contact point of the drain terminal of the transistor P 49 and the source terminal of the transistor P 50 becomes an output terminal of the first scan signal SS 1 . One terminal of the capacitor C 14 is coupled to the gate terminal of the transistor P 50 , and an other terminal thereof is coupled to the source terminal of the transistor P 50 .

The second output selection portion 220 ′_ 2 includes a plurality of transistors P 51 -P 58 and a plurality of capacitors C 15 and C 16 . Here, the plurality of transistors P 51 -P 58 are formed as P-mos transistors.

The transistor P 51 includes a gate terminal configured to receive the first sequential driving signal G 1 , a source terminal coupled to a drain terminal of the transistor P 52 , and a drain terminal coupled to the second power source voltage VSS. The transistor P 52 includes a gate terminal configured to receive the area selection signal PTA and a source terminal coupled to a drain terminal of the transistor P 55 . The transistor P 53 includes a gate terminal configured to receive the second sequential driving signal G 2 and a source terminal coupled to the first power source voltage VDD. The transistor P 54 includes a gate terminal configured to receive an inverted area selection signal PTB, a source terminal coupled to a drain terminal of the transistor P 53 , and a drain terminal coupled to the second power source VSS.

The transistor P 55 includes a gate terminal coupled to the drain terminal of the transistor P 53 , a source terminal coupled to the first power source VDD, and a drain terminal coupled to the source terminal of the transistor P 52 . The transistor P 56 includes a gate terminal configured to receive the second initialization signal INT 2 , a source terminal coupled to the gate terminal of the transistor P 55 , and a drain terminal coupled to the second power source VSS.

One terminal of the capacitor C 15 is coupled to the first power source VDD. The transistor P 57 includes a gate terminal coupled to an other terminal of the capacitor C 15 , a source terminal coupled to the first power source voltage VDD, and a drain terminal coupled to a source terminal of the transistor P 58 . The transistor P 58 includes a gate terminal coupled to the source terminal of the transistor P 52 and a drain terminal configured to receive the second light emitting clock signal CLK 2 . A contact point of the drain terminal of the transistor P 57 and the source terminal of the transistor P 58 becomes an output terminal of the second scan signal SS 2 . One terminal of the capacitor C 16 is connected to the gate terminal of the transistor P 58 , and an other terminal thereof is connected to the source terminal of the transistor P 58 .

Operation of the scan driver 200 having the above-described configuration is described with reference to FIG. 6 as follows. A configuration that outputs a plurality of sequential driving signals G 1 -Gn is substantially identical to that of an operation description of FIG. 6 and thus a detailed description thereof is not provided again, and a plurality of scan signals SS 1 -SSn will be described hereinafter.

At a time point A 5 , when the area selection signal PTA becomes a low level, the transistor P 52 is turned on. Then, when the second sequential driving signal G 4 becomes a low level, the transistor P 51 is also turned on. Accordingly, the transistor P 58 is turned on by the second power source voltage VSS and thus, the second light emitting clock signal CLK 2 is outputted as a second scan signal SS 4 for a segment T 3 .

Likewise, at a time point A 6 , while the area selection signal maintains the low level (and transistor P 44 is turned on), the transistor P 43 is turned on by a first sequential driving signal G 5 . Accordingly, as the transistor P 50 is turned on by the second power source voltage VSS, the first light emitting clock signal CLK 1 is outputted as a first scan signal SS 5 for a segment T 4 . Continuing in this fashion, for segments in which the area selection signal PTA is in the low level, scan signals SS 4 -SS 8 are sequentially generated.

While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof.