Fixed-frequency control circuit and method for pulse width modulation

The present invention is related generally to pulse width modulation and, more particularly, to fixed-frequency control for pulse width modulation (PWM).

If a PWM power converter uses a non-fixed frequency system architecture, such as a constant on-time or constant off-time control system, the frequency of the PWM power converter may deviate from the designed value under different loading and cause new problems. For example, two channels on a printed circuit board (PCB) are designed to operate with a frequency difference of higher than 100 KHz therebetween, but the real operation frequencies of the two channels may quite close to each other under certain loading, thereby causing audio beating. FIG. 1 is a circuit diagram of the basic architecture for constant on-time and constant off-time PWM, and FIG. 2 is a waveform diagram thereof. Referring to FIGS. 1 and 2 , a comparator 10 compares the output voltage Vout of the system with a reference voltage Vref 1 to generate a comparison signal S 1 , and a PWM signal generator 12 generates a PWM signal S 2 according to the comparison signal S 1 to drive a power output stage 14 to convert an input voltage VIN into the output voltage Vout. In the PWM signal generator 12 , responsive to the comparison signal S 1 , a constant-time trigger 16 triggers a constant on-time Ton or a constant off-time Toff, whose width is set by a current I 1 provided by a current generator 18 . For example, FIG. 3 is a circuit diagram of the constant-time trigger 16 for constant on-time PWM, in which the comparison signal S 1 is used to control a switch SW 3 and thereby determine the time point at which a capacitor C 1 is to be charged, and a comparator 22 compares the capacitor voltage VC 1 with a reference voltage Vref 2 to generate the PWM signal S 2 . Once the comparison signal S 1 triggers a flip-flop 20 to turn off the switch SW 3 , the current I 1 charges the capacitor C 1 and thereby the capacitor voltage VC 1 increases from zero at a constant speed. When the capacitor voltage VC 1 becomes as high as the reference voltage Vref 2 , the PWM signal S 2 turns off the on-time Ton. As the current I 1 is constant, the on-time Ton of the PWM signal S 2 has a fixed width. In the system shown in FIG. 1 , error under different loading mainly comes from three sources:

(1) The variation of the phase node voltage Vp (=VIN−IL×Ron) with the load current IL, where Ron is the on-resistance of the high side power switch SW 1 ; (2) The voltage drop (IL×RL) caused by the inductor L and the parasitic resistance RL of the PCB; and (3) The increased frequency caused by the reduced pulse width of the phase node voltage VP resulted from the shorter deadtime time under heavy loading.

U.S. Pat. No. 6,456,050 uses a timing control circuit to generate a timing signal in response to the duty cycle for constant off-time control; however, a fixed frequency is achievable only when the input/output voltage ratio is less than 0.5. U.S. Pat. No. 6,774,611 uses a phase locked loop (PLL) to control the duty cycle of the PWM signal and thus provide precise frequency control, but the circuit is highly complicated. U.S. Pat. No. 7,508,180 converts the frequency of the PWM signal into a voltage and then compares the voltage with a reference voltage by an error amplifier to produce a differential voltage to adjust the on-time Ton and off-time Toff of the PWM signal and thereby control the frequency of the PWM signal. However, this art does not disclose or teach how to adjust the on-time Ton and off-time Toff of the PWM signal with the differential voltage. Generally, a constant-time trigger controls the width of a constant on-time or constant off-time according to a constant current. Therefore, an additional voltage to current converter will be required to convert the differential voltage into a current, which nevertheless adds to circuit complexity.

Therefore, it is desired a simple fixed-frequency control circuit and method with precise frequency control.

An object of the present invention is to provide a fixed-frequency control circuit for pulse width modulation.

Another object of the present invention is to provide a fixed-frequency control method for pulse width modulation.

According to the present invention, for pulse width modulation using a constant-time trigger to trigger the on-time or off-time of a PWM signal, and a current generator to provide a first current to determine the width of the on-time or off-time, a fixed-frequency control circuit generates an error current according to the frequency of the PWM signal to be combined into the first current to adjust the width of the on-time or off-time and thereby stabilizes the frequency of the PWM signal at a target frequency.

According to the present invention, for pulse width modulation including triggering the on-time or off-time of a PWM signal and determining the width of the on-time or off-time according to a first current, a fixed-frequency control method generates an error current according to the frequency of the PWM signal to be combined into the first current to adjust the width of the on-time or off-time and thereby stabilizes the frequency of the PWM signal at a target frequency.

These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of the basic architecture for constant on-time and constant off-time PWM;

FIG. 2 is a waveform diagram of the circuit shown in FIG. 1 ;

FIG. 3 is a circuit diagram of a constant-time trigger for constant on-time PWM;

FIG. 4 is a circuit diagram of a first embodiment according to the present invention;

FIG. 5 is a circuit diagram of a second embodiment according to the present invention;

FIG. 6 is a circuit diagram of an embodiment for the programmable current source shown in FIG. 5 ;

FIG. 7 is a circuit diagram of a third embodiment according to the present invention; and

FIG. 8 is a diagram showing the curves of frequency to loading in a PWM system.

FIG. 4 is a circuit diagram of a first embodiment according to the present invention, in which the PWM signal generator 12 includes a fixed-frequency control circuit 24 in addition to the constant-time trigger 16 and the current generator 18 . Based on the frequency of the PWM signal S 2 , the fixed-frequency control circuit 24 adjusts the current I 1 ′ supplied to the constant-time trigger 16 and thereby controls the frequency of the PWM signal S 2 . The fixed-frequency control circuit 24 includes an error current generator 26 and an adder 28 . The error current generator 26 generates an error current I 2 according to the frequency of the PWM signal S 2 , and the adder 28 adds the error current I 2 to the first current I 1 to generate the current I 1 ′ supplied to the constant-time trigger 16 . In the error current generator 26 , a frequency to current converter 30 converts the frequency of the PWM signal S 2 into a second current I 3 , a current generator 32 provides a reference current Iref, a subtractor 34 subtracts the second current I 3 from the reference current Iref to generate a differential current Id, and a current amplifier 36 amplifies the differential current Id to generate the error current I 2 . The current amplifier 36 can be implemented by a current mirror. After the first current I 1 is adjusted by the error current I 2 , the constant on-time Ton or constant off-time Toff generated by the constant-time trigger 16 is adjusted, for example as shown in FIG. 3 , such that the frequency of the PWM signal S 2 is stabilized at a target frequency determined by the reference current Iref. Thus, by adjusting the reference current Iref, the frequency of the PWM signal S 2 can be precisely adjusted. Furthermore, as the error current generator 26 generates the error current I 2 directly from the frequency of the PWM signal S 2 , only a simple circuit is needed for the task.

In a second embodiment as shown in FIG. 5 , the error current generator 26 is implemented by a digital circuit, in which a clock generator 38 provides a clock signal clk having a fixed frequency, an up/down counter 40 calculates the frequency difference between the PWM signal S 2 and the clock signal clk to generate a count CNT, and a programmable current source 42 determines the error current I 2 according to the count CNT. The error current generator 26 may either supply the error current I 2 to the adder 28 or draw the error current I 2 from the adder 28 , so as to adjust the current I 1 ′ supplied to the constant-time trigger 16 to stabilize the frequency of the PWM signal S 2 at the frequency of the clock signal clk. Since the error current generator 26 generates the error current I 2 directly from the frequency of the PWM signal S 2 , the circuit is simpler.

FIG. 6 is a circuit diagram of an embodiment for the programmable current source 42 shown in FIG. 5 , which includes parallel-connected current sources IB 0 , IB 1 and IB 2 as well as switches SWB 0 , SWB 1 and SWB 2 serially connected to the current sources IB 0 , IB 1 and IB 2 respectively. The count CNT includes bits B 0 , B 1 and B 2 for controlling the switches SWB 0 , SWB 1 and SWB 2 respectively. Thus, the count CNT determines the configuration of the switches SWB 0 , SWB 1 and SWB 2 and thereby determines the current sources that will output jointly. In consequence, the count CNT determines the error current I 2 . For example, if the count CNT is “101”, the switches SWB 0 and SWB 2 will be closed, and the switch SWB 1 opened; as a result, the error current I 2 equals to IB 0 +IB 2 . If the count CNT is “110”, the switches SWB 1 and SWB 2 will be closed, and the switch SWB 0 opened, thus generating an error current I 2 equal to IB 1 +IB 2 . The error currents I 2 corresponding to other bit combinations of the count CNT can be deduced by analogy.

FIG. 7 is a circuit diagram of a third embodiment for the fixed-frequency control circuit 24 , in which the error current generator 26 includes a clock generator 38 to provide a clock signal clk having a fixed frequency, a one shot generator 44 triggered by the clock signal clk to generate a pulse signal SP 1 , a current mirror 46 responsive to the pulse signal SP 1 to generate a reference current Iref related to the frequency of the clock signal clk, a one shot generator 48 triggered by the PWM signal S 2 to generate a pulse signal SP 2 , and a current mirror 50 responsive to the pulse signal SP 2 to generate a current I 3 related to the frequency of the PWM signal S 2 , and the outputs of the current mirrors 46 and 50 are connected to an input 52 of the adder 28 for the adder 28 to add the differential current I 2 between the reference current Iref and the second current I 3 to the first current I 1 to generate the current I 1 ′. In the current mirror 46 , a transistor M 1 has a drain and a gate connected to each other and connected to a current source IO via a switch SW 4 controlled by the pulse signal SP 1 , a low-pass filter 54 is coupled between the gate of the transistor M 1 and the gate of a transistor M 2 having a drain connected to the input 52 of the adder 28 , the sources of the transistors M 1 and M 2 are both connected to a power supply, and the transistor M 2 mirrors the current of the transistor M 1 to generate the reference current Iref. In the current mirror 50 , a transistor M 3 has a drain and a gate connected to each other and connected to a current source IO via a switch SW 5 controlled by the pulse signal SP 2 , a low-pass filter 56 is coupled between the gate of the transistor M 3 and the gate of a transistor M 4 having a drain connected to the input 52 of the adder 28 , the sources of the transistors M 3 and M 4 are both grounded, and the transistor M 4 mirrors the current of the transistor M 3 to generate the second current I 3 .

FIG. 8 is a diagram showing two curves describing the relationship between the frequency of the PWM signal S 2 and the load current IL. As shown by the curve 58 , there is a nonlinear relationship between the frequency and load current IL of a conventional constant on-time PWM power converter. However, after adjusted by the fixed-frequency control circuit 26 of the present invention, the frequency of the PWM signal S 2 is substantially kept at a constant value, as shown by the curve 60 .

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.