Systems and methods for cancelling interferers in a receiver

This application claims the benefit of U.S. Provisional Patent Application No. 61/259,183, filed Nov. 8, 2009, which is hereby incorporated by reference herein in its entirety.

The disclosed subject matter relates to systems and methods for cancelling interferers in a receiver.

With recent technology scaling, the supply voltages on which circuits operate has continued to drop and supply voltages of 0.5-0.7 volts are foreseen for future highly scaled CMOS technologies. Like other areas of technology, wireless communication receivers (e.g., for mobile communications such as mobile telephones) will need to be capable of operating on such low supply voltages while maintaining low-noise-figure and high-linearity characteristics.

Systems and methods for cancelling interferers in a receiver are provided. In some embodiments, systems for cancelling interferers in a receiver are provided, the systems comprising: a first mixer in a main path that downconverts a first RF signal to form a main baseband or intermediate-frequency signal; and a second mixer in an alternate path that downconverts a second RF signal to form an alternate baseband or intermediate-frequency signal, wherein the first RF signal and the second RF signal are both based on a third RF signal, and wherein the main baseband or intermediate-frequency signal and the alternate baseband or intermediate-frequency signal, when combined, cancel out an interferer in the third RF signal.

In some embodiments, methods for cancelling interferers in a receiver are provided, the methods comprising: downconverting a first RF signal to form a main baseband or intermediate-frequency signal; and downconverting a second RF signal to form an alternate baseband or intermediate-frequency signal, wherein the first RF signal and the second RF signal are both based on a third RF signal, and wherein the main baseband or intermediate-frequency signal and the alternate baseband or intermediate-frequency signal, when combined, cancel out an interferer in the third RF signal.

In some embodiments, methods for cancelling interferers in a receiver are provided, the methods comprising: a) providing a radio frequency test tone to a main path and an alternate path in a receiver; b) enabling the main path and disabling the alternate path and then measuring a downconverted signal amplitude produced at the output of the main path; c) enabling the alternate path and disabling the main path and then measuring a downconverted signal amplitude produced at the output of the alternate path; d) adjusting a gain setting in at least one of the main path and the alternate path to match the downconverted signal amplitude of the main path and the downconverted signal amplitude of the alternate path; e) enabling the main path and the alternate path and then measuring a signal power produced at a combined output of the main path and the alternate path; and f) adjusting a phase control setting in at least one of the main path and the alternate path to minimize the signal power produced at the combined output.

In some embodiments, systems for cancelling interferers in a receiver are provided, the systems comprising: at least one hardware processor that: a) provides a radio frequency test tone to a main path and an alternate path in a receiver; b) enables the main path and disables the alternate path and then measures a downconverted signal amplitude produced at the output of the main path; c) enables the alternate path and disables the main path and then measures a downconverted signal amplitude produced at the output of the alternate path; d) adjusts a gain setting in at least one of the main path and the alternate path to match the downconverted signal amplitude of the main path and the downconverted signal amplitude of the alternate path; e) enables the main path and the alternate path and then measures a signal power produced at a combined output of the main path and the alternate path; and f) adjusts a phase control setting in at least one of the main path and the alternate path to minimize the signal power produced at the combined output.

In some embodiments, computer-readable media containing computer-executable instructions that, when executed by a processor, cause the processor to perform a method for cancelling interferers in a receiver are provided, the method comprising: a) providing a radio frequency test tone to a main path and an alternate path in a receiver; b) enabling the main path and disabling the alternate path and then measuring a downconverted signal amplitude produced at the output of the main path; c) enabling the alternate path and disabling the main path and then measuring a downconverted signal amplitude produced at the output of the alternate path; d) adjusting a gain setting in at least one of the main path and the alternate path to match the downconverted signal amplitude of the main path and the downconverted signal amplitude of the alternate path; e) enabling the main path and the alternate path and then measuring a signal power produced at a combined output of the main path and the alternate path; and f) adjusting a phase control setting in at least one of the main path and the alternate path to minimize the signal power produced at the combined output.

FIG. 1 is a diagram of an example receiver in accordance with some embodiments.

FIG. 2 is a diagram showing further details of an example low noise amplifier, and an example buffer and an example mixer of a main path, of an example receiver in accordance with some embodiments.

FIG. 3 is a diagram showing further details of an example baseband transimpedance amplifier and an example baseband filter of an example receiver in accordance with some embodiments.

FIG. 4 is a diagram showing further details of an example buffer, an example programmable gain amplifier, and an example high pass filter of an alternate path of an example receiver in accordance with some embodiments.

FIG. 5 is a diagram of an example local oscillator buffer, an example polyphase filter, and example buffers of an example receiver in accordance with some embodiments.

FIG. 6 is a diagram of an example amplifier of an example local oscillator buffer of an example receiver in accordance with some embodiments.

FIG. 7 is a diagram of an example phase shifter of an example receiver in accordance with some embodiments.

FIG. 8 is a diagram of an example calibration scheme for an example receiver in accordance with some embodiments.

In accordance with some embodiments, systems and methods for cancelling interferers in a receiver are provided. These mechanisms, in some embodiments, include a receiver architecture that uses two paths for processing a received RF signal. After the RF signal is received and amplifier by a low noise amplifier (LNA), the signal is coupled to a main path and alternate path with different noise and/or linearity characteristics. In the main path, the signal is then buffered and mixed with a local oscillator. In the alternate path, the signal is then buffered, mixed with a phase-shifted local oscillator, amplified by a programmable gain amplifier, and filtered by a high pass filter. The resultant signals from the main path and the alternate path are then combined. Because of the different noise and/or linearity characteristics, combining these resultant signals can cause interferers to be cancelled out when the gain and the phase of the two paths are matched. These mechanisms, in some embodiments, also include a process or scheme for matching the gain and the phase of the two paths.

FIG. 1 shows an example block diagram of a direct conversion receiver 100 in accordance with some embodiments. In some embodiments, this receiver can operate off of a 0.6 V supply voltage. The receiver can include a radio frequency (RF) input section 125 , a local oscillator (LO) input section 140 , a LO buffer 142 , a polyphase filter 144 , a buffer 145 , a serial interface 146 , a low noise amplifier (LNA) 101 and two forward paths for each of an I-signal path 102 and a Q-signal path 104 : a main signal path 106 ; and an alternate path 108 with different noise and/or linearity characteristics.

RF input section 125 can include an antenna 128 , a balun 126 , capacitors 130 , and gate inductors L G 132 . Balun 126 can be used to perform single-ended to differential conversion of an RF input signal from antenna 128 in some embodiments. Capacitors 130 and gate inductors L G 132 in combination with the transistors of LNA 101 can provide an impedance match to balun 126 and antenna 128 (e.g., which can have a 50Ω impedance). Gate inductors L G 132 can be realized in some embodiments using a combination of a high Q bond wire inductance with a discrete inductor.

Local oscillator input section 140 can include a balun for performing single-ended to differential conversion of a local oscillator input signal from any suitable local oscillator source (e.g., such as a 900 MHz local oscillator) in some embodiments. LO buffer 142 can be used to buffer the local oscillator signal. Polyphase filter 144 can be used to produce a quadrature LO signal. Serial interface 146 can be used to receive control signals in serial form and provide those signals in non-serial form to other components of the receiver, and can be implemented in any suitable manner.

LNA 101 can be any suitable low noise amplifier for amplifying an RF input signal and providing it to I-signal path 102 and Q-signal path 104 in some embodiments 4.

In each of I-signal path 102 and Q-signal path 104 , the main signal path can include RF buffers 110 , a passive mixer 112 , a variable gain baseband transimpedance amplifier (TIA) 114 , and a second order low pass filter 116 with a cutoff frequency of 100 kHz in some embodiments.

The performance of these blocks in the main signal paths can be as summarized in the following table in some embodiments:

Gain/ Noise Figure/ Transconductance/ Integrated Block Transimpedance Output Noise IIP3 LNA 22 dB 3 dB −3 dBm Mixer 1.26 mS 1.52 nV RMS 3 dBV TIA 10 kΩ 38 μV RMS −60 dBA LPF 14 dB 50 μV RMS 5 dBV

In some embodiments, with these blocks alone, the receiver can achieve a cumulative gain of 58 dB, an overall dual side band noise figure (DSB NF) of 5.1 dB, but a third order input intercept point (IIP3) of only −29 dBm. The high gain required in the front-end to achieve a low noise figure can cause the IIP3 of the receiver main paths to be limited by the linearity of the baseband circuits TIA 114 and filter 116 . This is because the third order intermodulation product (IM3) can be high enough to swamp the signal at the output of low pass filter 116 .

To overcome the linearity bottleneck caused by these baseband circuits, out-of-channel interferers can be attenuated before reaching the baseband circuits in some embodiments. By applying a 20 dB rejection for in-band blockers before the baseband TIA via alternate signal paths 108 , the IM3 products can be brought below the noise floor and the receiver performance can therefore not be limited by the non-linearity of the baseband circuits, and the overall IIP3 of the receiver can be −12 dBm.

Alternate signal paths 108 in each of I and Q signal paths 102 and 104 can include an RF buffer 118 , a passive downconversion mixer 120 , a programmable gain amplifier (PGA) 122 , and a high pass filter 124 in some embodiments. For out-of-channel signals, the baseband output of the alternate paths can be of equal magnitude, but opposite phase, to the baseband output of the main paths, resulting in signal cancellation before entering the TIA. High-pass filter 124 can help minimize the extent to which the in-channel signal is affected by the alternate path. This feed-forward interference cancellation can effectively place a notch in the receiver gain at the desired out-of-channel-blocker frequency.

Achieving accurate gain and phase relationships for the signals from the two paths can be difficult under process or environmental changes. Therefore calibration of these gain and phase relationships can be performed, e.g., as described below, in some embodiments. By controlling these gain and phase relationships for different offset frequencies, it may be possible to program the cancellation to work for a wide variety of out-of-channel signals.

Turning to FIG. 2 , further details of an LNA 201 , a buffer 210 , and a passive mixer 212 that can be used for LNA 101 , buffer 110 , and passive mixer 112 of FIG. 1 , respectively, in some embodiments, are shown.

LNA 201 can be a pseudo-differential, inductively degenerated, cascoded common source amplifier with tuned load. A pseudo-differential LNA can be preferable over a fully differential LNA in some embodiments because it can have a stack of only two transistors (instead of three, for example) thus requiring a smaller saturation voltage (here about 250 mV, for example) and offering higher output swings. As shown, LNA 201 can include input transistors 240 and 242 , cascode transistors 244 and 246 , high/low gain switch 248 , inductors L S 252 , and tank 250 formed from inductor L D 254 and capacitors C D 256 .

A forward body bias of 600 mV (or any other suitable value) can be applied to both input transistors 240 and 242 and cascode transistors 244 and 246 to reduce their V T . The tuned output load provided by tank 250 and inductor 252 can allow for a single-ended swing of up to 700 mVpp (or any other suitable value) in some embodiments. This tuned load can be tuned by a TUNE LNA signal 257 that can be provided by serial interface 146 in some embodiments.

In simulation in some embodiments, the LNA can achieve a gain of 22 dB, a noise factor (NF) of 3 dB, and an IIP3 of −3 dBm, and consume 8 mA from a 0.6 V supply. The LNA can further have a low gain mode when switch M 5 248 is turned ON; the switch then provides a low shunt impedance (R ON ≈55Ω, for example) for tank 250 , thus lowering the Q of the tuned load, and thereby reducing the LNA gain.

In some embodiments, in order to achieve high gain and low-voltage operation, voltage-to-current conversion and current commutation (driven by a local oscillator (LO)) in the signal paths can be kept separate. As shown in FIG. 1 , this can be achieved in some embodiments by performing the voltage-to-current conversion in a transconductor with a tuned load in buffer 110 and the current commutation in a passive mixer 112 . Separate transconductors can be used in some embodiments in the I and Q paths 102 and 104 to isolate the output of LNA 101 from the passive mixers 112 so that 50%-duty-cycle, quadrature LOs can be used without gain degradation of the LNA output.

As mentioned above, in some embodiments, buffer 110 and passive mixer 112 can be provided by buffer 210 and passive mixer 212 as shown in FIG. 2 . As illustrated, buffer 210 can include coupling capacitors C C 258 , input transistors M 6 260 and M 7 262 , inductor L MX 264 , and capacitors C MX 266 in some embodiments. Inductor L MX 264 and capacitors C MX 266 can provide a tuned load for buffer 212 . This tuned load can be tuned using TUNE MX signal 267 that can be provided by serial interface 146 of FIG. 1 in some embodiments.

As also shown in FIG. 2 , passive mixer 212 can include coupling capacitors 268 , and switches M 8 270 , M 9 272 , M 10 274 , and M 11 276 . In some embodiment, passive mixer 212 can be configured to have a high LO swing in order to be more effective as a current commutator. The OFF/ON resistance ratio, R OFF /R ON , of switches 270 , 272 , 274 , and 276 in the passive mixer can be used to determine the conversion gain degradation, L, of the passive mixer compared to an ideal mixer based on the following:

L = 20 * log ⁡ ( R OFF R ON - 1 R OFF R ON + 1 )

To keep the degradation, L, lower than 0.1 dB, an R OFF /R ON ratio of at least 200 can be used in some embodiments. To reduce the ON resistance of switches 270 , 272 , 274 , and 276 for the limited available LO swing at low voltages, nMOS switches can be used in some embodiments. The gates of these switches can be DC biased at 400 mV (or any other suitable voltage) and capacitively coupled to a 375 mV pp,se LO signal (or any other suitable LO signal). The source and drain of the switches can be DC biased at 100 mV (or any other suitable voltage), and a forward body bias of 600 mV (or any other suitable voltage) can be applied to reduce the V T and the R ON of the switches in some embodiments. In simulation, the nominal R ON can be 125Ω (or any other suitable value) and the R OFF can be 110 kΩ (or any other suitable value). As shown in FIG. 2 , the downconverted signal current from passive mixer goes into the virtual ground of the baseband TIA 114 . This can be used to avoid signal swing across switches 270 , 272 , 274 , and 276 , thus keeping passive mixer 212 very linear. In order to bias the source and drain of switches 270 , 272 , 274 , and 276 of mixer 212 at 100 mV (or any other suitable value), the input common-mode of the TIA can be set to 100 mV (or any other suitable value).

Turning to FIG. 3 , further details of a TIA 314 and a filter 316 that can be used for TIA 114 and filter 116 of FIG. 1 , respectively, in some embodiments, are shown.

As illustrated, TIA 314 can include an operational transconductance amplifier 344 , capacitors C 1 340 , feedback resistors R FB 342 , and level-shifting resistors R LS 350 .

In some embodiments, TIA 314 can have two gain settings controlled by feedback resistor R FB 342 . In some embodiments, the output common-mode, V O,CM , of TIA 314 can be set to 300 mV for maximal output swing, whereas the input common-mode, V I,CM , of TIA 314 can be set to 100 mV for improved mixer switch biasing. Level-shifting resistors R LS 350 connected to ground can be used to control the input common-mode of TIA 314 , and the value of R LS can be scaled in tandem with the gain setting of the TIA according to the following equation:

R LS =R FB V I,CM /( V O,CM −V I,CM ).

Channel-select filtration can be performed in both TIA 314 and filter 316 in some embodiments. To keep the noise contribution from channel-select filtration low, the TIA gain can be set to a high value of 80 dBΩ (or any other suitable value) in some embodiments. Using C 1 340 and R FB 342 , a first order filter can be implemented in the TIA with a cut-off frequency of 3 MHz to filter out far-out blockers in some embodiments.

A second order active-RC bi-quad filter with a 100 kHz low-pass Butterworth response can be implemented in filter 316 in some embodiments. As illustrated in FIG. 3 , this filter can be formed from switched resistor banks R 1 354 , capacitors C 2 360 , resistors R 2 362 , operational transconductance amplifier 364 , resistors R 3 366 , capacitors C 3 376 , and operational transconductance amplifier 378 in some embodiments. The second order filter can provide an attenuation of 30 dB at 600 kHz in some embodiments. A 14 dB variable gain can be implemented in the filter with switched resistor banks R 1 354 at the input of the filter.

The values of resistors R LS 350 , resistors R FB 342 , resistors R 1 354 , capacitors C 2 360 , and capacitors C 3 376 can be controlled by one or more signals from serial interface 146 of FIG. 1 in some embodiments.

Turning to FIG. 4 , further details of a buffer 418 , a mixer 420 , a programmable gain amplifier 422 , and a high pass filter 424 that can be used for buffer 118 , mixer 120 , programmable gain amplifier 122 , and high pass filter 124 of alternate signal path 408 in accordance with some embodiments are shown.

As illustrated, buffer 418 can include coupling capacitors C C 440 , signal transistors M 1 442 and M 2 444 , and bias transistors M 3 446 and M 4 448 in some embodiments.

Mixer 420 can be a current-driven passive mixer (e.g., such as passive mixer 212 described herein in connection with FIG. 2 ) in some embodiments.

Programmable gain amplifier (PGA) 422 can include a transimpedance amplifier (TIA) 450 , resistors R 1 452 and R 2 454 , a feedback amplifier 456 , and resistors R 3 458 . TIA 450 can have three gain settings (with relative values of 0 dB, 6 dB and 9 dB), which can be controlled by serial interface 146 , in some embodiments. This TIA can provide low impedance at the output of the mixer. Fine gain control in the PGA can be realized using feedback amplifier 456 and discretely switched resistors R 2 454 . A combined gain range of 20 dB can be achieved in PGA 422 with a gain step of less than 1 dB using TIA 450 and feedback amplifier 456 .

The high pass filter at the end of the alternate path can be used to block noise or intermodulation products from corrupting the in-channel path. High pass filter 424 can include a series combination of resistors R 4 460 and capacitors C 4 462 , with values of 5 k ohms and 100 pF (or any other suitable values) in some embodiments. In some embodiments, capacitors 462 can be made tunable to adjust the cut-off frequency of the high pass filter from 200 kHz-450 kHz to account for process variations. A 10 dB attenuation up to 100 kHz can be achieved using high-pass filter 424 with a 3 dB cut-off frequency of 300 kHz in some embodiments. Filter 424 can pass the first in-band blocker at a 600 kHz offset from the desired channel with less than 1 dB of attenuation and can attenuate the desired channel in the alternate path by 10 dB in some embodiments.

The values of resistors R 1 452 , resistors R 2 454 , and capacitors 462 can be controlled by one or more signals from serial interface 146 in some embodiments.

Turning back to FIG. 1 , it can be seen that a local oscillator signal can be provided to each of the mixers in the main and alternate paths by LO buffer 142 , polyphase filter 144 , LO phase shifter 148 , buffer 150 , and buffer 152 in some embodiments. An example of a first order passive polyphase filter 544 that can be used as filter 144 to generate a quadrature 900 MHz LO from a differential LO signal in accordance with some embodiments is shown in FIG. 5 . This filter can be formed from resistors R 2 562 and capacitors C 2 564 , which can have values of 500 ohms and 350 fF (or any other suitable values), in some embodiments.

As also shown in FIG. 5 , buffers 545 , 550 , and 552 (that can be used as buffers 145 , 150 , and 152 , respectively, of FIG. 1 in some embodiments) can be used to amplify the quadrature LO from passive polyphase filter 544 in some embodiments. Buffers 545 , 550 , and 552 can be implemented in some embodiments as a cascade of amplifiers 566 . An example common-source NMOS amplifier 666 with PMOS current source loads that can be used for amplifiers 566 in some embodiments is shown in FIG. 6 . As illustrated, the LO can be capacitively coupled to amplifier 666 at V I and the amplifier can be DC biased using a replica circuit at V B .

As described above, out of channel signals in the main signal path can be cancelled out by signals produced in the alternate signal path in accordance with some embodiments. In order to cancel the out-of-channel signal currents from the main and alternate signal paths at the input to TIA 114 in FIG. 1 , the signals from these two paths need to have the same (or nearly the same) amplitude A but with opposite (or nearly opposite) phase. For an amplitude mismatch ΔA and a phase mismatch of Δφ between the main path and the alternate path out-of-channel signals, the maximum rejection (R) can be given by:

R ≈10 log(Δφ 2 +(Δ A/A ) 2 )

To get an out-of-channel signal rejection higher than 20 dB, the amplitude and phase mismatch between the two paths can be limited to 0.5 dB and 2.5 degrees, respectively, in some embodiments.

To match the amplitudes of the main path and alternate path, the gain of programmable gain amplifier (PGA) 122 can be controlled in some embodiments. In order to match the gains of the main path and alternate path to within 0.5 dB, a programmable gain with a step of 1 dB can be used.

To control the phase shift between the main and alternate paths, a phase shifter 700 can be used in accordance with some embodiments. The phase shifter can be implemented using a Cartesian combiner which takes the I and Q LO that can be generated using the passive polyphase filter ( FIG. 5 ) and combines them with different weights. The different weights for each of the LO inputs can be controlled by changing the voltage of the cascode node (e.g., across 702 and 704 , 704 and 706 , 708 and 710 , or 710 and 712 ) for each branch. For example, in the branch including transistors M 1 714 , M 5 722 , and M 6 724 , the current from M 1 714 will split between M 5 722 and M 6 724 based on the impedance looking in to the sources of these transistors. To the first order, the current will split linearly depending on the cascode bias. The control voltages can be generated using two 6-bit current steering DACs 738 and 740 (based on one or more signals from serial interface 146 of FIG. 1 ) that change the cascode bias from 480 mV to 600 mV (or any other suitable values) in some embodiments. To get a phase shift of θ between one of the inputs (e.g., I LO ) and the output, the DAC voltage can be set such that:

cos ⁡ ( θ ) = V I , DAC V I , DAC 2 + V Q , DAC 2 sin ⁡ ( θ ) = V Q , DAC V I , DAC 2 + V Q , DAC 2

where:

V I,DAC is the output of the DAC generating the cascode voltage from I CW ; and

V Q,DAC is the output of the DAC generating the cascode voltage from Q CW .

The phase shifter output common mode can be set to 400 mV (or any other suitable value) in some embodiments. Because there is a stack of three transistors in each branch, the output swing can be limited to about 200 mVpp for a 0.6 V supply in some embodiments.

Because the phase noise performance of the alternate path may be more relaxed than that in the main path, the phase shifter can be implemented for the LO of the alternate path. The phase shifter can have a resolution better than 5 degrees over a 360 degree range in simulation in some embodiments.

Even assuming a worst-case amplitude mismatch of 0.5 dB from the PGA and a 2.5 degree phase mismatch from the phase shifter, a suppression of 22.6 dB can be achieved for the blockers in some embodiments.

A calibration scheme 800 that can be used to match (or nearly match) the amplitude and phase of the main and alternate paths in accordance with some embodiments is shown in FIG. 8 . This scheme can be operated in one or more hardware processors (e.g., a microprocessor, a microcontroller, a programmable device, etc.) coupled to the receiver (e.g., via serial interface 146 ) in accordance with some embodiments.

As illustrated, after scheme 800 starts at 802 , the scheme selects a channel in which a cancellation notch is desired at 804 . Next, at 806 , an RF test tone is applied to the receiver at the frequency where the notch is desired. This RF test tone can be provided by any suitable source. The main signal path is then enabled (and the alternate signal path is disabled) and the power of the test tone at the output of the main signal path is measured at 808 . Next, the alternate signal path is then enabled (and the main signal path is disabled) and the power of the test tone at the output of the alternate signal path is measured at 810 . In some embodiments, an analog to digital converter (ADC) with a resolution greater than 6-bits (e.g., a 12-bit ADC with a 2 Vpp input signal range) can be used to measure the power of the main and alternate signal paths, and the ADC sampling frequency can be set by the maximum offset frequency at which the cancellation notch is to be placed. It is then determined if the power levels at the outputs of the two paths are equal (or within a given tolerance). If not, then gain setting of the PGA is adjusted at 814 and scheme 800 loops back to 810 . Otherwise, scheme 800 next enables both paths and sweeps the LO phase shift in the alternate path until the downconverted test tone power is minimized at the output of the receiver at 816 . The LO phase shift that minimizes the test tone power is next stored at 818 .

Scheme 800 next determines whether all channels have been programmed. If not, scheme 800 loops back to 804 . Otherwise, scheme 800 terminates at 822 .

After a receiver has been calibrated for one or more test tone frequencies, the calibration settings for each frequency can be stored and later used to configure the receiver when an interferer at a corresponding frequency is detected.

In some embodiments, any suitable computer readable media can be used for storing instructions for performing the functions, such as those described in connection with FIG. 8 , described herein. For example, in some embodiments, computer readable media can be transitory or non-transitory. For example, non-transitory computer readable media can include media such as magnetic media (such as hard disks, floppy disks, etc.), optical media (such as compact discs, digital video discs, Blu-ray discs, etc.), semiconductor media (such as flash memory, electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), etc.), any suitable media that is not fleeting or devoid of any semblance of permanence during transmission, and/or any suitable tangible media. As another example, transitory computer readable media can include signals on networks, in wires, conductors, optical fibers, circuits, any suitable media that is fleeting and devoid of any semblance of permanence during transmission, and/or any suitable intangible media.

Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is only limited by the claims which follow. Features of the disclosed embodiments can be combined and rearranged in various ways.