Booster circuit

This is a continuation of PCT International Application PCT/JP2010/003226 filed on May 12, 2010, which claims priority to Japanese Patent Application No. 2009-213077 filed on Sep. 15, 2009. The disclosures of these applications including the specifications, the drawings, and the claims are hereby incorporated by reference in their entirety.

The present disclosure relates to booster circuits.

In recent years, for flash memories, which are a type of non-volatile storage devices, there has been a demand for data read operation and data rewrite operation which are performed with a single power supply voltage or low power supply voltages. To meet the demand, an on-chip booster circuit may be required which supplies a positive or negative boosted voltage when each operation is performed.

The booster circuit is also becoming a key technology to ensure an operating margin of a non-volatile storage device or an analog circuit in a CMOS process.

FIG. 14 shows a configuration of a conventional booster circuit (see, for example, U.S. Pat. No. 7,176,746). The booster circuit 900 performs boosting operation in accordance with two input clock signals CLK 1 and CLK 2 having different phases. Reference characters 901 a - 901 e each indicate a charge transfer cell which transfers charge from the preceding stage to the succeeding stage, and reference characters 902 a - 902 d each indicate a boosting capacitor which boosts the output of a charge transfer cell.

FIG. 15 is a diagram showing details of the charge transfer cells 901 a - 901 e . A reference character 903 indicates a charge transfer transistor. Reference characters 904 and 905 indicate switching transistors provided in each of the charge transfer cells 901 a - 901 e , which switch between the input voltage of a charge transfer cell in the preceding stage and the output voltage of the each charge transfer cell, depending on an input to the each charge transfer cell.

Next, operation of the booster circuit 900 of FIG. 14 will be briefly described with reference to FIG. 16 .

Initially, at time T 1 , the clock signal CLK 1 transitions from low to high, so that the voltages of the boosting capacitors 902 a and 902 c are boosted. As a result, the voltages of the output terminals OUT of the charge transfer cells 901 a and 901 c are boosted, so that the switching transistors 905 of the charge transfer cells 901 a and 901 c transition to the conductive state, and therefore, the charge transfer transistors 903 are set to the non-conductive state. At the same time, the switching transistors 904 of the charge transfer cells 901 b and 901 d transition to the conductive state, and therefore, the charge transfer transistors 903 transition to the conductive state. By the aforementioned operation, charge on the output terminals having the boosted voltages of the charge transfer cells 901 a and 901 c is transferred to the output terminals of the charge transfer cells 901 b and 901 d.

At time T 2 (a period of time Ttrans after time T 1 ), the clock signal CLK 2 transitions from low to high, so that the voltages of the boosting capacitors 902 b and 902 d are boosted. As a result, the voltages of the output terminals OUT of the charge transfer cells 901 b and 901 d are boosted, so that the switching transistors 905 of the charge transfer cells 901 b and 901 d transition to the conductive state, and therefore, the charge transfer transistors 903 are set to the non-conductive state. At the same time, the switching transistors 904 of the charge transfer cells 901 c and 901 e transition to the conductive state, and therefore, the charge transfer transistors 903 transition to the conductive state. By the aforementioned operation, charge on the output terminals having the boosted voltages of the charge transfer cells 901 b and 901 d is transferred to the output terminal of the charge transfer cell 901 c and the output terminal of the booster circuit 900 .

Thereafter, at time T 3 , boosting operation similar to that which is performed at time T 1 is repeated.

However, in the conventional booster circuit, after the clock signal transitions from low to high and the voltage of a boosting capacitor is then boosted, the switching transistor in the preceding stage transitions to the conductive state and the charge transfer transistor is set to the non-conductive state. Therefore, immediately after the boosting, boosted charge flows backward to the further preceding stage via the charge transfer transistor, resulting in a decrease in boosting efficiency, which is a problem.

The detailed description describes implementations of a booster circuit with high boosting efficiency which is operated using a two-phase clock and in which a plurality of (M≧4) boosting cell lines constitute a unit.

An example booster circuit includes boosting cells arranged in M parallel lines (M≧4) and L stages (L≧2) and configured to perform boosting operation in synchronization with a plurality of clock signals having different phases. Each of the boosting cells includes a first boosting capacitor having two ends, one of the two ends being connected to an output terminal of the each boosting cell, and a clock signal corresponding to the each boosting cell being received at the other end, a charge transfer transistor connected between an input terminal and the output terminal of the each boosting cell, and a state controller configured to control the charge transfer transistor. The input terminal of one of the boosting cells located in the same stage as that of the each boosting cell and in a first one of the lines other than the line of the each boosting cell, is connected to a control terminal of the state controller, whereby the M boosting cells in the same stage are connected in a ring shape. Therefore, after the charge transfer transistor of the boosting cell is set from the conductive state to the non-conductive state, the boosting cell can perform boosting operation, whereby the backflow of charge via the charge transfer transistor can be reduced or prevented.

As described above, according to the present disclosure, the charge transfer transistor can be set to the non-conductive state during boosting operation without using a complicated clock, whereby the decrease in boosting efficiency can be reduced or prevented.

The charge transfer transistor used in the boosting cell and the backflow preventing cell may be configured using a P-channel transistor. Therefore, in this case, even when a twin-well CMOS process is employed, the substrate bias effect of the charge transfer transistor can be reduced or prevented, and the area of the booster circuit can be reduced by the reduction or prevention of the decrease in boosting efficiency.

A control signal to the boosting cell in the K-th line may be connected to the input terminal of the boosting cell in the A-th preceding line (1≧A≧M/2−1). In this case, an optimum boosting standby state time and a sufficient charge transfer time can be set with respect to the charge transfer transistor.

According to the present disclosure, the control terminals of the state controllers of the boosting cells in the same stage are limited not only by similar connection conditions, but also by predetermined voltage constraints. Therefore, the charge transfer transistor can be set to the non-conductive state during boosting operation without using a complicated clock, whereby the decrease in boosting efficiency can be reduced or prevented.

FIG. 1 is a block diagram showing a configuration of a booster circuit according to a first embodiment of the present disclosure.

FIGS. 2A-2C are circuit diagrams showing configurations of a boosting cell and a backflow preventing cell of FIG. 1 .

FIG. 3 is a waveform diagram for describing operation of the booster circuit of FIG. 1 .

FIGS. 4A-4D are diagrams showing operating modes of the boosting cell for describing operation of the booster circuit of FIG. 1 .

FIG. 5 is a diagram showing operating modes and voltage constraints of the boosting cell of the booster circuit of FIG. 1 .

FIG. 6 is a block diagram showing a configuration of a booster circuit according to a second embodiment of the present disclosure.

FIG. 7 is a block diagram showing a configuration of a booster circuit according to a third embodiment of the present disclosure.

FIG. 8 is a waveform diagram for describing operation of the booster circuits of FIGS. 6 and 7 .

FIG. 9 is a block diagram showing a configuration of a booster circuit according to a fourth embodiment of the present disclosure.

FIG. 10 is a waveform diagram for describing operation of the booster circuit of FIG. 9 .

FIG. 11 is a block diagram showing a configuration of a booster circuit according to a fifth embodiment of the present disclosure.

FIGS. 12A-12C are circuit diagrams showing configurations of a boosting cell and a backflow preventing cell of FIG. 11 .

FIG. 13 is a waveform diagram for describing operation of the booster circuit of FIG. 11 .

FIG. 14 is a circuit diagram showing a configuration of a conventional booster circuit.

FIG. 15 is a circuit diagram showing a detailed configuration of a charge transfer cell of FIG. 14 .

FIG. 16 is a waveform diagram for describing operation of the booster circuit of FIG. 14 .

Embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Like parts are indicated by like reference characters throughout the specification.

First Embodiment

<Configuration>

FIG. 1 shows a configuration of a booster circuit 100 according to a first embodiment of the present disclosure. The booster circuit 100 includes a plurality of boosting cell lines L 01 -L 04 . Boosting cells are also arranged into boosting stages ST 1 -ST 3 and a backflow preventing circuit ST 4 . Of the boosting cell lines L 01 -L 04 , the first boosting stage ST 1 includes boosting cells P 101 -P 104 , the second boosting stage ST 2 includes boosting cells P 201 -P 204 , the third boosting stage ST 3 includes boosting cells P 301 -P 304 , and the backflow preventing circuit ST 4 includes backflow preventing cells P 401 -P 404 . The boosting cells are each operated in synchronization with a clock signal CLK 1 A, CLK 2 A, CLK 1 B, or CLK 2 B, whereby boosting operation is performed.

A plurality of (N=4) signals, i.e., the clock signals CLK 1 A, CLK 2 A, CLK 1 B, and CLK 2 B, have a phase difference of about 360 degrees/N. The clock signal CLK 1 A transitions from low to high, then the clock signal CLK 2 A transitions from low to high, then the clock signal CLK 1 B transitions from low to high, and then finally the clock signal CLK 2 B transitions from low to high. It is preferable that a pair of the clock signals CLK 1 A and CLK 1 B, and a pair of the clock signals CLK 2 A and CLK 2 B, each have a phase difference of about 180 degrees. Although the clock signals CLK 1 A and CLK 1 B are input to the boosting cell lines L 01 and L 03 , a clock signal CLK 3 B corresponding to the clock signal CLK 1 B and a clock signal CLK 3 A corresponding to the clock signal CLK 1 A may be input to the boosting cell line L 03 . Similarly, a clock signal CLK 4 B corresponding to the clock signal CLK 2 B and a clock signal CLK 4 A corresponding to the clock signal CLK 2 A may be input to the boosting cell line L 04 . Reference characters N 001 -N 004 , N 101 -N 104 , N 201 -N 204 , and N 301 -N 304 indicate input/output terminals of the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 . Note that, in FIG. 1 , terminals indicated by the same reference character are connected to each other.

Here, the order of the boosting cell lines will be described. As a representative example, the boosting stage ST 3 will be described. What will be described about the boosting stage ST 3 is also true of the other boosting stages and the backflow preventing circuit.

The order of the boosting cell lines is the order in which the clock signals input to the boosting cells P 301 -P 304 included in the boosting stage ST 3 transition from low to high. Therefore, the boosting cell line L 01 having the boosting cell P 301 which receives the clock signal CLK 1 A is the first line. The boosting cell line L 02 having the boosting cell P 302 which receives the clock signal CLK 2 A which transitions from low to high after the clock signal CLK 1 A has transitioned from low to high is the second line. The boosting cell line L 03 having the boosting cell P 303 which receives the clock signal CLK 1 B which next transitions from low to high is the third line. Similarly, the boosting cell line L 04 in the boosting cell P 304 which receives the clock signal CLK 2 B which next transitions from low to high is the fourth line, which is the final line. This is true of when the number of boosting cell lines is more than four. In this case, the order of the boosting cell lines is also the order in which clock signals input to boosting cells in any boosting stage transition from low to high (the same is true of when the clock signals transition from high to low).

The boosting cells P 101 , P 201 , and P 301 and the backflow preventing cell P 401 in the boosting cell line L 01 are connected in series. The boosting cells P 101 and P 301 in the (2K+1)th stages (K≧0) as counted from the head receive the clock signal CLK 1 A, and the boosting cell P 201 in the (2K+2)th stage as counted from the head receives the clock signal CLK 1 B. The backflow preventing cell P 401 receives the clock signal CLK 1 B, which is the same signal received by the boosting cell P 201 in the stage immediately preceding the final stage in which the boosting cell P 301 is provided.

The boosting cells P 102 , P 202 , and P 302 and the backflow preventing cell P 402 in the boosting cell line L 02 are connected in series. The boosting cells P 102 and P 302 in the (2K+1)th stages (K≧0) as counted from the head receive the clock signal CLK 2 A, and the boosting cell P 202 in the (2K+2)th stage as counted from the head receives the clock signal CLK 2 B. The backflow preventing cell P 402 receives the clock signal CLK 2 B, which is the same signal received by the boosting cell P 202 in the stage immediately preceding the final stage in which the boosting cell P 302 is provided.

The boosting cells P 103 , P 203 , and P 303 and the backflow preventing cell P 403 in the boosting cell line L 03 are connected in series. The boosting cells P 103 and P 303 in the (2K+1)th stages (K≧A) as counted from the head receive the clock signal CLK 1 B, and the boosting cell P 203 in the (2K+2)th stage as counted from the head receives the clock signal CLK 1 A. The backflow preventing cell P 403 receives the clock signal CLK 1 A, which is the same signal received by the boosting cell P 203 in the stage immediately preceding the final stage in which the boosting cell P 303 is provided.

The boosting cells P 104 , P 204 , and P 304 and the backflow preventing cell P 404 in the boosting cell line L 04 are connected in series. The boosting cells P 104 and P 304 in the (2K+1)th stages (K≧0) as counted from the head receive the clock signal CLK 2 B, and the boosting cell P 204 in the (2K+2)th stage as counted from the head receives the clock signal CLK 2 A. The backflow preventing cell P 404 receives the clock signal CLK 2 A, which is the same signal received by the boosting cell P 204 in the stage immediately preceding the final stage in which the boosting cell P 304 is provided.

As a result, the boosting states of the boosting clocks at a predetermined time of the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 , and the backflow preventing cells P 401 -P 404 are indicated by “1” where the boosting cell performs boosting operation or “0” where the boosting cell does not perform boosting operation.

Next, the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 , and the backflow preventing cells P 401 -P 404 included in the boosting stages ST 1 -ST 4 will be described.

Of the boosting cells P 101 -P 104 included in the first boosting stage ST 1 , the boosting cell P 101 in the boosting cell line L 01 receives the clock signal CLK 2 A, which is in antiphase with the clock signal CLK 2 B input to the boosting cell P 104 in the boosting cell line L 04 . The boosting cell P 101 performs boosting operation by switching between the voltage of the input/output terminal N 101 of the boosting cell P 101 and the voltage of the clock signal CLK 1 A input to the boosting cell P 101 , depending on the clock signal CLK 2 A.

Similarly, the boosting cell P 102 in the boosting cell line L 02 receives the clock signal CLK 1 B, which is in antiphase with the clock signal CLK 1 A input to the boosting cell P 101 in the boosting cell line L 01 . The boosting cell P 102 performs boosting operation by switching between the voltage of the input/output terminal N 102 of the boosting cell P 102 and the voltage of the clock signal CLK 2 A input to the boosting cell P 102 , depending on the clock signal CLK 1 B.

The boosting cell P 103 in the boosting cell line L 03 receives the clock signal CLK 2 B, which is in antiphase with the clock signal CLK 2 A input to the boosting cell P 102 in the boosting cell line L 02 . The boosting cell P 103 performs boosting operation by switching between the voltage of the input/output terminal N 103 of the boosting cell P 103 and the voltage of the clock signal CLK 1 B input to the boosting cell P 103 , depending on the clock signal CLK 2 B.

The boosting cell P 104 in the boosting cell line L 04 receives the clock signal CLK 1 A, which is in antiphase with the clock signal CLK 1 B input to the boosting cell P 103 in the boosting cell line L 03 . The boosting cell P 104 performs boosting operation by switching between the voltage of the input/output terminal N 104 of the boosting cell P 104 and the voltage of the clock signal CLK 2 B input to the boosting cell P 104 , depending on the clock signal CLK 1 A.

These mean that, in the first boosting stage ST 1 of the M (M=4) boosting cell lines L 01 -L 04 arranged in parallel, the boosting cell in the K-th line switches between the output terminal voltage of the boosting cell in the K-th line and a clock signal input to the boosting cell in the K-th line, depending on a clock signal which is in antiphase with a clock signal input to the boosting cell in the (K−1)th line (1≦K≦M, (K−1)=M when K=1).

Of the boosting cells P 201 -P 204 included in the second boosting stage ST 2 , the boosting cell P 201 in the boosting cell line L 01 is connected to the input/output terminal N 104 of the boosting cell P 204 in the boosting cell line L 04 . The boosting cell P 201 performs boosting operation by switching between the voltage of the input/output terminal N 201 of the boosting cell P 201 and the voltage of the input/output terminal N 103 of the boosting cell P 203 in the boosting cell line L 03 which is operated with a clock which is in antiphase with the clock of the boosting cell P 201 , depending on the voltage of the input/output terminal N 104 .

Similarly, the boosting cell P 202 in the boosting cell line L 02 is connected to the input/output terminal N 101 of the boosting cell P 201 in the boosting cell line L 01 . The boosting cell P 202 performs boosting operation by switching between the voltage of the input/output terminal N 202 of the boosting cell P 202 and the voltage of the input/output terminal N 104 of the boosting cell P 204 in the boosting cell line L 04 which is operated with a clock which is in antiphase with the clock of the boosting cell P 202 , depending on the voltage of the input/output terminal N 101 .

The boosting cell P 203 in the boosting cell line L 03 is connected to the input/output terminal N 102 of the boosting cell P 202 in the boosting cell line L 02 . The boosting cell P 203 performs boosting operation by switching between the voltage of the input/output terminal N 203 of the boosting cell P 203 and the voltage of the input/output terminal N 101 of the boosting cell P 201 in the boosting cell line L 01 which is operated with a clock which is in antiphase with the clock of the boosting cell P 203 , depending on the voltage of the input/output terminal N 102 .

The boosting cell P 204 in the boosting cell line L 04 is connected to the input/output terminal N 103 of the boosting cell P 203 in the boosting cell line L 03 . The boosting cell P 204 performs boosting operation by switching between the voltage of the input/output terminal N 204 of the boosting cell P 204 and the voltage of the input/output terminal N 102 of the boosting cell P 202 in the boosting cell line L 02 which is operated with a clock which is in antiphase with the clock of the boosting cell P 204 , depending on the voltage of the input/output terminal N 103 .

As described above, in the second boosting stage ST 2 , the boosting cell in the K-th line is connected to the input terminal of the boosting cell in the (K−1)th line (1≦K≦M, (K−1)=M when K=1). The boosting cell in the K-th line performs boosting operation by switching between the output terminal voltage of the boosting cell in the K-th line and the input terminal voltage of a boosting cell which is operated at a phase which is different by about 180 degrees from that of the boosting cell in the K-th line, depending on the voltage of the input terminal of the boot cell in the (K−1)th line.

The third boosting stage ST 3 and the backflow preventing circuit ST 4 are operated in a manner similar to that of the second boosting stage ST 2 .

Note that the number of boosting stages is not limited to three.

<Configuration of Boosting Cell>

FIG. 2A shows a configuration of each of the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 of FIG. 1 . The boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 each include a charge transfer transistor M 1 , an on-switch transistor M 2 , an off-switch transistor M 3 , and a boosting capacitor C 1 . Here, the on-switch transistor M 2 and the off-switch transistor M 3 constitute a state controller for the charge transfer transistor M 1 .

The charge transfer transistor M 1 transfers charge from an input terminal INPUT to an output terminal OUTPUT. The on-switch transistor M 2 supplies the voltage of a source signal SourceN to the gate N 1 of the charge transfer transistor M 1 , depending on the voltage of a control signal Sig, thereby causing the charge transfer transistor M 1 to be in the conductive state. The off-switch transistor M 3 equalizes the voltages of the gate N 1 of the charge transfer transistor M 1 and the output terminal OUTPUT, depending on the voltage of the control signal Sig, thereby causing the charge transfer transistor M 1 to be in the non-conductive state. The boosting capacitor C 1 is pumped in synchronization with one of the clock signals CLK 1 A, CLK 2 A, CLK 1 B, and CLK 2 B input to the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 .

<Backflow Preventing Cell>

FIG. 2B shows a configuration of each of the backflow preventing cells P 401 -P 404 included in the backflow preventing circuit ST 4 of FIG. 1 . The backflow preventing cells P 401 -P 404 each have the configuration of each of the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 of FIG. 2A from which the boosting capacitor C 1 is removed. The charge transfer transistor M 1 , the on-switch transistor M 2 , and the off-switch transistor M 3 are each operated in a manner similar to that of the corresponding one in the boosting cell.

Note that the configuration of the backflow preventing cell of FIG. 2B is only for illustrative purposes. Any other configurations that provide a similar function may be used. For example, as shown in FIG. 2C , the source of the off-switch transistor M 3 may be changed to an intermediate terminal N 2 which is disconnected from the output terminal of the booster circuit 100 . Also, the source of the off-switch transistor M 3 may be connected to the boosting capacitor C 1 whose voltage is boosted using a boosting signal and a diode-connected transistor M 4 connected to the input terminal of the backflow preventing cell. In this case, a function similar to that of FIG. 2B can be obtained. Therefore, the present disclosure is not limited to the configuration of FIG. 2B , and any configuration which provides a function similar to that of the configuration of FIG. 2B may be used.

<Operation>

Next, operation of the booster circuit 100 of FIG. 1 will be described with reference to FIG. 3 . Note that it is assumed that the amplitudes of the clock signals CLK 1 A, CLK 2 A, CLK 1 B, and CLK 2 B each vary between a power supply voltage Vdd and a ground voltage Vss, and the output terminal of the booster circuit 100 has neither a current load nor a voltage limit. In FIG. 3 , VV 1 , VV 2 , and VV 3 are as follows:

( VV 1)= Vdd+α×Vdd

( VV 2)= Vdd+ 2 α×Vdd

( VV 3)= Vdd+ 3 αVdd

As shown in FIGS. 4A-4D , as a representative of the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 , and the backflow preventing cell P 401 -P 404 , the boosting cell P 301 is used to categorize operating modes of the boosting cell and the backflow preventing cell, and clearly show a relationship between and constraints on the voltages of the clock signal CLK, the output terminal OUTPUT of the boosting cell, the control signal Sig, and the source signal SourceN in each operating mode.

[Time T 1 ]

Initially, at time T 1 , the voltage of the source signal SourceN of the on-switch transistor M 2 in each of the boosting cell P 101 in the boosting stage ST 1 and the boosting cell P 301 in the boosting stage ST 3 of the boosting cell line L 01 which perform boosting operation in accordance with the clock signal CLK 1 A is:

( CLK 1 A )= L=Vss

( VN 203)= VV 1

The control signal Sig is:

( CLK 2 A )= L=Vss

( VN 204)= VV 1

The input/output terminals N 101 and N 301 of the boosting cells P 101 and P 301 are set to:

( VN 101)= Vdd

( VN 301)= VV 2

Therefore, in each of the boosting cells P 101 and P 301 , the potential difference between the gate and source of the on-switch transistor M 2 is:

( CLK 2 A )−( CLK 1 A )= Vss−Vss= 0

( VN 204)−( VN 203)= VV 1 −VV 1=0

On the other hand, the potential difference between the gate and source of the off-switch transistor M 3 is:

( CLK 2 A )−( VN 101)= Vss−Vdd=−α×Vdd

( VN 204)−( VN 301)= VV 1 −VV 2 =−α×Vdd

Therefore, the off-switch transistor M 3 is in the conductive state.

Therefore, the voltages VN 1 of the gates N 1 of the charge transfer transistors M 1 of the boosting cells P 101 and P 301 in the boosting cell line L 01 are Vdd and VV 2 , respectively. The potential differences between the gates and sources of the charge transfer transistors M 1 of the boosting cells P 101 and P 301 are:

( VN 1 of P 101)−( VN 101)= Vdd−Vdd= 0

( VN 1 of P 301)−( VN 301)= VV 2 −VV 2=0

Thus, the gate and source of the charge transfer transistor M 1 of each of the boosting cells P 101 and P 301 are set to the same potential, and therefore, the charge transfer transistor M 1 is in the non-conductive state.

Similarly, in each of the boosting cell P 203 in the boosting stage ST 2 of the boosting cell line L 03 which perform boosting operation in synchronization with the clock signal CLK 1 A and the backflow preventing cell P 403 in the backflow preventing circuit ST 4 of the boosting cell line L 03 , the off-switch transistors M 3 is in the conductive state, so that the gate and source of the charge transfer transistor M 1 are set to the same potential, and therefore, the charge transfer transistor M 1 is in the non-conductive state.

[Time T 2 ]

Next, at time T 2 , the clock signal CLK 1 A transition from low to high. As a result, the voltages VN 101 and VN 301 of the input/output terminals N 101 and N 301 of the boosting cell P 101 in the boosting stage ST 1 and the boosting cell P 301 in the boosting stage ST 3 of the boosting cell line L 01 are boosted to:

( VN 101)= VV 1

( VN 301)= VV 3

In this case, it is clear that, because the charge transfer transistors M 1 of the boosting cells P 101 and P 301 have been set to the non-conductive state since time T 1 , the backflow of charge via the charge transfer transistors M 1 does not occur.

The boosting cells P 101 and P 301 perform boosting operation in synchronization with the clock signal CLK 1 A, and at the same time, the clock signal CLK 1 B transitions from high to low, and therefore, the boosting cell P 201 in the boosting stage ST 2 and the backflow preventing cell P 401 in the backflow preventing circuit ST 4 of the boosting cell line L 01 transition to the charge transfer state. The terminal voltages of the boosting cell P 201 and the backflow preventing cell P 401 are as follows.

The source signals SourceN of the boosting cell P 201 and the backflow preventing cell P 401 are:

( VN 103)= Vdd

( VN 303)= VV 2

The control signals Sig of the boosting cell P 201 and the backflow preventing cell P 401 are:

( VN 104)= VV 1

( VN 304)= VV 3

The output voltages of the input/output terminal N 201 of the boosting cell P 201 and the booster circuit 100 are:

( VN 201)= VV 1

( V PUMP)= VV 3

Therefore, the potential differences between the gates and sources of the on-switch transistors M 2 in the boosting cell P 201 and the backflow preventing cell P 401 are:

( VN 104)−( VN 103)= VV 1 −Vdd=α×Vdd

( VN 304)−( VN 303)= VV 3 −VV 2= α×Vdd

On the other hand, the potential differences between the gates and sources of the off-switch transistors M 3 are:

( VN 104)−( VN 201)= VV 1 −VV 1=0

( VN 304)−( V PUMP)= VV 3− VV 3=0

Therefore, the on-switch transistors M 2 transition to the conductive state.

As a result, the voltages VN 1 of the gates N 1 of the charge transfer transistors M 1 in the boosting cells P 201 and the backflow preventing cell P 401 are Vdd and VV 2 , respectively. The potential differences between the gates and sources of the charge transfer transistors M 1 in the boosting cell P 201 and the backflow preventing cell P 401 are:

( VN 1 of P 201)−( VN 201)= Vdd−VV 1 =−α×Vdd

( VN 1 of P 401)−( V PUMP)= VV 2 −VV 3 =−α×Vdd

Therefore, the charge transfer transistors M 1 in the boosting cell P 201 and the backflow preventing cell P 401 transition to the conductive state, i.e., the charge transfer state. As a result, charge on the input/output terminal N 101 whose voltage has been boosted by the boosting cell P 101 in the boosting stage ST 1 is transferred via the boosting cell P 201 in the boosting stage ST 2 to the input/output terminal N 201 . Charge on the input/output terminal N 301 whose voltage has been boosted by the boosting cell P 301 in the boosting stage ST 3 is transferred via the backflow preventing cell P 401 in the backflow preventing circuit ST 4 to the output terminal of the booster circuit 100 , so that the output voltage VPUMP of the booster circuit 100 is increased.

The voltages of the input/output terminals N 101 -N 301 in the boosting stages of the boosting cell line L 01 are also supplied to the corresponding same boosting stages of the boosting cell line L 02 . As a result, the on-switch transistors M 2 of the boosting cells P 102 and P 302 in the boosting cell line L 02 transition to the non-conductive state, and the off-switch transistors M 3 transition to the conductive state. As a result, as in the boosting cells P 101 and P 301 at time T 1 , the charge transfer transistors M 1 of the boosting cells P 102 and P 302 in the boosting cell line L 02 are set to the non-conductive state.

As described above, operation similar to that of the boosting cells P 101 and P 301 in the boosting cell line L 01 at time T 2 is performed in the boosting cell P 203 and the backflow preventing cell P 403 in the boosting cell line L 03 . Briefly, after the charge transfer transistors M 1 of the boosting cell P 203 and the backflow preventing cell P 403 in the boosting cell line L 03 are set to the non-conductive state at time T 1 , the voltage of the input/output terminal N 203 of the boosting cell P 203 is boosted at time T 2 . Charge on the input/output terminal N 203 whose potential has been increased is transferred via the boosting cell P 303 in the succeeding boosting stage ST 3 to the input/output terminal N 303 . Charge on the input/output terminal N 103 of the boosting cell P 203 is input to the boosting cell P 204 in the succeeding boosting cell line L 04 . Similarly, charge on the input/output terminal N 303 of the backflow preventing cell P 403 is input to the backflow preventing cell P 404 in the succeeding boosting cell line L 04 . As a result, the off-switch transistors M 3 of the boosting cell P 204 and the backflow preventing cell P 404 in the boosting cell line L 04 are set to the conductive state, so that the charge transfer transistors M 1 are set to the non-conductive state.

[Time T 3 ]

Next, at time T 3 , the clock signal CLK 2 A transitions from low to high. As a result, the voltages VN 102 and VN 302 of the input/output terminals N 102 and N 302 of the boosting cell P 102 in the boosting stage ST 1 and the boosting cell P 302 in the boosting stage ST 3 of the boosting cell line L 02 are boosted to:

( VN 102)= VV 1

( VN 302)= VV 3

In this case, it is clear that, because the charge transfer transistors M 1 of the boosting cells P 102 and P 302 have been set to the non-conductive state since time T 2 , the backflow of charge via these charge transfer transistors M 1 does not occur.

The boosting cells P 102 and P 302 perform boosting operation in synchronization with the clock signal CLK 2 A, and at the same time, the clock signal CLK 2 B transitions from high to low, so that the boosting cell P 202 in the boosting stage ST 2 and the backflow preventing cell P 402 in the backflow preventing circuit ST 4 of the boosting cell line L 02 transition to the charge transfer state. The terminal voltages of the boosting cell P 202 and the backflow preventing cell P 402 are as follows.

The source signals SourceN of the boosting cell P 202 and the backflow preventing cell P 402 are:

( VN 104)= Vdd

( VN 304)= VV 2

The voltages VN 101 and VN 301 of the input/output terminals N 101 and N 301 of the boosting cell P 201 in the boosting stage ST 2 and the backflow preventing cell P 401 in the backflow preventing circuit ST 4 of the boosting cell line L 01 are:

( VN 101)= VV 1

( VN 301)= VV 3

The voltages of the input/output terminal N 202 of the boosting cell P 202 and the output terminal of the booster circuit 100 are:

( VN 202)= VV 1

( V PUMP)= VV 3

Therefore, the potential differences between the gates and sources of the on-switch transistors M 2 of the boosting cell P 202 and the backflow preventing cell P 402 in the boosting cell line L 02 are:

( VN 101)−( VN 104)= VV 1 −Vdd=α×Vdd

( VN 301)−( VN 304)= VV 3 −VV 2 =α×Vdd

On the other hand, the potential differences between the gates and sources of the off-switch transistors M 3 are:

( VN 101)−( VN 202)= VV 1 −VV 1=0

( VN 301)−( V PUMP)= VV 3 −VV 3=0

Therefore, the on-switch transistors M 2 transition to the conductive state.

As a result, the voltages VN 1 of the gates N 1 of the charge transfer transistors M 1 in the boosting cell P 202 and the backflow preventing cell P 402 are Vdd and VV 2 , respectively, and the potential differences between the gates and sources of the charge transfer transistors M 1 in the boosting cell P 202 and the backflow preventing cell P 402 are:

( VN 1 of P 202)−( VN 202)= Vdd−VV 1 =−α×Vdd

( VN 1 of P 402)−( V PUMP)= VV 2 −VV 3 =−α×Vdd

Therefore, the charge transfer transistors M 1 in the boosting cell P 202 and the backflow preventing cell P 402 transition to the conductive state, i.e., the charge transfer state. As a result, charge on the input/output terminal N 102 whose voltage has been boosted by the boosting cell P 102 in the boosting stage ST 1 is transferred via the boosting cell P 202 in the boosting stage ST 2 to the input/output terminal N 202 . Charge on the input/output terminal N 302 whose voltage has been boosted by the boosting cell P 302 in the boosting stage ST 3 is transferred via the backflow preventing cell P 402 in the backflow preventing circuit ST 4 to the output terminal of the booster circuit 100 , so that the output voltage VPUMP of the booster circuit 100 is increased.

The voltages of the input/output terminals N 102 -N 302 in the boosting stages of the boosting cell line L 02 are also supplied to the corresponding same boosting stages of the boosting cell line L 03 . As a result, the on-switch transistors M 2 of the boosting cells P 103 and P 303 in the boosting cell line L 03 transition to the non-conductive state, and the off-switch transistors M 3 transition to the conductive state. As a result, as in the boosting cells P 102 and P 302 at time T 2 , the charge transfer transistors M 1 of the boosting cells P 103 and P 303 in the boosting cell line L 03 are set to the non-conductive state.

As described above, operation similar to that of the boosting cells P 102 and P 302 in the boosting cell line L 02 at time T 3 is performed in the boosting cell P 204 and the backflow preventing cell P 404 in the boosting cell line L 04 . Briefly, after the charge transfer transistors M 1 of the boosting cell P 204 and the backflow preventing cell P 404 in the boosting cell line L 04 are set to the non-conductive state at time T 2 , the voltage of the input/output terminal N 204 of the boosting cell P 204 is boosted at time T 3 . Charge on the input/output terminal N 204 whose potential has been increased is transferred via the boosting cell P 304 in the succeeding boosting stage ST 3 to the input/output terminal N 304 . Charge on the input/output terminal N 104 of the boosting cell P 204 is input to the boosting cell P 201 in the succeeding boosting cell line L 01 . Similarly, charge on the input/output terminal N 304 of the backflow preventing cell P 404 is input to the backflow preventing cell P 401 in the succeeding boosting cell line L 01 . As a result, the off-switch transistors M 3 of the boosting cell P 201 and the backflow preventing cell P 401 in the boosting cell line L 01 are set to the conductive state, so that the charge transfer transistors M 1 are set to the non-conductive state.

[Time T 4 ]

Next, at time T 4 , the clock signal CLK 1 B transitions from low to high. As a result, the voltages VN 103 and VN 303 of the input/output terminals N 103 and N 303 of the boosting cell P 103 in the boosting stage ST 1 and the boosting cell P 303 in the boosting stage ST 3 of the boosting cell line L 03 are boosted. In this case, it is clear that, as in the foregoing cases, because the charge transfer transistors M 1 of the boosting cells P 103 and P 303 have been set to the non-conductive state since time T 3 , the backflow of charge via the charge transfer transistors M 1 does not occur.

Charge on the input/output terminal N 103 of the boosting cell P 103 whose potential has been increased is transferred via the boosting cell P 203 in the succeeding boosting stage ST 2 to the input/output terminal N 203 , and charge on the input/output terminal N 303 of the boosting cell P 303 is transferred via the backflow preventing cell P 403 in the succeeding backflow preventing circuit ST 4 to the output terminal of the booster circuit 100 , so that the boosted voltage VPUMP is increased. The voltages of the input/output terminals N 103 -N 303 in the boosting stages of the boosting cell line L 03 are supplied to the corresponding same boosting stages of the succeeding boosting cell line L 04 . As a result, the on-switch transistors M 2 of the boosting cell P 104 and P 304 in the boosting cell line L 04 transition to the non-conductive state, and the off-switch transistors M 3 transition to the conductive state. As a result, as in the boosting cells P 103 and P 303 at time T 3 , the charge transfer transistors M 1 of the boosting cells P 104 and P 304 in the boosting cell line L 04 are set to the non-conductive state.

As described above, operation similar to that of the boosting cells P 103 and P 303 in the boosting cell line L 03 at time T 4 is performed in the boosting cell P 201 and the backflow preventing cell P 401 in the boosting cell line L 01 . Briefly, after the charge transfer transistors M 1 of the boosting cell P 201 and the backflow preventing cell P 401 in the boosting cell line L 01 are set to the non-conductive state at time T 3 , the voltage of the input/output terminal N 201 of the boosting cell P 201 is boosted at time T 4 . Charge on the input/output terminal N 201 whose potential has been increased is transferred via the boosting cell P 301 in the succeeding boosting stage ST 3 to the input/output terminal N 301 . Charge on the input/output terminal N 101 of the boosting cell P 201 is input to the boosting cell P 202 in the succeeding boosting cell line L 02 . Similarly, charge on the input/output terminal N 301 of the backflow preventing cell P 401 is input to the backflow preventing cell P 402 in the succeeding boosting cell line L 02 . As a result, the off-switch transistors M 3 of the boosting cell P 202 and the backflow preventing cell P 402 in the boosting cell line L 02 are set to the conductive state, so that the charge transfer transistors M 1 are set to the non-conductive state.

[Time T 5 ]

Next, at time T 5 , the clock signal CLK 2 B transitions from low to high. As a result, the voltages VN 104 and VN 304 of the input/output terminals N 104 and N 304 of the boosting cell P 104 in the boosting stage ST 1 and the boosting cell P 304 in the boosting stage ST 3 of the boosting cell line L 04 are boosted. In this case, it is clear that, as in the foregoing cases, because the charge transfer transistors M 1 of the boosting cells P 104 and P 304 have been set to the non-conductive state since time T 4 , the backflow of charge via the charge transfer transistors M 1 does not occur.

Charge on the input/output terminal N 104 of the boosting cell P 104 whose potential has been increased is transferred via the boosting cell P 204 in the succeeding boosting stage ST 2 to the input/output terminal N 204 , and charge on the input/output terminal N 304 of the boosting cell P 304 is transferred via the backflow preventing cell P 404 of the succeeding backflow preventing circuit ST 4 to the output terminal of the booster circuit 100 , so that the boosted voltage VPUMP is increased. The voltages of the input/output terminals N 104 -N 304 in the boosting stages of the boosting cell line L 04 which is the final line are supplied to the corresponding same boosting stages of the succeeding boosting cell line L 01 (leading line). As a result, the on-switch transistors M 2 of the boosting cells P 101 and P 301 in the boosting cell line L 01 transition to the non-conductive state, and the off-switch transistors M 3 transition to the conductive state. As a result, as in the boosting cells P 104 and P 304 at time T 4 , the charge transfer transistors M 1 of the boosting cells P 101 and P 301 in the boosting cell line L 01 are set to the non-conductive state.

As described above, operation similar to that of the boosting cells P 104 and P 304 in the boosting cell line L 04 at time T 5 is performed in the boosting cell P 202 and the backflow preventing cell P 402 in the boosting cell line L 02 . Briefly, after the charge transfer transistors M 1 of the boosting cell P 202 and the backflow preventing cell P 402 in the boosting cell line L 02 are set to the non-conductive state at time T 4 , the voltage of the input/output terminal N 202 of the boosting cell P 202 is boosted at time T 5 . Charge on the input/output terminal N 202 whose potential has been increased is transferred via the boosting cell P 302 in the succeeding boosting stage ST 3 to the input/output terminal N 302 . Charge on the input/output terminal N 102 of the boosting cell P 202 is input to the boosting cell P 203 in the succeeding boosting cell line L 03 . Similarly, charge on the input/output terminal N 302 of the backflow preventing cell P 402 is input to the backflow preventing cell P 403 in the succeeding boosting cell line L 03 . As a result, the off-switch transistors M 3 of the boosting cell P 203 and the backflow preventing cell P 403 in the boosting cell line L 03 are set to the conductive state, so that the charge transfer transistors M 1 are set to the non-conductive state.

By the transition at time T 5 , control returns to a state similar to that of time T 1 . Thus, boosting operation is repeated.

The operation of the booster circuit 100 has been described heretofore. As described above, all of the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 and the backflow preventing cells P 401 -P 404 repeatedly perform operation of time T 1 -T 4 to perform boosting operation. In a boosting cell to be operated, the charge transfer transistor M 1 transitions from the conductive state to the non-conductive state (boosting standby state), and thereafter, boosting operation is performed (boosting state), and thereafter, charge is transferred from the preceding stage to the succeeding stage (charge transfer state). Thereafter, the boosting cell returns to the boosting standby state.

Therefore, the description of the boosting standby state, boosting state, and charge transfer state of a single boosting cell can encompass the operation of the other boosting cells and the backflow preventing cell.

Moreover, if conditions for the terminal voltages of the boosting cell or the backflow preventing cell in the boosting standby state, the boosting state, and the charge transfer state can be clearly shown, it can be shown that boosting operation can be performed, by indicating that the terminal voltage conditions are satisfied.

Therefore, as a representative example, the boosting cell P 301 in the boosting stage ST 3 of the boosting cell line L 01 will be described with reference to FIGS. 3 and 4 A- 4 D in terms of the clock signals to the boosting cell and the terminal voltage conditions in the boosting standby state, the boosting state, and the charge transfer state.

Initially, at time T 1 , the boosting cell P 301 needs to cause the charge transfer transistor M 1 to transition from the conductive state to the non-conductive state to be ready for boosting operation. In this case, the clock signal and the terminal voltages are:

clock signal CLK 1 A=L

input terminal INPUT=VV 2

output terminal OUTPUT=VV 2

control signal Sig=VV 1 (the voltage VN 204 of the input/output terminal N 204 of the boosting cell P 304 )

source signal SourceN=VV 1 (the voltage VN 203 of the input/output terminal N 203 of the boosting cell P 303 )

Therefore, when the clock signal is low, the charge transfer transistor M 1 is caused to be in the non-conductive state by:

1. causing the off-switch transistor M 3 to be in the conductive state by satisfying

V (control signal Sig)≦ V (OUTPUT)−| Vtm 3|, and

2. causing the on-switch transistor M 2 to be in the non-conductive state by satisfying

V (Source N )≧ V (Sig)− Vtm 2

In this case, the voltages of the gate and source of the charge transfer transistor M 1 can be equalized. Here, Vtm 2 is the threshold voltage of the on-switch transistor M 2 , and |Vtm 3 | is the absolute value of the threshold voltage of the off-switch transistor M 3 .

Next, at time T 2 , the boosting cell P 301 needs to maintain the charge transfer transistor M 1 in the non-conductive state to perform boosting operation. In this case, the clock signal and the terminal voltages are:

clock signal CLK 1 A=H

input terminal INPUT=VV 1

output terminal OUTPUT=VV 3

control signal Sig=VV 1 (the voltage VN 204 of the input/output terminal N 204 of the boosting cell P 304 )

source signal SourceN=VV 2 (the voltage VN 203 of the input/output terminal N 203 of the boosting cell P 303 )

Therefore, when the clock signal is high, the charge transfer transistor M 1 is caused to be in the non-conductive state by:

1. causing the off-switch transistor M 3 to be in the conductive state by satisfying

V (control signal Sig)≦ V (OUTPUT)−| Vtm 3|, and

2. causing the on-switch transistor M 2 to be in the non-conductive state by satisfying

V (Source N )≧ V (Sig)− Vtm 2

In this case, the voltages of the gate and source of the charge transfer transistor M 1 can be equalized.

Next, at time T 3 , the boosting cell P 301 needs to maintain the charge transfer transistor M 1 in the non-conductive state to maintain boosting operation. In this case, the clock signal and the terminal voltages are:

clock signal CLK 1 A=H

input terminal INPUT=VV 1

output terminal OUTPUT=VV 3

control signal Sig=VV 2 (the voltage VN 204 of the input/output terminal N 204 of the boosting cell P 304 )

source signal SourceN=VV 2 (the voltage VN 202 of the input/output terminal N 202 of the boosting cell P 302 )

Therefore, when the clock signal is high, the charge transfer transistor M 1 is caused to be in the non-conductive state by:

1. causing the off-switch transistor M 3 to be in the conductive state by satisfying

V (control signal Sig)≦ V (OUTPUT)−|Vtm3|, and

2. causing the on-switch transistor M 2 to be in the non-conductive state by satisfying

V (Source N )≧ V (Sig)− Vtm 2

In this case, the voltages of the gate and source of the charge transfer transistor M 1 can be equalized. Voltage conditions when the clock signal is high are the same as those of time T 2 .

Finally, at time T 4 , the boosting cell P 301 needs to cause the charge transfer transistor M 1 to transition from the non-conductive state to the conductive state, thereby transferring charge from the input terminal INPUT to the output terminal OUTPUT. In this case, the clock signal and the terminal voltages are:

clock signal CLK 1 A=L

input terminal INPUT=VV 2

output terminal OUTPUT=VV 2

control signal Sig=VV 2 (the voltage VN 204 of the input/output terminal N 204 of the boosting cell P 304 )

source signal SourceN=VV 1 (the voltage VN 203 of the input/output terminal N 203 of the boosting cell P 303 )

Therefore, when the clock signal is low, the charge transfer transistor M 1 is caused to be in the conductive state by:

1. causing the off-switch transistor M 3 to be in the non-conductive state by satisfying

V (control signal Sig)≧ V (OUTPUT)−| Vtm 3|, and

2. causing the on-switch transistor M 2 to be in the conductive state by satisfying

V (Source N )≦ V (Sig)− Vtm 2

The states in boosting operation of the boosting cell and the backflow preventing cell are summarized in FIG. 5 . The boosting operation states are: (1) the boosting standby state, (2) the boosting state, and (3) the charge transfer state. The clock signal and the terminal conditions are described in FIG. 5 .

There are additional conditions: forbidding conditions and tolerance conditions. Firstly, as the forbidding conditions during transition of each operating state, there are voltage conditions under which the source signal SourceN and the output terminal OUTPUT cause a short circuit, so that charge flows backward from the succeeding stage to the preceding stage.

Forbidding Conditions:

V (Source N )≦ V (Sig)− Vtm 2; and

V (Sig)≦ V (OUTPUT)−| Vtm 3|

During transition of operation, the gate N 1 of the charge transfer transistor M 1 transitions to the high impedance (HiZ) state. In this case, there are tolerance conditions under which the backflow of charge from an input/output terminal in the succeeding stage to an input/output terminal in the preceding stage does not occur.

Tolerance Conditions:

V (Source N )= V (Sig)= V (OUTPUT)

The present disclosure is not limited to the connection of V(Sig) and V(SourceN) in this embodiment. Any connection of V(Sig) and V(SourceN) that satisfies the aforementioned conditions with respect to the clock signal to the boosting cell and the backflow preventing cell to be operated, can be used. In this case, it can be expected that, during boosting operation, the backflow of charge via the charge transfer transistor M 1 can be reduced or prevented.

Note that the aforementioned configuration of the boosting cell and the backflow preventing cell is only for illustrative purposes. Any configuration that can perform a similar function may be used. The number of boosting stages is not limited to three and may be any number. The aforementioned example in which the number of boosting cell lines is four is also only for illustrative purposes. A similar advantage can be expected when the number of boosting cell lines is four or more.

In the boosting cells P 201 -P 204 , and P 301 -P 304 , and the backflow preventing cells P 401 -P 404 provided in the corresponding same stages, the control terminal of the state controller including the on-switch transistor M 2 and the off-switch transistor M 3 is connected to the boosting cell in another line to form a ring connection. Here, the ring connection means that, for example, in the case of the boosting cells in the second stage, the input/output terminal N 104 of the boosting cell P 204 is connected to the control terminal of the state controller of the boosting cell P 201 , the input/output terminal N 101 of the boosting cell P 201 is connected to the control terminal of the state controller of the boosting cell P 202 , the input/output terminal N 102 of the boosting cell P 202 is connected to the control terminal of the state controller of the boosting cell P 203 , and the input/output terminal N 103 of the boosting cell P 203 is connected to the control terminal of the state controller of the boosting cell P 204 . Thus, the ring connection is a logical connection.

A perfect ring connection is not necessarily required. Any connection may be used if the charge transfer transistor of a boosting cell to be operated using the input terminal voltage of a boosting cell in a different line can be set from the conductive state to the non-conductive state, and thereafter, a series of operations which perform boosting operation with respect to the boosting cell to be operated can be repeatedly performed, although not shown. In this case, a similar advantage can be expected. For example, a boosting cell may be controlled by the input terminal voltage of a boosting cell in the immediately preceding line, and another boosting cell may be controlled by the input terminal voltage of the second preceding boosting cell. In this case, a similar advantage can be expected.

In the embodiments described below, it will be shown that boosting operation can be performed, by clearly showing conditions for terminal voltages of the boosting cell in the boosting standby state, the boosting state, and the charge transfer state, or the backflow preventing cell, and indicating that the terminal voltage conditions are satisfied.

<Advantages>

As described above, four clock signals are applied to four (M=4) boosting cell lines arranged in parallel. A boosting cell in the K-th line (1≦K≦M) is connected to the input terminal of a boosting cell in the (K−1)th line (when (K−1)=0, (K−1) is M) of the same stage. By performing a control by switching between the voltage of the output terminal of the boosting cell in the K-th line and the voltage of the input terminal of another boosting cell which is operated at a phase which is different by about 180 degrees from that of the boosting cell in the K-th line, depending on the voltage of the input terminal of the boosting cell in the (K−1)th line, the charge transfer transistor can be set to the non-conductive state during boosting operation without using a complicated clock. As a result, the decrease in boosting efficiency can be reduced or prevented.

The charge transfer transistor M 1 used in the boosting cell and the backflow preventing cell may be configured using a P-channel transistor. Therefore, in this case, even when a twin-well CMOS process is employed, the substrate bias effect of the charge transfer transistor can be reduced or prevented, and the area of the booster circuit can be reduced by the reduction or prevention of the decrease in boosting efficiency.

Second Embodiment

<Configuration>

FIG. 6 shows a booster circuit 200 according to a second embodiment of the present disclosure. FIG. 6 shows a circuit block corresponding to the third boosting stage ST 3 in the booster circuit 100 of FIG. 1 . The circuit block of FIG. 6 is different from the third boosting stage ST 3 in the booster circuit 100 in that the number of boosting cell lines is changed from 4 to 12, specifically, boosting cell lines L 01 -L 12 and boosting cells P 301 -P 312 are provided. Therefore, the boosting cells P 301 -P 312 are provided with input/output terminals N 201 -N 212 and N 301 -N 312 . The boosting cells P 301 -P 312 repeatedly perform boosting operation in synchronization with clock signals CLK 1 A-CLK 6 A and CLK 1 B-CLK 6 B. A boosting cell line in which boosting operation is performed in synchronization with the clock signal CLK 1 A is assumed to be the first line (L 01 ), boosting cell lines in which boosting operation is performed in synchronization with the clock signals CLK 2 A-CLK 6 A are assumed to be the second to sixth lines (L 02 -L 06 ), respectively, and boosting cell lines in which boosting operation is performed in synchronization with the clock signals CLK 1 B-CLK 6 B are assumed to be the seventh to twelfth lines (L 7 -L 12 ), respectively. Note that the clock signals CLK 1 A and CLK 1 B have complementary amplitudes. Similarly, pairs of CLK 2 A and CLK 2 B, CLK 3 A and CLK 3 B, CLK 4 A and CLK 4 B, CLK 5 A and CLK 5 B, and CLK 6 A and CLK 6 B each have the complementary relationship.

FIG. 8 shows operating waveforms of the booster circuit 200 including the 12 lines. Because, as described in the first embodiment, the boosting cells and the backflow preventing cells have similar operating states, the boosting cell P 301 which repeatedly performs boosting operation in synchronization with the clock signal CLK 1 A is used as a representative example to describe operation of the booster circuit 200 . Here, a control signal Sig indicated by CaseA in FIG. 8 is used. The control signal Sig is the voltage of the input/output terminal N 212 of the boosting cell P 312 in the boosting cell line L 12 , and a source signal SourceN is the voltage of the input/output terminal N 207 of the boosting cell P 307 in the boosting cell line L 07 .

Note that, in the booster circuit 200 including the M boosting cell lines (M=12), the boosting cell in the K-th line (1≦K≦M) are connected to the input/output terminal (N 201 -N 212 ) of the boosting cell (P 301 -P 312 ) in the (K−1)th line (when (K− 1 )=0, (K−1) is M). The boosting cell in the K-th line performs boosting operation by switching between the voltage of the output terminal OUTPUT of the boosting cell in the K-th line and the voltage of the input terminal of the boosting cell in the KB-th line which is operated at a phase which is different by about 180 degrees from that of the boosting cell in the K-th line (KB=(M/2+K) when K≦M/2, and KB=(K−M/2) when K>M/2), depending on the voltage of the input/output terminal (N 201 -N 212 ) of the boosting cell (P 301 -P 312 ) in the (K−1)th line.

<Operation>

As described in the first embodiment with reference to FIG. 5 , the operating states of the boosting cell P 301 of the booster circuit 200 synchronous with the clock signal CLK 1 A can be categorized as the boosting standby state, the boosting state, and the charge transfer state using the operating waveforms (control signal: Sig is CaseA) of FIG. 8 .

At time Ta, the clock signal CLK 1 A=L, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 2

V (Source N )= VV 1 =V (Sig)= VV 1

Therefore, at time Ta, the boosting cell P 301 is in the boosting standby state.

Next, at time Tb, CLK 1 A=H, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 3

V (Source N )= VV 2 >V (Sig)= VV 1

Therefore, at time Tb, the boosting cell P 301 is in the boosting state.

At time Tg, the clock signal CLK 6 B transitions from high to low, and:

V (control signal Sig)= VV 2 <V (OUTPUT)= VV 3

V (Source N )= VV 2 =V (Sig)= VV 2

Therefore, the boosting cell P 301 is maintained in the boosting state.

Next, at time Th, the clock signal CLK 1 A transitions from high to low, and:

V (control signal Sig)= VV 2 =V (OUTPUT)= VV 2

V (Source N )= VV 1 <V (Sig)= VV 2

Therefore, the boosting cell P 301 transitions to the charge transfer state.

Next, at time Tm, the boosting cell P 301 transitions to the boosting standby state, which is the same state as that of time Ta.

In this case, the time required for charge transfer is (clock signal cycle×5/12), which is longer than the charge transfer time (=clock signal cycle/4) in the first embodiment, resulting in a reduction or prevention of an increase in the layout size of the charge transfer transistor.

Although the example in which 12 boosting cell lines are arranged in parallel has been described, a similar advantage can be expected if four or more boosting cell lines arranged in parallel are provided (the case of the four lines is described in the first embodiment). Also, the number of boosting stages in the booster circuit 200 is not limited to three and may be any number.

<Advantages>

By increasing the number of boosting cell lines, the charge transfer time can be increased, whereby the increase in the layout size of the charge transfer transistor can be reduced or prevented.

Third Embodiment

<Configuration>

FIG. 7 shows a booster circuit 210 according to a third embodiment of the present disclosure. The booster circuit 210 of FIG. 7 is a variation of the booster circuit 200 of FIG. 6 . The booster circuit 210 is different from the booster circuit 200 in that the input/output terminal N 208 of the boosting cell P 308 in the boosting cell line L 08 which repeatedly performs boosting operation in synchronization with the clock signal CLK 2 B (CLK 2 A) is connected to the control signal Sig of the boosting cell P 301 (the control signal Sig is one indicated by CaseB in FIG. 8 ).

In the M boosting cell lines (M=12) arranged in parallel, the boosting cell in the K-th line (1≦K≦M) performs boosting operation by switching the voltage of the output terminal OUTPUT of the boosting cell of the K-th line and the voltage of the input terminal of a boosting cell which is operated at a phase which is different by about 180 degrees from that of the boosting cell of the K-th line, depending on the voltage of the input/output terminal (N 201 -N 212 ) of the boosting cell (P 301 -P 312 ) in the KA-th line which is the A-th preceding line from the K-th line (A=M/2−1=5, and KA=(K−A) when (K−A)>0, and KA=(M−|K−A|) when (K−A)≦0).

Note that, as in the second embodiment, the boosting cell P 301 which repeatedly performs boosting operation in synchronization with the clock signal CLK 1 A is used as a representative example to describe operation of the booster circuit 210 .

<Operation>

As described in the first embodiment with reference to FIG. 5 , the operating states of the boosting cell P 301 of the booster circuit 210 synchronous with the clock signal CLK 1 A can be categorized as the boosting standby state, the boosting state, and the charge transfer state using the operating waveforms (control signal: Sig is CaseB) of FIG. 8 .

At time Ta, the clock signal CLK 1 A=L, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 2

V (Source N )= VV 1 =V (Sig)= VV 1

Therefore, at time Ta, the boosting cell P 301 is in the boosting standby state.

Next, at time Tb, CLK 1 A=H, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 3

V (Source N )= VV 2 >V (Sig)=VV 1

Therefore, at time Tb, the boosting cell P 301 is in the boosting state.

At time Tg, the clock signal CLK 6 B transitions from high to low, and:

V (control signal Sig)= VV 2 <V (OUTPUT)= VV 3

V (Source N )= VV 2 =V (Sig)= VV 2

Therefore, the boosting cell P 301 is maintained in the boosting state.

Next, at time Th, the clock signal CLK 1 A transitions from high to low, and:

V (control signal Sig)= VV 2 =V (OUTPUT)= VV 2

V (Source N )= VV 1 <V (Sig)= VV 2

Therefore, the boosting cell P 301 transitions to the charge transfer state.

Next, at time Tm, the boosting cell P 301 transitions to the boosting standby state, which is the same state as that of time Ta.

Therefore, it can be seen that the charge transfer time is as short as (clock signal cycle× 1/12), i.e., the charge transfer time is reduced.

According to the second and third embodiments, the control signal Sig of the boosting cell P 301 which performs boosting operation in synchronization with the clock signal CLK 1 A can be connected to the input terminals INPUT of the boosting cells P 312 , P 310 , and P 308 which perform boosting operation in synchronization with the clock signals CLK 6 B, CLK 4 B, and CLK 2 B, respectively. The charge transfer time can be adjusted within the range of (clock signal cycle× 1/12) to (clock signal cycle× 5/12) (the voltage conditions for a boosting cell described in the first embodiment are satisfied).

Specifically, in the M boosting cell lines (M≧4) arranged in parallel, the charge transfer transistor M 1 of the boosting cell in the K-th line (1≦K≦M) can be controlled, depending on the voltage of the input terminal INPUT of the boosting cell in the KA-th line which is the A-th preceding line from the K-th line (1≦A≦M/2−1, and KA=(K−A) when (K−A)>0, and KA=(M−|K−A|) when (K−A)≦0). The charge transfer time can be adjusted under the predetermined constraint.

As the number M of boosting cell lines increases, the time difference ΔT between clock signals decreases, and the time required for transition from the boosting standby state to the boosting state decreases. As a result, the problem that it is difficult to substantially set the charge transfer transistor M 1 to the non-conductive state is solved by arbitrarily changing the input terminal of a boosting cell to which the control signal Sig is connected (setting A) to set an optimum boosting standby state time and a sufficient charge transfer time.

Note that even when, as in the third embodiment, the control terminal of the state controller of a boosting cell is connected to the input terminal of another boosting cell in the same stage which is located in an n-th preceding line (n>1) instead of the first-preceding line, a ring connection is formed as in the first embodiment. Here, the ring connection means that, in the case of the boosting cells in the third stage, the input/output terminal N 208 of the boosting cell P 308 is connected to the control terminal of the state controller of the boosting cell P 301 , the input/output terminal N 209 of the boosting cell P 309 is connected to the control terminal of the state controller of the boosting cell P 302 , the input/output terminal N 210 of the boosting cell P 310 is connected to the control terminal of the state controller of the boosting cell P 303 , the input/output terminal N 211 of the boosting cell P 311 is connected to the control terminal of the state controller of the boosting cell P 304 , the input/output terminal N 212 of the boosting cell P 312 is connected to the control terminal of the state controller of the boosting cell P 305 , the input/output terminal N 201 of the boosting cell P 301 is connected to the control terminal of the state controller of the boosting cell P 306 , the input/output terminal N 202 of the boosting cell P 302 is connected to the control terminal of the state controller of the boosting cell P 307 , the input/output terminal N 203 of the boosting cell P 303 is connected to the control terminal of the state controller of the boosting cell P 308 , the input/output terminal N 204 of the boosting cell P 304 is connected to the control terminal of the state controller of the boosting cell P 309 , the input/output terminal N 205 of the boosting cell P 305 is connected to the control terminal of the state controller of the boosting cell P 310 , the input/output terminal N 206 of the boosting cell P 306 is connected to the control terminal of the state controller of the boosting cell P 311 , and the input/output terminal N 207 of the boosting cell P 307 is connected to the control terminal of the state controller of the boosting cell P 312 .

Thus, a configuration in which the control terminal of the state controller is connected to the input terminal of the boosting cell which is located in an n-th logically preceding line (n>1), and the connection pattern is repeatedly provided, is defined as the ring connection.

<Advantages>

In the M boosting cell lines (M≧4) arranged in parallel, the control signal Sig of a boosting cell in the K-th line is connected to the input terminal INPUT of a boosting cell in the A-th preceding line (1≦A≦M/2−1), whereby an optimum boosting standby state time and a sufficient charge transfer time can be set with respect to the charge transfer transistor M 1 .

Fourth Embodiment

<Configuration>

FIG. 9 shows a booster circuit 220 according to a fourth embodiment of the present disclosure. The booster circuit 220 of FIG. 9 is a variation of the booster circuit 200 of FIG. 6 . The booster circuit 220 is different from the booster circuit 200 in that the input/output terminal N 211 of the boosting cell P 311 in the boosting cell line L 11 which performs boosting operation in synchronization with the clock signal CLK 5 B is connected to the source signal SourceN of the boosting cell P 301 .

In the M boosting cell lines (M=12) arranged in parallel, the source signal SourceN of a boosting cell in the K-th line (1≦K≦M) may be connected to the input terminal INPUT of a boosting cell in the KB-th line which is the B-th preceding line from the K-th line (A<B≦M/2: A is the value described in the third embodiment, and KB=(K−B) when (K−B)>0, and KB=(M−|K−B|) when (K−B)≦0). In the booster circuit 220 , it is assumed that B=2, for example.

<Operation>

As described in the first embodiment with reference to FIG. 5 , the operating states of the boosting cell P 301 of the booster circuit 220 synchronous with the clock signal CLK 1 A can be categorized as the boosting standby state, the boosting state, and the charge transfer state using operating waveforms (the source signal SourceN is CaseC) of FIG. 10 .

Note that CaseA in FIG. 10 indicates the operating waveform of the booster circuit 200 described in the second embodiment.

At time Ta, the clock signal CLK 1 A=L, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 2

V (Source N )= VV 1 =V (Sig)= VV 1

Therefore, at time Ta, the boosting cell P 301 is in the boosting standby state.

Next, at time Tb, CLK 1 A=H, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 3

V (Source N )= VV 1 =V (Sig)= VV 1

Therefore, at time Tb, the boosting cell P 301 is in the boosting state.

At time Tf, the clock signal CLK 5 B transitions from high to low, and:

V (control signal Sig)= VV 1 <V (OUTPUT)= VV 3

V (Source N )= VV 2 >V (Sig)= VV 1

Therefore, the boosting cell P 301 is maintained in the boosting state.

Next, at time Th, the clock signal CLK 1 A transitions from high to low, and:

V (control signal Sig)= VV 2 =V (OUTPUT)= VV 2

V (Source N )= VV 2= V (Sig)= VV 2

Therefore, the gate N 1 of the charge transfer transistor M 1 transitions to the HiZ state. Despite this, the backflow of charge from the boosting cell in the succeeding stage to the boosting cell in the preceding stage does not occur.

Next, at time T 1 , the clock signal CLK 5 B transitions from low to high, and:

V (the control signal Sig)= VV 2 =V (OUTPUT)= VV 2

V (Source N )= VV 1 <V (Sig)= VV 2

Therefore, the boosting cell P 301 transitions to the charge transfer state.

Next, at time Tm, the boosting cell P 301 transitions to the boosting standby state, which is the same state as that of time Ta.

Therefore, the gate N 1 of the charge transfer transistor M 1 transitions to the HiZ state before the charge transfer state. Despite this, the backflow of charge from the boosting cell in the succeeding stage to the boosting cell in the preceding stage via the charge transfer transistor M 1 does not occur.

According to the second and fourth embodiments, the source signal SourceN of the boosting cell P 301 which performs boosting operation in synchronization with the clock signal CLK 1 A can be connected to the input terminals INPUT of the boosting cells which perform boosting operation in synchronization with the clock signals CLK 5 B, CLK 3 B, and CLK 1 B (the voltage conditions for a boosting cell described in the first embodiment are satisfied).

The clock signal CLK 5 B is used to drive the second preceding boosting cell line from CLK 1 A, and the clock signal CLK 1 B is used to drive the sixth preceding boosting cell line from CLK 1 A. When the shift amount of a clock signal from CLK 1 A is represented by B, CLK 5 B is A=2 and CLK 2 B=6=M/2.

Here, in order to satisfy the voltage conditions of FIG. 5 , the source signal SourceN needs to be synchronous with an n-th boosting cell line (n≧1) from the control signal Sig.

Thus, in the M boosting cell lines (M≧4) arranged in parallel, the boosting cell in the K-th line (1≦K≦M) can repeatedly perform boosting operation by switching between the voltage of the output terminal OUTPUT of the boosting cell in the K-th line and the voltage of the input terminal INPUT of the boosting cell in the KB-th line which is the B-th preceding line from the K-th line (A+1≦B≦M/2, and KB=(K−B) when (K−B)>0, and (M−|K−B|) when (K−B)≦0), depending on the voltage of the input terminal INPUT of the boosting cell in the KA-th line which is the A-th preceding line from the K-th line (1≦A≦M/2−1, and KA=(K−A) when (K−A)>0, and KA=(M−|K−A|) when (K−A)≦0).

<Advantages>

In the M boosting cell lines (M≧4) arranged in parallel, the boosting cell in the K-th line (1≦I≦M) can perform boosting operation while reducing or preventing the backflow via the charge transfer transistor.

Fifth Embodiment

In the aforementioned embodiments, for example, the booster circuit 100 receives a power supply voltage to generate a positive boosted voltage. Alternatively, as shown in FIG. 11 , a booster circuit 300 may receive a ground voltage to generate a negative boosted voltage. In this case, in each of the embodiments, the polarity of each transistor included in the booster circuit may be reversed to configure the booster circuit which generates a negative boosted voltage. For example, the boosting cells P 101 -P 104 , P 201 -P 204 , and P 301 -P 304 and the backflow preventing cells P 401 -P 404 of FIGS. 2A-2C may be adapted as shown in FIGS. 12A-12C . Here, transistors MN 1 -MN 4 have conductivities reverse to those of the transistors M 1 -M 4 , respectively.

With the configuration of FIG. 11 , as shown in FIG. 13 , in the booster circuit 300 , the amplitudes of the input/output terminal voltages VNN 101 -VNN 104 of the boosting stage ST 1 vary between Vss and −VV 1 . The amplitudes of the input/output terminal voltages VNN 201 -VNN 204 of the boosting stage ST 2 vary between −VV 1 and −VV 2 . The amplitudes of the input/output terminal voltages VNN 301 -VNN 304 of the boosting stage ST 3 vary between −VV 2 and −VV 3 . The negative booster circuit can generate, at its output terminal, a negative boosted voltage of −VV 3 . If an N-channel transistor is used as the charge transfer transistor MN 1 , a well bias control of the N-channel transistor can be performed, whereby the decrease in boosting efficiency due to the charge transfer transistor MN 1 can be reduced or prevented.

The booster circuit of the present disclosure can reduce or prevent the backflow of charge via a charge transfer transistor occurring in the two-phase booster circuit, and therefore, is useful as, for example, a power supply generating circuit for improving analog circuit characteristics in a non-volatile semiconductor storage device or a CMOS process. Moreover, the booster circuit of the present disclosure is applicable to nonvolatile semiconductor devices, such as a DRAM and the like, liquid crystal displays, power supply circuits for mobile telephones, and the like.