Light-emitting diode (LED) driving circuit

The present application claims the priority benefit of Taiwan application serial no. 98136410, filed on Oct. 28, 2009, and Taiwan application serial no. 98138314, filed on Nov. 11, 2009, the contents of which are hereby incorporated by reference herein in their entireties.

1. Field of the Invention

The present invention relates to a light-emitting diode (LED) driving circuit. More particularly, the present invention relates to an LED driving circuit for driving a plurality of lightbars each including a plurality of LEDs coupled in series.

2. Description of the Prior Art

FIG. 1 is a block diagram illustrating a conventional LED driving circuit. Referring to FIG. 1 , an LED driving circuit 1 is adapted to drive a plurality of lightbars LB 1 -LBm, with each lightbar LBi including a plurality of LEDs D 1 -Dn coupled in series, where m and n are positive integers, and i is an integer from 1 to m. The LED driving circuit 1 includes a direct-current to direct-current (DC/DC) converter 11 and an LED controller 12 . The DC/DC converter 11 , such as a buck or boost converter converts a DC input voltage Vin to a DC voltage V 1 b sufficient to drive the lightbars LB 1 -LBm. Each lightbar LBi has a first terminal coupled to the DC/DC converter 11 to receive the DC voltage V 1 b and a second terminal coupled to a corresponding channel terminal CHi of the LED controller 12 . The LED controller 12 detects current of each lightbar LBi and controls current of each lightbar LBi to become equal to a predetermined value by built-in constant current sources or variable resistors. That is, the LED controller 12 balances currents of the lightbars LB 1 -LBm. The LED controller 12 further outputs a feedback signal from a feedback terminal FB to control the DC/DC converter 11 to adjust the DC voltage V 1 b.

FIG. 2 is a block diagram illustrating another conventional LED driving circuit. Referring to FIG. 2 , if too many lightbars LB 1 -LBm or LEDs D 1 -Dn with high brightness are employed, the total current of the lightbars LB 1 -LBm may cause the LED controller to be destroyed. Accordingly, there is a need for an LED driving circuit to employ an external control manner shown in FIG. 2 . An LED driving circuit 2 includes a DC/DC converter 21 , an LED controller 22 , a plurality of transistors M 1 -Mm and a plurality of resistors R 1 -Rm. The transistor Mi and the resistor Ri are coupled in series between the second terminal of a corresponding lightbar LBi and ground. The LED controller 22 detects current of each lightbar LBi from a corresponding current sensing terminal ISi and outputs a signal from a corresponding channel terminal CHi to control current of each lightbar LBi to become equal to a predetermined value. The LED controller 22 further detects a voltage at the second terminal of each lightbar LBi from a voltage detecting terminal VDi to provide a short protection for the lightbars LB 1 -LBm.

The LED driving circuits 1 and 2 employ the LED controllers 12 and 22 which are specific-purpose integrated circuits (ICs). However, a commercially available LED controller IC supports a fixed number of lightbars. It may be necessary to employ a plurality of LED controller ICs to drive the lightbars as the number of the lightbars increases. The number of the transistors M 1 -Mm and the resistors R 1 -Rm employed in the LED driving circuit 2 will increase as the number of the lightbars increases. Therefore, as the number of the lightbars increases, the conventional LED driving circuits become more complex and expensive to design and manufacture.

It is therefore an object of the present invention to provide an LED driving circuit employing a simple driving structure with reduced components and without using a specific-purpose LED controller IC.

The present invention provides an LED driving circuit for driving a plurality of first lightbars and a plurality of second lightbars. Each of the first and second lightbars includes a plurality of LEDs coupled in series. Each of the first and second lightbars has a first terminal coupled to receive a direct-current (DC) voltage and a second terminal. The LED driving circuit includes a first current mirror, a second current mirror and a control circuit. The first current mirror coupled to the second terminals of the first lightbars balances current among the first lightbars when the first current mirror is enabled, and causes current of the first lightbars to become zero when the first current mirror is disabled. The second current mirror coupled to the second terminals of the second lightbars balances current among the second lightbars when the second current mirror is enabled, and causes current of the second lightbars to become zero when the second current mirror is disabled. The control circuit coupled to the first and second current mirrors, during a first period, disables the second current mirror and adjusts the duration of enabling the first current mirror according to a dimming signal; and, during a second period, disables the first current mirror and adjusts the duration of enabling the second current mirror according to the dimming signal. The first and second periods are repeated alternatively.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a block diagram illustrating a conventional LED driving circuit;

FIG. 2 is a block diagram illustrating another conventional LED driving circuit;

FIG. 3 is a block diagram illustrating an LED driving circuit according to the present invention;

FIG. 4 is a schematic diagram illustrating a first embodiment of the LED driving circuit shown in FIG. 3 ;

FIG. 5 is a timing diagram illustrating a time division control of the LED driving circuit shown in FIG. 4 under maximum brightness;

FIG. 6 is a schematic diagram illustrating a second embodiment of the LED driving circuit shown in FIG. 3 ;

FIG. 7 is a schematic diagram illustrating a third embodiment of the LED driving circuit shown in FIG. 3 ; and

FIG. 8 is a timing diagram illustrating a DCR function control of the LED driving circuit shown in FIG. 7 .

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 3 is a block diagram illustrating an LED driving circuit 3 according to the present invention. Referring to FIG. 3 , an LED driving circuit 3 is adapted to drive a plurality of first lightbars LB 11 -LB 1 m and a plurality of second lightbars LB 21 -LB 2 m , where m is a positive integer. Each of the first lightbars LB 11 -LB 1 m and the second lightbars LB 21 -LB 2 m includes a plurality of LEDs D 1 -Dn coupled in series, where n is a positive integer. Each of the first lightbars LB 11 -LB 1 m and the second lightbars LB 21 -LB 2 m has a first terminal coupled to receive a DC voltage V 1 b and a second terminal. The DC voltage V 1 b , for example, is provided by the DC/DC converter 11 shown in FIG. 1 .

The LED driving circuit 3 includes a first current mirror 31 , a second current mirror 32 and a control circuit 33 . The first current mirror 31 is coupled to the second terminals of the first lightbars LB 11 -LB 1 m . The first current mirror 31 is adapted to balance current among the first lightbars LB 11 -LB 1 m when the first current mirror 31 is enabled, and cause current of the first lightbars LB 11 -LB 1 m to become zero when the first current mirror 31 is disabled. The second current mirror 32 is coupled to the second terminals of the second lightbars LB 21 -LB 2 m . The second current mirror 32 is adapted to balance current among the second lightbars LB 21 -LB 2 m when the second current mirror 32 is enabled, and cause current of the second lightbars LB 21 -LB 2 m to become zero when the second current mirror 32 is disabled. The control circuit 33 is coupled to the first current mirror 31 and the second current mirror 32 . During a first period, the control circuit 33 disables the second current mirror 32 and adjusts the duration of enabling the first current mirror 31 according to a dimming signal Vdim. During a second period, the control circuit 33 disables the first current mirror 31 and adjusts the duration of enabling the second current mirror 32 according to the dimming signal Vdim. The first and second periods are repeated alternatively.

FIG. 4 is a schematic diagram illustrating a first embodiment of the LED driving circuit 4 shown in FIG. 3 . Referring to FIG. 4 , an LED driving circuit 4 includes a first current mirror 41 , a second current mirror 42 and a control circuit 43 . The first current mirror 41 includes a plurality of first transistors Q 11 -Q 1 m . Each first transistor Q 1 i has a first terminal, a second terminal and a control terminal, where i is an integer from 1 to m. The first terminal of each first transistor Q 1 i is coupled to the second terminal of a corresponding first lightbar LB 1 i . The second terminals of the first transistors Q 11 -Q 1 m are coupled to one another and to the control circuit 43 . The control terminals of the first transistors Q 11 -Q 1 m are coupled to one another and to the first terminal of one of the first transistors Q 11 -Q 1 m (e.g. Q 11 ). The second current mirror 42 includes a plurality of second transistors Q 21 -Q 2 m . Each second transistor Q 2 i has a first terminal, a second terminal and a control terminals terminal. The first terminal of each second transistor Q 2 i is coupled to the second terminal of a corresponding second lightbar LB 2 i . The second terminals of the second transistors Q 21 -Q 2 m are coupled to one another and to the control circuit 43 . The control terminals of the second transistors Q 21 -Q 2 m are coupled to one another and to the first terminal of one of the second transistors Q 21 -Q 2 m (e.g. Q 21 ). The first transistors Q 11 -Q 1 m and the second transistors Q 21 -Q 2 m are matched to one another.

The control circuit 43 includes a controller U 1 , a first switch M 1 , a first current detector Rd 1 , a second switch M 2 and a second current detector Rd 2 . The controller U 1 outputs a first pulse-width modulation (PWM) signal Vpwm 1 and a second PWM signal Vpwm 2 . A duty cycle of the first PWM signal Vpwm 1 is determined by the dimming signal Vdim and the total current I 31 of the first lightbars LB 11 -LB 1 m , and a duty cycle of the second PWM signal Vpwm 2 is determined by the dimming signal Vdim and the total current I 32 of the second lightbars LB 21 -LB 2 m . The first switch M 1 has a first terminal coupled to the second terminals of the first transistors Q 11 -Q 1 m , a second terminal and a control terminal coupled to receive the first PWM signal Vpwm 1 . The first current detector Rd 1 has a first terminal coupled to the second terminal of the first switch M 1 and the controller U 1 and a second terminal coupled to ground. The first current detector Rd 1 detects the total current I 31 of the first lightbars LB 11 -LB 1 m . The second switch M 2 has a first terminal coupled to the second terminals of the second transistors Q 21 -Q 2 m , a second terminal and a control terminal coupled to receive the second PWM signal Vpwm 2 . The second current detector Rd 2 has a first terminal coupled to the second terminal of the second switch M 2 and the controller U 1 and a second terminal coupled to ground. The second current detector Rd 2 detects the total current I 32 of the second lightbars LB 21 -LB 2 m.

In this embodiment, the controller U 1 is a general-purpose PWM controller IC such as TL494 or OZ9938. The controller U 1 has a dimming terminal DIM, output terminals G 1 and G 2 and a current sensing terminal IS. The controller U 1 receives the dimming signal Vdim from the dimming terminal DIM, obtains the detection result of the total current I 31 of the first lightbars LB 11 -LB 1 m and the total current I 32 of the second lightbars LB 21 -LB 2 m from the current sensing terminal IS, and outputs the first PWM signal Vpwm 1 and the second PWM signal Vpwm 2 from the output terminals G 1 and G 2 . The first transistors Q 11 -Q 1 m and the second transistors Q 21 -Q 2 m are N-channel field-effect transistors (FETs). The first switch M 1 and the second switch M 2 are implemented by N-channel FETs. The first current detector Rd 1 and the second current detector Rd 2 are implemented by resistors. In an alternative embodiment, the first transistors Q 11 -Q 1 m and the second transistors Q 21 -Q 2 m are NPN bipolar junction transistors (BJTs), and the first switch M 1 and the second switch M 2 are implemented by NPN BJTs.

FIG. 5 is a timing diagram illustrating time division control of the LED driving circuit shown in FIG. 4 under maximum brightness. Referring to FIG. 5 , a pulse signal Vpulse generated by an internal oscillator (not shown) of the controller U 1 serves as an operating frequency of the controller U 1 . Time can be divided into a plurality of periods each having a duration T. Each period includes a pulse having a duration (or pulse width) of Td, where Td is much less than T. These pulses are adapted to avoid overlap between the first PWM signal Vpwm 1 and the second PWM signal Vpwm 2 so that the first lightbars LB 11 -LB 1 m are turned on when the second lightbars LB 21 -LB 2 m are turned off, and the first lightbars LB 11 -LB 1 m are turned off when the second lightbars LB 21 -LB 2 m are turned on. It is defined that odd periods are first periods T 1 and that even periods are second periods T 2 . Hence, the first period T 1 and the second period T 2 are repeated alternatively.

During a first period T 1 , the second PWM signal Vpwm 2 remains always at low level and controls the second switch M 2 to be open to disable the second current mirror 42 , and then, the disabled second current mirror 42 controls the second lightbars LB 21 -LB 2 m to be turned off. The first PWM signal Vpwm 1 is at high level except in the interval from j×2T to (j×2T+Td), where j is a non-negative integer. The first PWM signal Vpwm 1 at high level of a duration Ton 1 controls the first switch M 1 to be closed to enable the first current mirror 41 , and then, the enabled first current mirror 41 controls the first lightbars LB 11 -LB 1 m to be turned on and balances currents I 11 -I 1 m of the first lightbars LB 11 -LB 1 m . The first PWM signal Vpwm 1 at low level of a duration Td controls the first switch M 1 to be open to disable the first current mirror 41 , and, then, the disabled first current mirror 41 controls the first lightbars LB 11 -LB 1 m to be turned off. The duty cycle of the first PWM signal Vpwm 1 , Ton 1 /2T, will be adjusted by the controller U 1 according to the dimming signal Vdim and the total current I 31 of the first lightbars LB 11 -LB 1 m . That is, the duration of enabling the first current mirror 41 or the duration of the first PWM signal Vpwm 1 at high level, Ton 1 , will be adjusted.

During a second period T 2 , the first PWM signal Vpwm 1 remains always at low level and controls the first switch M 1 to be open to disable the first current mirror 41 , and, then, the disabled first current mirror 41 controls the first lightbars LB 11 -LB 1 in to be turned off. The second PWM signal Vpwm 2 is at high level except in the interval from (2j+1)×T to ((2j+1)×T+Td). The second PWM signal Vpwm 2 at high level of a duration Ton 2 controls the second switch M 2 to be closed to enable the second current mirror 42 , and, then, the enabled second current mirror 42 controls the second lightbars LB 21 -LB 2 m to be turned on and balances currents I 21 -I 2 m of the second lightbars LB 21 -LB 2 m . The second PWM signal Vpwm 2 at low level of a duration Td controls the second switch M 2 to be open to disable the second current mirror 42 , and then, the disabled second current mirror 42 controls the second lightbars LB 21 -LB 2 m to be turned off. The duty cycle of the second PWM signal Vpwm 2 , Ton 2 /2T, will be adjusted by the controller U 1 according to the dimming signal Vdim and the total current I 32 of the second lightbars LB 21 -LB 2 m . That is, the duration of enabling the second current mirror 42 or the duration of the second PWM signal Vpwm 2 at high level, Ton 2 , will be adjusted.

In this embodiment, the dimming signal Vdim is a DC signal whose magnitude influences the duty cycles of the first PWM signal Vpwm 1 and the second PWM signal Vpwm 2 . In an alternative embodiment, the dimming signal Vdim is a PWM signal whose duty cycle influences the duty cycles of the first PWM signal Vpwm 1 and the second PWM signal Vpwm 2 .

FIG. 6 is a schematic diagram illustrating a second embodiment of the LED driving circuit shown in FIG. 3 . Referring to FIG. 6 , an LED driving circuit 6 includes a first current mirror 61 , a second current mirror 62 and a control circuit 63 . The first current mirror 61 includes a first constant current source CS 1 , a plurality of first transistors Q 11 -Q 1 m and a second transistor Q 2 . The first constant current source CS 1 provides a first constant current I 1 . Each of the first transistors Q 11 -Q 1 m and the second transistor Q 2 has a first terminal, a second terminal and a control terminals terminal. The first terminal of each first transistor Q 1 i is coupled to the second terminal of a corresponding first lightbar LB 1 i . The second terminals of the first transistors Q 11 -Q 1 m and the second transistor Q 2 are coupled to one another and to ground. The control terminals of the first transistors Q 11 -Q 1 m and the second transistor Q 2 are coupled to one another and to the first terminal of the second transistor Q 2 , the first constant current source CS 1 and the control circuit 63 . The first transistors Q 11 -Q 1 m and the second transistor Q 2 are matched to one another. The second current mirror 62 includes a second constant current source CS 2 , a plurality of third transistors Q 31 -Q 3 m and a fourth transistor Q 4 . The second constant current source CS 2 provides a second constant current I 2 having the same magnitude as the first constant current I 1 . Each of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 has a first terminal, a second terminal and a control terminal. The first terminal of each third transistor Q 3 i is coupled to the second terminal of a corresponding second lightbar LB 2 i . The second terminals of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are coupled to one another and to ground. The control terminals of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are coupled to one another and to the first terminal of the fourth transistor Q 4 , the second constant current source CS 2 and the control circuit 63 . The third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are matched to one another. In this embodiment, the first transistors Q 11 -Q 1 m , the second transistor Q 2 , the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are NPN BJTs. In an alternative embodiment, the first transistors Q 11 -Q 1 m , the second transistor Q 2 , the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are N-channel FETs.

The control circuit 63 includes a controller U 1 , a first switch unit SW 1 and a second switch unit SW 2 . The controller U 1 outputs a first PWM signal Vpwm 1 and a second PWM signal Vpwm 2 . Duty cycles of the first PWM signal Vpwm 1 and the second PWM signal Vpwm 2 are determined by the dimming signal Vdim. The first switch unit SW 1 has a first terminal coupled to the control terminal of the second transistor Q 2 , a second terminal coupled to ground and a control terminal coupled to receive the first PWM signal Vpwm 1 . The second switch unit SW 2 has a first terminal coupled to the control terminal of the fourth transistor Q 4 , a second terminal coupled to ground and a control terminal coupled to receive the second PWM signal Vpwm 2 .

When a short protection mechanism is introduced, the control circuit further 63 further includes a short protection circuit (not shown), a third switch unit SW 3 and a fourth switch unit SW 4 . The short protection circuit coupled to the second terminals of the first lightbars LB 11 -LB 1 m and the second lightbars LB 21 -LB 2 m outputs a short signal Vshort. The short signal Vshort is valid when a voltage at the second terminal of one of the first lightbars LB 11 -LB 1 m and the second lightbars LB 21 -LB 2 m is larger than a threshold voltage. Otherwise, the short signal Vshort is invalid when a voltage at the second terminal of one of the first lightbars LB 11 -LB 1 m and the second lightbars LB 21 -LB 2 m is smaller than the threshold voltage. The third switch unit SW 3 has a first terminal coupled to receive the first PWM signal Vpwm 1 , a second terminal coupled to the control terminal of the first switch unit SW 1 and a control terminal coupled to receive the short signal Vshort. The third switch unit SW 3 is open when the short signal Vshort is valid and closed when the short signal Vshort is invalid. The first switch unit SW 1 is open or closed according to the first PWM signal Vpwm 1 when the third switch unit SW 3 is closed, and the first switch unit SW 1 is closed when the third switch unit SW 3 is open. The fourth switch unit SW 4 has a first terminal coupled to receive the second PWM signal Vpwm 2 , a second terminal coupled to the control terminal of the second switch unit SW 2 and a control terminal coupled to receive the short signal Vshort. The fourth switch unit SW 4 is open when the short signal Vshort is valid and closed when the short signal Vshort is invalid. The second switch unit SW 2 is open or closed according to the second PWM signal Vpwm 2 when the fourth switch unit SW 4 is closed, and the second switch unit SW 2 is closed when the fourth switch unit SW 4 is open.

FIG. 7 is a schematic diagram illustrating a third embodiment of the LED driving circuit shown in FIG. 3 . Referring to FIG. 7 , an LED driving circuit 7 includes a first current mirror 71 , a second current mirror 72 and a control circuit 73 . The first current mirror 71 includes a first constant current source CS 1 , a plurality of first transistors Q 11 -Q 1 m and a second transistor Q 2 . The first constant current source CS 1 provides a first constant current I 1 . Each of the first transistors Q 11 -Q 1 m and the second transistor Q 2 has a first terminal, a second terminal and a control terminal. The first terminal of each first transistor Q 1 i is coupled to the second terminal of a corresponding first lightbar LB 1 i . The second terminals of the first transistors Q 11 -Q 1 m and the second transistor Q 2 are coupled to one another and to the control circuit 73 . The control terminals of the first transistors Q 11 -Q 1 m and the second transistor Q 2 are coupled to one another and to the first terminal of the second transistor Q 2 , the first constant current source CS 1 and the control circuit 73 . The first transistors Q 11 -Q 1 m and the second transistor Q 2 are matched to one another. The second current mirror 72 includes a second constant current source CS 2 , a plurality of third transistors Q 31 -Q 3 m and a fourth transistor Q 4 . The second constant current source CS 2 provides a second constant current I 2 having the same magnitude as the first constant current I 1 . Each of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 has a first terminal, a second terminal and a control terminal. The first terminal of each third transistor Q 3 i is coupled to the second terminal of a corresponding second lightbar LB 2 i . The second terminals of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are coupled to one another and to the control circuit 73 . The control terminals of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are coupled to one another and to the first terminal of the fourth transistor Q 4 , the second constant current source CS 2 and the control circuit 73 . The third transistors Q 31 -Q 3 m and the fourth transistor Q 4 are matched to one another.

The control circuit 73 includes a controller U 1 , a first switch M 1 , a second switch M 2 , a first switch unit SW 1 and a second switch unit SW 2 . The controller U 1 outputs a first PWM signal Vpwm 1 and a second PWM signal Vpwm 2 . Duty cycles of the first PWM signal Vpwm 1 and the second PWM signal Vpwm 2 are determined by the dimming signal Vdim. The first switch M 1 has a first terminal coupled to the second terminals of the first transistors Q 11 -Q 1 m and the second transistor Q 2 , a second terminal coupled to ground and a control terminal coupled to receive the first PWM signal Vpwm 1 . The second switch M 2 has a first terminal coupled to the second terminals of the third transistors Q 31 -Q 3 m and the fourth transistor Q 4 , a second terminal coupled to ground and a control terminal coupled to receive the second PWM signal Vpwm 2 . The first switch unit SW 1 has a first terminal coupled to the control terminal of the second transistor Q 2 , a second terminal coupled to ground and a control terminal coupled to receive a third PWM signal Vpwm 3 . The second switch unit SW 2 has a first terminal coupled to the control terminal of the fourth transistor Q 4 , a second terminal coupled to ground and a control terminal coupled to receive the third PWM signal Vpwm 3 .

When a short protection mechanism is introduced, the control circuit further 73 further includes a short protection circuit (not shown), a third switch unit SW 3 and a fourth switch unit SW 4 . The short protection circuit is described above. The third switch unit SW 3 has a first terminal coupled to receive the third PWM signal Vpwm 3 , a second terminal coupled to the control terminal of the first switch unit SW 1 and a control terminal coupled to receive the short signal Vshort. The third switch unit SW 3 is open when the short signal Vshort is valid and closed when the short signal Vshort is invalid. The first switch unit SW 1 is open or closed according to the third PWM signal Vpwm 3 when the third switch unit SW 3 is closed, and the first switch unit SW 1 is closed when the third switch unit SW 3 is open. The fourth switch unit SW 4 has a first terminal coupled to receive the third PWM signal Vpwm 3 , a second terminal coupled to the control terminal of the second switch unit SW 2 and a control terminal coupled to receive the short signal Vshort. The fourth switch unit SW 4 is open when the short signal Vshort is valid and closed when the short signal Vshort is invalid. The second switch unit SW 2 is open or closed according to the third PWM signal Vpwm 3 when the fourth switch unit SW 4 is closed, and the second switch unit SW 2 is closed when the fourth switch unit SW 4 is open.

FIG. 8 is a timing diagram illustrating DCR function control of the LED driving circuit shown in FIG. 7 . Referring to FIG. 8 , the LED driving circuit 7 can provide a dynamic contrast ratio (DCR) function. When the DCR function of the LED driving circuit 7 are turned off (DCR Off), the dimming signal Vdim is a DC signal, and the brightness provided by the lightbars LB 11 -LB 1 m and LB 21 -LB 2 m is determined by a duty cycle D 1 of the third PWM signal Vpwm 3 with a frequency f 1 . When the DCR function of the LED driving circuit 7 are turned on (DCR ON), the dimming signal Vdim becomes a PWM signal whose frequency f 2 and duty cycle D 2 are determined by the brightness of the image displayed on a display device, and the brightness provided by the lightbars LB 11 -LB 1 m and LB 21 -LB 2 m now is determined by a DCR signal Vdcr which is generated according to the dimming signal Vdim and the third PWM signal Vpwm 3 .

In summary, the LED driving circuit of the present invention divides all lightbars into the first lightbars and the second lightbars for time division control, and only the first lightbars or the second lightbars are driven in each period. For example, only the first lightbars are driven in the first period, and only the second lightbars are driven in the second period. It reduces the amount of current provided by the DC/DC converter for driving the lightbars in each period. Hence, the DC/DC converter can reduce voltage ripple therein and can employ a smaller value filter capacitor at its output to reduce its cost. In addition, the LED driving circuit of the present invention employs a simple driving structure with reduced components and without using a specific-purpose LED controller IC to reduce its cost.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.