Over-drive circuit having stacked transistors

The present application claims priority of U.S. Provisional Patent Application Ser. No. 61/256,157, filed on Oct. 29, 2009, which is incorporated herein by reference in its entirety.

The present disclosure is generally related to a voltage pumping circuit. In various embodiments, the pumping circuit improves hot-carrier reliability effects.

Hot-carriers refer to holes or electrons that have gained very high kinetic energy in areas of high electrical field intensity within a semiconductor device (e.g., a metal-oxide semiconductor (MOS) device). Because of their high kinetic energy, hot carriers can get trapped in device areas (e.g., the gate oxide, the silicon-oxide interface, etc.) where they should not be, which can cause changes to the device threshold voltage and diminish device lifetime. Stacked MOS devices have been widely used in over-drive circuits to reduce hot-carrier degradation and reliability effects. In many approaches, however, voltage Vds, the voltage drop across the drain and the source of a MOS (e.g., the first MOS in a pair of stacked MOS devices) still experiences a high over-voltage during a gate signal transition (e.g., a transition from a low voltage level to a high voltage level or from a high voltage level to a low voltage level), which continues to cause hot-carrier degradations.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of embodiments of the invention will be apparent from the description, drawings, and claims.

FIG. 1 shows a circuit in accordance with an embodiment.

FIG. 2 shows waveforms illustrating operation of the circuit in FIG. 1 , in accordance with an embodiment.

FIG. 3 shows a schematic drawing of an exemplary circuit, in accordance with an embodiment.

FIG. 4 shows waveforms illustrating operation of the circuit in FIG. 3 with respect to the PMOS transistors, in accordance with an embodiment.

FIG. 5 shows waveforms illustrating operation of the circuit in FIG. 3 with respect to the NMOS transistors, in accordance with an embodiment.

FIG. 6 shows a schematic drawing of an exemplary circuit in accordance with another embodiment.

Like reference symbols in the various drawings indicate like elements.

Embodiments, or examples, of the invention illustrated in the drawings are described below using specific language. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and modifications in the described embodiments, and any further applications of principles of the invention described in this document are contemplated as would normally occur to one of ordinary skill in the art to which the invention relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number.

Examplary Over-Drive Circuit

FIG. 1 shows a circuit 100 in accordance with an embodiment. Circuit 100 is an output circuit that can be over-driven to a voltage higher than the process defined device operation voltage.

Pre-driver 105 includes logic circuitry to control circuit 100 to a specific logic state, e.g., high, low, tri-state, etc. Pre-driver 105 provides voltage Vpre_p to and thus controls P-pump circuit 110 . Voltage Vpre_p provides a transitioning voltage based on which a “pump” voltage is provided to node MP 1 _Vg. Pre-driver 105 also provides voltage Vpgate 2 and voltage Vngate 2 that drive transistor MP 2 and MN 2 , respectively.

Voltage Vbias_P is transferred to node MP 1 _Vg and works in conjunction with P-pump circuit 110 to suppress unwanted over-voltage of voltage MP 1 _Vsd (the voltage drop between the source and the drain of transistor MP 1 , not shown). Voltage Vbias_P may be referred to as the middle bias because, in various embodiments, voltage Vbias_P is between 0V and voltage VDDPST, the supply voltage for transistors MP 1 , MP 2 , MN 1 , and MN 2 . In an embodiment of 1.8V device (e.g., the operation voltage defined by a manufacturing process), voltage Vbias_P is configured to be 1.8V to eliminate/reduce the gate-oxide breakdown or hot-carrier effect causing device un-reliabilities. Depending on applications, voltage Vbias_P may be part of P-pump circuit 110 .

P-pump circuit 110 , coupled between pre-driver 105 and the gate of transistors MP 1 , and in conjunction with voltage Vbias_P, provides the pump voltage to the gate of transistor MP 1 (e.g., node MP 1 _Vg) upon detecting a transition of voltage Vpre_p, e.g., from a high to a low. As a result, transistor MP 1 turns on better and causes voltage MP 1 _Vsd to be suppressed to a safe voltage level. Because voltage MP 1 _Vsd operates at a safe level, hot-carrier degradations can be avoided, and the device lifetime can be prolonged. Depending on application, the lifetime of the device using various embodiments of the invention can be greater than about 10 years.

Comparable to P-pump circuit 110 , N-pump circuit 120 coupled between pre-driver 105 and the gate of transistors MN 1 , and in conjunction with voltage Vbias_N, provides the pump voltage to the gate of transistor MN 1 (e.g., node MN 1 _Vg) upon detecting a transition of voltage Vpre_n, e.g., from a low to a high. As a result, transistor MN 1 turns on better and causes voltage MN 1 _Vds to be suppressed to a safe voltage level. Because voltage MP 1 _Vds operates at a safe level, hot-carrier degradations can be avoided, and the device lifetime can be prolonged. Depending on application, the lifetime of the device using various embodiments of the invention can be greater than about 10 years.

The pair of PMOS transistors MP 1 and MP 2 and the pair of NMOS transistors MN 1 and MN 2 may be referred to as stacked MOS transistors, post drivers (e.g., P-post drivers and N-post drivers, respectively), an over-drive output buffer, etc. As illustratively shown in FIG. 1 , transistors MP 2 . MP 1 , MN 1 and MN 2 are coupled in series wherein the source of transistor MP 2 is coupled to supply voltage source VDDPST, the drain of transistor MP 2 is coupled to the source of transistor MP 1 , the drain of transistor MP 1 is coupled to the drain of transistor MN 1 , which also serves as an output for circuit 100 having voltage Vout. Further, the source of transistor MN 1 is coupled to the drain of transistor MN 2 , and the source of transistor MN 2 is coupled to ground, which, as recognizable by persons of ordinary skill in the art, is also voltage VSS (e.g., a reference voltage source). The output swing of these P-type and N-type over-drive output buffers can be larger than their process defined operation voltage. For example, in an embodiment, transistors MP 1 , MP 2 , MN 1 , and MN 2 are 1 . 8 V devices but their output swing can be 0-3.3V (e.g., VDDPST can be at 3.3V). Further, in some embodiments, a dynamic floating N-well is used with PMOS transistors MP 1 and MP 2 to bias the body of these transistors to the highest voltage level and avoid possible leakage caused by the parasitic diode being turned on.

Voltage Vout serves as the output voltage for circuit 100 . Depending on applications, various embodiments of the invention are advantageous when Vout is transitioning, e.g., from a low to a high, or from a high to a low. For example, each of the P-pump circuit 110 and N-pump circuit 120 provides a pump voltage at a particular transition. Further, in the embodiment of FIG. 1 , P-pump circuit 110 provides a pump voltage (e.g. a “P-pump” voltage) and therefore is advantageous when voltage Vout is transitioning from a low to a high. In contrast, N-pump circuit 120 provides another pump voltage (e.g., an “N-pump voltage) and therefore is advantageous when voltage Vout is transitioning from a high to a low.

FIG. 2 shows waveforms 200 illustrating operations of circuit 100 , in accordance with an embodiment. Voltage Vout transitions between 0V and voltage VDDPST. Voltage Vpre_p transitions between two different levels (e.g., a high and a low), and in this embodiment, between voltage VDDPST and voltage Vbias_p. Voltage MP 1 _Vg is generally configured at voltage Vbias_p.

At about time t 1 , voltage Vout or the drain of transistor MP 1 (e.g., node MP 1 _Vd not labeled) is transitioning from 0V to voltage VDDPST, and voltage Vpre_p is transitioning from voltage VDDPST toward voltage Vbias_P. In accordance with some embodiments, P-pump circuit 110 in conjunction with voltage Vbias_P causes a drop in voltage MP 1 _Vg shown as voltage Vmpl_drop that prevents or reduces an over-voltage of voltage MP 1 _Vsd, which, in turns, eliminates/reduces the hot-carrier effect in transistor MP 1 .

Similarly, at about time t 2 , voltage Vout or the drain of transistor MN 1 (e.g., node MN 1 _Vd, not labeled) is transitioning from voltage VDDPST to 0V and voltage Vpre_n is transitioning from 0V toward Vbias_N. In accordance with some embodiments, N-pump circuit 120 in conjunction with voltage Vbias_N causes an increase in voltage MN 1 _Vg shown as voltage Vmnl_increase that prevents or reduces an over-voltage of voltage MN 1 _Vds, which, in turns, eliminates/reduces the hot-carrier effect in transistor MN 1 .

Voltage Pumping Circuits

FIG. 3 shows a schematic drawing of an exemplary circuit 300 and depicts details of an exemplary P-pump circuit 110 and an exemplary N-pump circuit 120 in accordance with an embodiment. Further, as compared to FIG. 1 , pre-driver 105 in FIG. 3 is shown as having the last stage with inverters 107 -P and 107 -N, which, as those of ordinary skill in the art will recognize, are commonly used in the pre-driver circuits. Additionally, voltage Vpgate 2 and voltage Vpre_p in circuit 100 are the same while voltage Vngate 2 and voltage Vpre_n in circuit 100 are the same.

P-pump circuit 110 , coupled between the gates of transistors MP 1 and MP 2 , provides a pump voltage to node MP 1 _Vg upon detecting a transition of voltage Vpgate 2 (e.g., from a high to a low). As a result, transistor MP 1 turns on better and causes voltage MP 1 _Vsd to be suppressed to a safe voltage level. In an embodiment, the safe level for voltage MP 1 _Vsd defined by a manufacturing process is less than 2.5V.

P-pump circuit 110 includes resistor PR coupled between nodes Vbias_P and MP 1 _Vg, and MOS transistor PCT coupled between nodes Vpgate 2 and MP 1 _Vg. MOS transistor PCT serves as a capacitor because its source and drain are coupled together. MOS transistor PCT may be referred to as a MOS capacitor, a capacitor transistor, etc. Resistor PR and MOS capacitor PCT are shown for illustration, but various embodiments of the invention are not so limited. Other circuitry, devices, networks (e.g., a combination of circuitry and/or devices) providing resistance and capacitance in place of resistor PR and transistor PCT are within the scope of various embodiments of the invention. Examples of such circuitry include poly resistors, OD resistors (e.g., resistors in the diffusion region), well resistors, etc., metal-oxide-metal (MOM) capacitors, metal-insulator-metal (MIM) capacitors, MOS varactor capacitors, etc.

Voltage Vbias_P, coupled to one end of resistor PR, provides bias voltage Vbias_p to node MPl_Vg. Under some circumstances, voltage Vbias_P is transferred to node MP 1 _Vg and works in conjunction with MOS capacitor PCT to suppress unwanted over-voltage of voltage MP 1 _Vsd. For example, voltage Vbias_P_provides via resistor PR the bias voltage for transistor MP 1 to reduce voltage MP 1 _Vgs and thus reduce/eliminate un-reliabilities from hot-carrier effects. In the over-drive circuit of FIG. 3 , voltage Vbias_P is configured to be about 10% over the middle point of 1.8V or 1.98V, which is calculated as the worst case for MP 1 reliability concern. In another embodiment of 1.8V device, voltage Vbias_P is configured to be at 1.8V. If voltage Vbias_P is set lower (e.g., 0V), voltage MP 1 _Vsg would be 3.3V, which can cause gate-oxide breakdown.

MOS capacitor PCT, coupled between the gates of transistors MP 1 and MP 2 (e.g., nodes MP 1 _Vg and Vpgate 2 ) provides a desired voltage to node MP 1 _Vg as MOS capacitor PCT is configured to retain a voltage difference between gates of transistors MP 1 and MP 2 previously seen by MOS capacitor PCT. In effect, various embodiments of the invention use MOS capacitor PCT to pump a desired voltage to node MP 1 _Vg. The selected value of resistor PR and the size of MOS capacitor PCT vary depending on various factors such as the size of pre-driver 105 , of post driver transistors MP 1 , MP 2 , MN 1 , MN 2 , output loading at node Vout, etc. Generally, resistor PR and MOS capacitor PCT are selected such that enough voltage is provided to node MP 1 _Vg to suppress the over-voltage of voltage MP 1 _Vsd. The over-voltage of voltage MP 1 _Vsd varies depending on technologies (e.g., process node), the size of transistor MP 1 , etc. In various embodiments of the invention relevant circuitry is simulated to determine this over-voltage and the appropriate value for resistor PR and MOS capacitor PCT is configured to suppress the unwanted over-voltage. In various embodiments of the invention the maximum voltage of voltage MP 1 _Vsd is also estimated and/or simulated to select a value for resistor PR, MOS capacitor PCT, voltage Vbias_P, etc. For example, for a 1.8V device, the calculated maximum endurable for voltage MP 1 _Vsd is about 2.5V, resistor PR, MOS capacitor PCT, and voltage Vbias_P are selected such that voltage MP 1 _Vg can only produce a maximum voltage MP 1 _Vsd of 2.5V. In configurations without the disclosed techniques, voltage MP 1 _Vsd could rise to as high as 3.4V, which can cause undesirable hot-carrier effect.

Voltage Vpgate 2 provided by pre-driver 105 through inverter 107 -P to the gate of transistor MP 2 and MOS capacitor PCT controls transistor MP 2 and MOS capacitor PCT. In an embodiment, voltage Vpgate 2 is anti-phase (e.g., 180 degree out-of-phase) with voltage Vout. For illustration, voltage Vbias_P is at 1.98V, and voltage Vpgate 2 transitions from 3.6V to 1.98V. As a result, the original voltages at two ends (e.g., node Vpgate 2 and node MP 1 _Vg) of MOS capacitor PCT are at 3.6V and 1.98V, respectively. Alternatively expressed, the voltage drop across MOS capacitor PCT is 3.6V−1.98V or 1.62V. When voltage Vpgate 2 transitions to 1.98V, one end of MOS capacitor PCT (e.g., node Vpgate 2 ) is 1.98V. Because MOS capacitor PCT tends to retain the 1.62V across it, which, in theory, causes the voltage at the other end (e.g., node MP 1 _Vg) to be pumped down from 1.98V to 1.98V-1.62V or 0.36V. In an embodiment, however, because resistor PR also fights with the capacitor pumping effect of PMOS capacitor PCT, voltage MP 1 _Vg is driven to about 1.5V. Because voltage MP 1 _Vg is at a voltage (e.g., 1.5V) lower than voltage Vbias_P (e.g., 1.98V), voltage MP 1 _Vg is eventually charged to Vbias_P at 1.98V. At the same time, voltage MP 1 _Vsg (e.g., the voltage across the source and the gate of transistor MP 1 ) increases higher than the voltage without the disclosed techniques because MP 1 _Vsg=MP 1 _Vs−MP 1 _Vg, and because MP 1 _Vg decreases, MP 1 _Vsg, in effect, increases.

Comparable to P-pump circuit 110 , N-pump circuit 120 , coupled between the gates of transistors MN 1 and MN 2 , provides a pump voltage to node MN 1 _Vg upon detecting a transition of voltage Vngate 2 (e.g., from a low to a high). As a result, transistor MN 1 turns on better and causes voltage MN 1 _Vds to be suppressed to a safe voltage level. In an embodiment, the safe level for voltage MN 1 _Vds defined by a manufacturing process is 2.5V.

N-pump circuit 120 includes resistor NR coupled between nodes Vbias_N and MN 1 _Vg, and MOS transistor NCT coupled between nodes Vngate 2 and MN 1 _Vg. MOS transistor NCT serves as a capacitor because its source and drain are coupled together. MOS transistor NCT may be referred to as a MOS capacitor, a capacitor transistor, etc. Resistor NR and MOS capacitor NCT are shown for illustration, but various embodiments of the invention are not so limited. Other circuitry, devices, networks (e.g., a combination of circuitry and/or devices) providing resistance and capacitance in place of resistor NR and transistor NCT are within the scope of various embodiments of the invention. Examples of such circuitry include poly resistors, OD resistors, well resistors, etc., MOM (metal-oxide-metal) capacitors, MIM (metal-insulator-metal) capacitors, MOS varactor capacitors, etc.

Voltage Vbias_N, coupled to one end of resistor NR, provides bias voltage Vbias_N to node MN 1 _Vg. Under some circumstances, voltage Vbias_N is transferred to node MN 1 _Vg and works in conjunction with MOS capacitor NCT to suppress unwanted over-voltage of voltage MN 1 _Vds. For example, voltage Vbias_Nprovides via resistor NR the bias voltage for transistor MN 1 to increase voltage MN 1 _Vgs and thus reduce/eliminate un-reliabilities from hot-carrier effects. In the over-drive circuit of FIG. 3 , voltage Vbias_N is configured to be about 10% below the middle point of 1.8V or 1.62V, which is calculated as the worst case for MN 1 reliability concern. In another embodiment of 1.8V device, voltage Vbias_N is configured to be at 1.8V. If voltage Vbias_N is set higher (e.g., 3.6V), voltage MN 1 _Vgs would be 3.6V, which can cause gate-oxide breakdown.

MOS capacitor NCT, coupled between the gates of transistors MN 1 and MN 2 (e.g., nodes MN 1 _Vg and Vngate 2 ), provides a desired voltage to node MN 1 _Vg as MOS capacitor NCT is configured to retain a voltage difference between gates of transistors MN 1 and MN 2 previously seen by MOS capacitor NCT. In effect, in various embodiments of the invention MOS capacitor NCT is used to pump a desired voltage to node MN 1 _Vg. The selected value of resistor NR and the size of MOS capacitor NCT vary depending on various factors such as the size of pre-driver 105 , of post driver transistors MP 1 , MP 2 , MN 1 , MN 2 , output loading at node Vout, etc. Generally, resistor NR and MOS capacitor NCT are configured such that enough voltage is provided to node MN 1 _Vg to suppress the over-voltage of voltage MN 1 _Vds. The over-voltage of voltage MN 1 _Vds varies depending on technologies (e.g., process node), the size of transistor MN 1 , etc. In various embodiments of the invention the relevant circuitry can be simulated to determine this over-voltage and the appropriate value for resistor NR and MOS capacitor NCT to suppress the unwanted over-voltage. In various embodiments of the invention the maximum voltage of voltage MN 1 _Vds is also estimate and/or simulated to select a value for resistor NR, MOS capacitor NCT, voltage Vbias_N, etc. For example, for a 1.8V device, the calculated maximum endurable for voltage MN 1 _Vds is about 2.5V, resistor NR, MOS capacitor NCT, and voltage Vbais_N are selected such that voltage MN 1 _Vg can only produce a maximum voltage MN 1 _Vds of 2.5V. Without techniques of various embodiments of the invention, voltage MN 1 _Vds could rise to as high as 3.4V, which can cause undesirable hot-carrier effect.

Voltage Vngate 2 provided by pre-driver 105 through inverter 107 -N to the gate of transistor MN 2 and MOS capacitor NCT controls transistor MN 2 and MOS capacitor NCT. In an embodiment, voltage Vngate 2 is the same phase with voltage Vout. For illustration, voltage Vbias_N is at 1.62V, and voltage Vngate 2 transitions from 0V to 1.62V. As a result, the original voltages at two ends (e.g., node Vngate 2 and node MN 1 _Vg) of MOS capacitor NCT are at 0V and 1.62V, respectively. Alternatively expressed, the voltage drop across MOS capacitor NCT is 1.62V-0V or 1.62V. When voltage Vngate 2 transitions to 1.62V one end of MOS capacitor NCT (e.g., node Vngate 2 ) is 1.62V. Because MOS capacitor NCT tends to retain the 1.62V across it, which, in theory, causes the voltage at its other end (e.g., node MN 1 _Vg) to be pumped up from 1.62V to 1.62V+1.62V or 3.24V. In an embodiment, however, because resistor NR also fights with the capacitor pumping effect of NMOS capacitor NCT, voltage MN 1 _Vg increases to about 2.25V. Because voltage MN 1 _Vg is at a voltage (e.g., 2.25V) higher than voltage Vbias_N (e.g., 1.62V), voltage MN 1 _Vg is eventually discharged to Vbias_N at 1.62V. At the same time, voltage MN 1 _Vgs (e.g., the voltage across the gate and the source of transistor MN 1 ) increases higher than the voltage without the disclosed techniques because MN 1 _Vgs=MN 1 _Vg−MN 1 _Vs, and because MN 1 _Vg increases, MN 1 _Vgs, in effect, increases.

Illustrative Waveforms

FIG. 4 shows waveforms 400 illustrating operation of circuit 300 with respect to P-pump circuit 110 . In this illustration, various embodiments are advantageous when node Vout or the drain of transistor MP 1 (e.g., node MP 1 _Vd) is transitioning from a low to a high and voltage Vpgate 2 is transitioning from a high toward voltage Vbias_p. For illustration, such transitions occur at time t 3 (e.g., about 5 ns in FIG. 4 ). Further, a low voltage level is about 0V while a high voltage level is about 3.6V, and voltage Vbias_P is configured at 1.98V.

At time t 3 , voltage MP 1 _Vd (or voltage Vout) transitions from 0V to 3.6V, voltage MP 1 _Vsd is about to switch from about 2.25V to 0V, and voltage Vpgate 2 is about to switch from 3.6V toward 1.98V (e.g., toward voltage Vbias_P). At the same time, voltage MP 1 _Vs (e.g., the voltage at the source of transistor MP 1 ) is about to switch from about 2.25V to 3.6V. Because voltage MP 1 _Vs is about to switch to 3.6V quicker than voltage MP 1 _Vd, it tends to cause higher MP 1 _Vsd during voltage Vout is transitioning from a low to a high. In accordance with some embodiments, however, voltage Vbias_P, together with resistor PR and transistor PCT, causes a coupling of voltage Vbias_P to node MP 1 _Vg, which also causes a drop in voltage MP 1 _Vg shown as voltage MP 1 _Vg_drop that prevents or reduces an over-voltage of voltage MP 1 _Vsd. Alternatively stated, the peak of voltage MP 1 _Vsd is suppressed to be within a safe voltage of about 2.5V. Without various embodiments of the invention, this peak of MP 1 _Vsd could be as high as 3.4V.

FIG. 5 shows waveforms 500 illustrating operation of circuit 300 with respect to N-pump circuit 120 . In this illustration, some embodiments are advantageous when node Vout or the drain of transistor MN 1 (e.g., node MN 1 _Vd) is transitioning from a high to a low and voltage Vngate 2 is transitioning from 0V toward voltage Vbias_N. For illustration, such transitions occur at time t 4 (e.g., about 11 ns in FIG. 5 ). Further, a low logic level is about 0V while a high voltage level is about 3.6V, and voltage Vbias_N is configured at 1.62V.

At time t 4 , voltage MN 1 _Vd (or voltage Vout) transitions from 3.6V to 0V, voltage MN 1 _Vds is about to switch from about 2.5V to 0V, and voltage Vngate 2 is about to switch from 0V to 1.62V (e.g., to voltage Vbias_N). At the same time, voltage MN 1 _Vs (e.g., voltage at the source of transistor MN 1 ) is about to switch from about 1.2V to 0V. Because voltage MN 1 _Vs is about to switch to 0V quicker than voltage MN 1 _Vd, it tends to cause higher MN 1 _Vds during voltage Vout is transitioning from a high to a low. In accordance with some embodiments, however, voltage Vbias_N, together with resistor NR and transistor NCT, causes a coupling of voltage Vbias_N to node MN 1 _Vg, which also causes an increase in voltage MN 1 _Vg shown as voltage MN 1 _Vg_increase that prevents or reduces an over-voltage of voltage MN 1 _Vds. Alternatively stated, the peak of voltage MN 1 _Vds is suppressed to be within a safe voltage of about 2.5V. Without various embodiments of the invention, this peak could be as high as 3.4V.

Circuit Embodiment to Eliminate the Back-Gate Bias Effect

In an embodiment, to eliminate the back-gate bias effect, the body and source of transistor MP 1 are tied together so that voltage MP 1 _Vsb, the voltage between the source to the body, is zero, which, in turn, causes the threshold voltage MP 1 _Vth of transistor MP 1 to decrease and thus turns on transistor MP 1 better. As a result, voltage MP 1 _Vsd peak is further reduced to about 2.3V, as compared to about 2.5V, in the above example in FIG. 4 . Similarly, the body and the source of transistor MN 1 are tied together so that voltage MN 1 _Vsb, the voltage between the source to the body, is zero, which, in turn, causes the threshold voltage MN 1 _Vth of transistor MN 1 to increase and turns on transistor MN 1 better. As a result, voltage MN 1 _Vds peak is further reduced to about 2.3V, as compared to about 2.5V, in the above example in FIG. 5 .

FIG. 6 shows a circuit 600 illustrating the source and the body of transistors MP 1 are coupled together and the source and body of transistors MN 1 are coupled together. In an embodiment, when the source and the body of transistor MN 1 are coupled together, and a deep N-well (e.g., deep N-well 410 ) is used to isolate the body of transistor MN 1 from the common P-substrate.

A number of embodiments of the invention have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, various embodiments of the invention are not limited to a particular level when a signal is activated or deactivated, but, rather, selecting such a level is a matter of design choice and is within the scope of the invention. The various transistors being shown as a particular type (e.g., NMOS, PMOS, etc.) are also for illustration, various embodiments of the invention are not limited to a particular type, but the particular type selected for a transistor is also a design choice and is within the scope various embodiments of the invention.