Voltage level shifter

The present disclosure is related to a voltage level shifter.

Ground, or a ground node, in integrated circuits is the reference point for other voltages to be measured. Generally, the voltage level at a ground node is 0 volts (V). Many circuits, however, have more than one ground domain or ground node wherein, for example, a first sub-circuit uses a first ground node while a second sub-circuit uses a second ground node, and the voltage level at the two ground nodes is different from one another. Similarly, a circuit may have more than one power domain having more than one power supply source providing more than one supply voltage.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims.

FIG. 1 is a diagram of a voltage level shifter, in accordance with some embodiments.

FIG. 2 is a diagram of the voltage level shifter in FIG. 1 having the operational state of each transistor labeled when the input of the voltage level shifter receives a low logic level, in accordance with some embodiments.

FIG. 3 is a flowchart illustrating the operation of the voltage level shifter in FIG. 1 when the input of the voltage level shifter receives a low logic level, in accordance with some embodiments.

FIG. 4 is a diagram of the voltage level shifter in FIG. 1 having the operational state of each transistor labeled when the input of the voltage level shifter receives a high logic level, in accordance with some embodiments.

FIG. 5 is a flowchart illustrating the operation of the voltage level shifter in FIG. 1 when the input of the voltage level shifter receives a high logic level, in accordance with some embodiments.

Like reference symbols in the various drawings indicate like elements.

Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. Reference numbers may be repeated throughout the embodiments, but they do not require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number.

Exemplary Circuit

FIG. 1 is a diagram of a voltage level shifting circuit (e.g., a voltage level shifter) 100 , in accordance with some embodiments. When input IN is applied with a low logic level (e.g., a Low), output OUT follows the voltage level specified at node VSS 2 (e.g., the ground reference input level node). When input IN is applied with a high logic level (e.g., a High), however, output OUT follows the voltage specified at node VDD 2 (e.g., the power supply input level node). Stated another way, voltage level shifter 100 shifts the ground level in a first ground domain having voltage VSS 1 as ground to a second ground domain having voltage VSS 2 as ground. Similarly, voltage level shifter 100 shifts the supply level in a first power domain (e.g., power supply domain) having voltage VDD 1 as an operational voltage to a second power domain having voltage VDD 2 as an operational voltage.

For example, in some circuits in a first ground domain, the Low has a voltage value of voltage VSS 1 (e.g., 0 V) while in some other circuits in a second ground domain, the Low has a voltage value of voltage VSS 2 (e.g., −0.5 V). Similarly, in some circuits in a first power domain, the High has a voltage value of voltage VDD 1 (e.g., 0.85 V) while in some other circuits in a second power domain, the High has a voltage level of voltage VDD 2 (e.g., 0.95 V). In FIG. 1 , inverter INV 1 is in both the first ground domain and the first power domain because, when input IN is Low, output O 1 is High at the voltage value of voltage VDD 1 . But when input IN is High, output O 1 is Low at the voltage value of voltage VSS 1 . For a further example, inverter INV 2 is in both the second ground domain and the second power domain because when output OUT is Low, the Low voltage value is from voltage VSS 2 , but when output OUT is High, the High voltage value is from voltage VDD 2 . Even though voltage level shifter 100 can shift both the ground level of voltage VSS 1 and the power supply level of voltage VDD 1 , shifting either the ground level or the power supply level is within the scope of various embodiments. For example, to shift the ground level only, voltage VDD 2 is set at voltage VDD 1 or both nodes of voltage VDD 1 and VDD 2 are coupled together. Similarly, to shift the power supply level only, voltage VSS 2 is set at voltage VSS 1 or nodes of voltage VSS 1 and VSS 2 are coupled together.

PMOS transistor P 7 and NMOS transistor N 6 are coupled in series (e.g., the drain of PMOS transistor P 7 is coupled to the drain of NMOS transistor N 6 ) and form inverter INV 1 . Output O 1 of inverter INV 1 serves as the input for inverter INV 2 constituted by PMOS transistor P 0 and NMOS transistor N 0 coupled in series (e.g., the drain of PMOS transistor P 0 is coupled to the drain of NMOS transistor N 0 ). The output of inverter INV 2 serves as output OUT for level shifter 100 , which also controls (e.g., turns on/off) NMOS transistor N 2 . For example, when output OUT is High, the gate of transistor N 2 is High, which turns on transistor N 2 . When output OUT, however, is Low, the gate of transistor N 2 is Low, which turns off transistor N 2 .

NMOS transistors N 0 and N 3 are coupled in series (e.g., the source of NMOS transistor is coupled to the drain of NMOS transistor N 3 ). When input IN is low, transistor N 3 together with transistor N 0 pulls the voltage level at output OUT, which is the drain of transistor N 0 , to the voltage level at node VSS 2 , which is the source of transistor N 3 .

Transistor P 0 , when input IN is High), pulls the voltage level at output OUT, which is the drain of transistor P 0 , to the voltage level at the source of transistor P 0 , which is voltage VDD 2 .

PMOS transistor P 1 and NMOS transistor N 1 are coupled in series (the drain of PMOS transistor P 1 is coupled to the drain of NMOS transistor N 1 ), and form inverter INV 3 . Node O 2 , the output of inverter INV 3 , controls (e.g., turns on/off) transistor N 3 . For example, when output O 2 is High, the gate of NMOS transistor N 3 is High, which turns on transistor N 3 . But if output O 2 is Low, the gate of NMOS transistor N 3 is Low, which turns off transistor N 3 .

In some embodiments,

VDD 1 >Vtn 1 +VSS 1 and VDD 2 >Vtn 2 +VSS 2 and

VDD 1 >Vtn 2 +VSS 2 and VDD 1 >VDD 2 −|Vtp 2|

Wherein voltage Vtn 1 is the threshold voltage of NMOS transistor N 6 , and voltage Vtn 2 is the threshold voltage of NMOS transistors N 0 , N 1 , N 2 , and N 3 . Voltage Vtp 2 is the threshold voltage of transistors P 0 and P 1 .

In the above illustration, when VDD 1 >Vtn 1 +VSS 1 , transistor N 6 has sufficient power supply to be on. When VDD 2 >Vtn 2 +VSS 2 transistors N 2 and N 3 have sufficient power supply to be on. When VDD 1 >Vtn 2 +VSS 2 , transistors N 0 and N 1 have sufficient power supply be on, and when VDD 1 >VDD 2 −|Vtp 2 |, transistors P 0 and P 1 have sufficient power to be off. In some embodiments, voltages VSS 1 and VSS 2 are in the range from about −0.5 V to about 0.3, but different ranges are within the scope of various embodiments.

Exemplary Operation with the Input Receiving a Low Logic Level

FIG. 2 is a diagram 200 of voltage level shifter 100 having the operational state of each transistor labeled, illustrating an operation of voltage level shifter 100 when a Low is applied to input IN, in accordance with some embodiments. As illustratively shown, transistors N 6 , P 0 , N 1 , and N 2 are off while transistors P 7 , N 0 , N 3 , and P 1 are on. Further, voltages VSS 1 , VDD 1 , VSS 2 , and VDD 2 are set at 0.0 V, 0.85 V, and −0.5 V, and 0.95 V, respectively. In some embodiments, when input IN is Low, the voltage level of output OUT follows the voltage level specified at node VSS 2 , which, for illustration, is −0.5 V.

Because input IN is Low, NMOS transistor N 6 is off while PMOS transistor P 7 is on. Node O 1 , which is the drain of PMOS transistor P 7 is pulled to the voltage level at the source of PMOS transistor P 7 , which is High at the voltage value of voltage VDD 1 (e.g., 0.85V). Stated another way, because input IN of inverter INV 1 is Low, output O 1 , the output of inverter INV 1 , is High, which also turns off PMOS transistor P 0 , and turns on NMOS transistor N 0 . Because transistor P 0 is off, output OUT is electrically disconnected from voltage VDD 2 .

Because input IN is Low, the gates of PMOS transistor P 1 and NMOS transistor N 1 are Low. As a result, transistor P 1 and N 1 are on and off, respectively. Because transistor P 1 is on, node O 2 , which is the drain of transistor P 1 , is pulled to the voltage level at its source, which is voltage VDD 2 . Because node O 2 is also the gate of transistor N 3 , which is at voltage VDD 2 , transistor N 3 turns on.

Because NMOS transistor N 0 is on, the voltage level at the drain of transistor N 0 is pulled to the source of transistor N 0 , which is the drain of transistor N 3 . Because transistor N 3 is on, it pulls the voltage level at its drain to the voltage level at its source, which is voltage VSS 2 or −0.5 V. Stated differently, the voltage level at output OUT is pulled to (or follows) the voltage level at node VSS 2 , which is illustratively shown at −0.5 V.

FIG. 3 is a flowchart 300 , illustrating the operation of voltage level shifter 100 , when input IN receives a Low.

In step 305 , a Low is applied at input IN.

In step 310 , inverter INV 1 inverts the Low at input IN to a High at node O 1 , which turns on transistor N 0 .

In step 315 , inverter INV 2 inverts the High at node O 1 to a Low at output OUT.

In step 320 , inverter INV 3 inverts the Low at input IN to a High at node O 2 , which turns on transistor N 3 .

In step 325 , transistors N 0 and N 3 pull the voltage level at output OUT to the voltage level at the source of transistor N 3 having voltage VSS 2 , which is −0.5 V. In effect, output OUT has voltage VSS 2 or −0.5 V.

Exemplary Operation with the Input Receiving a High Logic Level

FIG. 4 is a diagram 400 of voltage level shifter 100 having the operational state of each transistor labeled, illustrating an operation of voltage level shifter 100 when a High is applied to input IN, in accordance with some embodiments. As illustratively shown, transistors N 6 , P 0 , N 1 , and N 2 are on while transistors P 7 , N 0 , N 3 , and P 1 are off. Further, voltages VSS 1 , VDD 1 , VSS 2 , and VDD 2 are set at 0.0 V, 0.85 V, and −0.5 V, and 0.95 V, respectively. In some embodiments, when input IN is High, the voltage level of output OUT follows the voltage level specified at node VDD 2 , which, for illustration, is 0.95 V.

Because input IN is High, NMOS transistor N 6 is on while PMOS transistor P 7 is off. Node O 1 , which is the drain of NMOS transistor N 6 , is pulled to the voltage level at the source of NMOS transistor N 6 , which is Low at the voltage value of voltage VSS 1 (e.g., 0 V). Stated another way, because input IN of inverter INV 1 is High, output O 1 , the output of inverter INV 1 , is Low, which also turns on PMOS transistor P 0 , and turns off NMOS transistor N 0 . Because transistor P 0 is on, output OUT, which is the drain of transistor P 0 , is pulled to the source of transistor P 0 , which is High (e.g., VDD 2 or 0.95 V). Because output OUT is also the gate of transistor N 2 , which is High, transistor N 2 is on.

Because input IN is High, the gates of PMOS transistor P 1 and NMOS transistor N 1 are High. As a result, transistor P 1 and N 1 are off and on, respectively. Because transistor N 1 is on, node O 2 , which is the drain of transistor N 1 , is pulled to the voltage level at its source, which is the drain of transistor N 2 . Because NMOS transistor N 2 is on, the voltage level at its drain is pulled to the voltage level at its source, which is voltage VSS 2 or Low. As a result, node O 2 is Low. Because node O 2 is also the gate of transistor N 3 , which is Low, transistor N 3 turns off. Because NMOS transistors N 0 and N 3 are off, node of voltage VSS 2 is electrically disconnected from output OUT.

FIG. 5 is a flowchart 500 , illustrating the operation of voltage level shifter 100 , when input IN receives a High.

In step 505 , a High is applied at input IN.

In step 510 , inverter INV 1 inverts the High at input IN to a Low at node O 1 , which turns off transistor N 0 .

In step 515 , inverter INV 3 inverts the High at input IN to a Low at node O 2 , which turns off transistor N 3 . Because transistors N 0 and N 3 are off, node of voltage VSS 2 is electrically disconnected from output OUT.

In step 520 , inverter INV 2 inverts the Low at node O 1 to a High of voltage VDD 2 at output OUT. Explained another way, the Low at output O 1 also turns on transistor P 0 , which pulls the voltage level at output OUT (e.g., the drain of transistor P 0 ) to the voltage level at the source of transistor P 0 having voltage VDD 2 . In effect, output OUT has voltage VDD 2 or 0.95 V.

A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the various transistors being shown as a particular dopant type (e.g., NMOS and PMOS) are for illustration purposes, embodiments of the disclosure are not limited to a particular type, but the dopant type selected for a particular transistor is a design choice and is within the scope of embodiments. The logic level (e.g., low or high) of the various signals used in the above description is also for illustration purposes, embodiments are not limited to a particular level when a signal is activated and/or deactivated, but, rather, selecting such a level is a matter of design choice.

For another example, in some embodiments, when input IN is Low, output OUT follows voltage VSS 2 , and when input IN is High, output OUT follows voltage VDD 2 .

For another example, some embodiments regard a circuit comprising: a first inverter, a second inverter, a third inverter, and a first NMOS transistor. An input of the first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of the second inverter. An output of the second inverter is configured to serve as an output node. An input of the third inverter is coupled to an input of the first inverter. A gate of the first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as an input level node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

For another example, some embodiments regard a circuit comprising: a first PMOS transistor having a first P gate, a first P drain, and a first P source; a first NMOS transistor having a first N gate, a first N drain, and a first N source; a second PMOS transistor having a second P gate, a second P drain, and a second P source; a second NMOS transistor having a second N gate, a second N drain, and a second N source; a third PMOS transistor having a third P gate, a third P drain, and a third P source; a third NMOS transistor having a third N gate, a third N drain, and a third N source; a fourth NMOS transistor having a fourth N gate, a fourth N drain, and a fourth N source; a fifth NMOS transistor having a fifth N gate, a fifth N drain, and a fifth N source; an input node; an output node; a first level input node; and a second level input node. The input node is coupled to the first P gate, the first N gate, the third P gate, and the third N gate. The first P drain is coupled to the first N drain, the second P gate, and the second N gate. The second P drain is coupled to the second N drain, the fifth N gate, and the output node. The second P source is coupled to the third P source and the second input level node. The second N source is coupled to the fourth N drain. The fourth N gate is coupled to third N drain and the third P drain. The fourth N source is coupled to the fifth N source and the first level input node. The third N source is coupled to the fifth N drain. When the input node is configured to receive a low logic level the output node is configured to receive a first voltage value provided by the first level input node, and when the input node is configured to receive a high logic level the output node is configured to receive a second voltage value provided by the second level input node.

For another example, some embodiments regard a method comprising: using a first inverter to invert a first high logic level to a first low logic level; using a second inverter to invert the first low logic level to a second high logic level; a voltage value of the second high logic level provided by a PMOS transistor of the second inverter; and using a third inverter to invert the first high logic level to a second low logic level to turn off a first NMOS transistor coupled to a second NMOS transistor of the second inverter; the second high logic level configured to turn on a third NMOS transistor coupled to a fourth NMOS transistor of the third inverter.

For another example, some embodiments regard a method comprising: using a first inverter to invert a first low logic level to a first high logic level; using a second inverter to invert the first high logic level to a second low logic level; the second inverter having a first PMOS transistor coupled in series with a first NMOS transistor; a drain of the first NMOS transistor configured to provide the second low logic level; and using a second NMOS transistor coupled in series with the first NMOS transistor to provide a voltage value at a source of the second NMOS transistor coupled to the drain of the first NMOS transistor.

The above methods show exemplary steps, but they are not necessarily performed in the order shown, and some steps may be performed concurrently. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.