Dynamic random access memory unit and data refreshing method thereof

1. Field of the Invention

The invention relates to a semiconductor memory device technique of a dynamic random access memory (DRAM). More particularly, the invention relates to a semiconductor memory device technique of performing a refresh operation to memory cells of specified word line address intervals, so as to reduce power consumption.

2. Description of Related Art

In a dynamic random access memory (DRAM), an amount of charges stored in a capacitor is used to represent “1” or “0” of a binary bit, so that each memory cell of the DRAM only requires one capacitor and one switch (or one transistor).

During an actual operation, the capacitors in the DRAM may have an electric leakage phenomenon, which may cause an insufficient potential difference of the capacitors, so that data stored in the DRAM can be disappeared. Therefore, the DRAM has to enter a refresh mode to periodically refresh (which can also be referred to as data charging/data refreshing) all of the memory cells, so as to ensure correctness of information stored in the DRAM. As shown in FIG. 1 and FIG. 2 , FIG. 1 is a block diagram illustrating a conventional DRAM unit 10 , and FIG. 2 is a signal waveform diagram of a data refreshing method of the conventional DRAM unit 10 . Referring to FIG. 1 , the DRAM unit 10 includes a memory array 110 , a refresh timing controller 120 and a word line address counter 130 . The memory array 110 includes a plurality of word lines and a plurality of bit lines. The word lines are perpendicularly intersected to the bit lines, and each intersection thereof has a memory cell for storing a binary (i.e. “0” or “1”) bit information.

The refresh timing controller 120 receives an entry refresh signal S ref , so as to determine whether the DRAM unit 10 is in the refresh mode. During the refresh mode, the refresh timing controller 120 generates a refresh clock signal S clk (referring to FIG. 2 ), and the word line address counter 130 cyclically calculates a word line address WL according to the refresh clock signal S clk . In the present embodiment, each pulse interval of the refresh clock signal S clk is 8 μS, so as to avoid excessive long refresh period that causes an error of data stored in the memory array 110 . Moreover, the word line address WL of the memory array 110 is composed of hexadecimal number of three digits, and a word line addresses interval of the memory array 110 is between 000 H and FFF H , so that after the word line address counter 130 sequentially counts from 000 H to FFF H , the word line address counter 130 restarts the counting from 000 H . The memory array 110 continually receives the refresh clock signal S clk and the word line address WL during the refresh mode, so as to periodically refresh all of the memory cells in the memory array 110 . However, during an application of the DRAM, not all of the memory cells are stored with data, so that when the memory cells that are not stored with data are charged/refreshed, extra charges are consumed.

Therefore, multiple DRAM refreshing techniques are developed to reduce the power consumption of the DRAM in the refresh mode. U.S. Pat. No. 6,590,822 discloses a self-refresh memory device, and in such memory device, a refresh command signal generated by a computer system is used to mask one or a plurality of bits in a word line address data, and a part of (for example, ½, ¼, ⅛ or 1/16, etc.) RAM memory blocks are provided in advance for data storage and the refresh operation, and other memory blocks are disabled, so as to reduce the power consumption. However, only a fixed rate (for example, ½, ¼ or ⅛, etc.) of the memory capacity of the above memory device can be used to store data. In case of an excessively large memory capacity, extra power is consumed for the memory blocks that are not stored with data during the data refreshing operation, and in case of an excessively small memory capacity, the memory device is not applicable for the computer system. Regarding the above memory device, the computer system cannot specify the required memory capacity in detail, so that a degree of freedom of the DRAM used by the computer system is reduced.

Accordingly, the invention is directed to a dynamic random access memory (DRAM) unit, which can refresh memory cells corresponding to specified word line address intervals, and stop refreshing memory cells outside the specified word line address intervals during a refresh mode, so as to reduce power consumption during the refresh mode.

According to another aspect, the invention is directed to a data refreshing method of a dynamic random access memory (DRAM) unit, by which memory cells corresponding to specified word line address intervals are refreshed, and memory cells outside the specified word line address intervals are not refreshed during a refresh mode, so as to reduce power consumption during the refresh mode.

The invention provides a dynamic random access memory (DRAM) unit including a memory array, a refresh address module, and a refresh control module. The memory array includes a plurality of memory cells. The refresh address module produces a refresh word line address cyclically during a refresh mode. The refresh control module is coupled to the memory array and the refresh address module, and obtains at least one start word line address and at least one stop word line address corresponding to the start word line address, wherein the start word line addresses and the corresponding stop word line addresses form at least one memory word line address interval. The refresh control module determines whether the refresh word line address is within the memory word line address intervals, and executes a data charging operation to the memory cells corresponding to the refresh word line address if the refresh word line address is within the memory word line address intervals, or stop the data charging operation otherwise.

According to another aspect, the invention provides a data refreshing method of a dynamic random access memory (DRAM) unit, wherein the DRAM unit includes a memory array having a plurality of memory cells. The data refreshing method of the DRAM unit includes following steps. At least one start word line address and at least one stop word line address corresponding to the start word line address are obtained, wherein the start word line addresses and the corresponding stop word line addresses form at least one memory word line address interval. Moreover, a refresh address module is provided during a refresh mode, and the refresh address module produces a refresh word line address cyclically. Then, it is determined that the refresh word line address is within the memory word line address intervals, so as to execute a data charging operation to the memory cells corresponding to the refresh word line address, or stop the data charging operation otherwise.

According to the above descriptions, in the invention, commands of a computer system or self-detect result of the memory cell stored with data form the DRAM can be used to obtain the word line address intervals. Then, during the refresh mode, the refresh control module determines whether the refresh word line address is within the memory word line address intervals, so as to refresh the memory cells within the memory word line address intervals, or stop refreshing the memory cells outside the memory word line address intervals, so that power consumption of the DRAM during the refresh mode can be reduced. Moreover, by determining whether the memory cells in the DRAM have been stored with data, a plurality of the word line address intervals can be obtained, thus a purpose of only refreshing the memory cells stored with data can be achieved.

In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a block diagram illustrating a conventional dynamic random access memory (DRAM) unit.

FIG. 2 is a signal waveform diagram of a data refreshing method of a conventional DRAM unit.

FIG. 3 is a block diagram illustrating a DRAM unit according to an embodiment of the invention.

FIG. 4 is a block diagram illustrating a memory array according to an embodiment of the invention.

FIG. 5 is a flowchart of a data refreshing method of a DRAM unit according to an embodiment of the invention.

FIG. 6 is a signal waveform diagram of a data refreshing method of a DRAM unit according to an embodiment of the invention.

FIG. 7 is a block diagram illustrating a DRAM unit according to another embodiment of the invention.

Referring to FIG. 3 , FIG. 3 is a block diagram illustrating a dynamic random access memory (DRAM) unit 30 according to an embodiment of the invention. The DRAM unit 30 includes a memory array 110 , a refresh address module 310 , and a refresh control module 320 . The memory array 110 has a plurality of memory cells, and a structure thereof is as that shown in FIG. 4 . FIG. 4 is a block diagram illustrating the memory array 110 according to an embodiment of the invention.

Referring to FIG. 4 , the memory array 110 includes a memory block 410 , a word line decoder 420 and a signal comparator module 430 . The memory block 410 includes word lines WL 1 -WLN and bit lines BL 1 -BLM, wherein N is a total number of the word lines WL 1 -WLN, and M is a number of memory cells corresponding to each of the word lines WL 1 -WLN. The word lines WL 1 -WLN are perpendicularly intersected to the bit lines BL 1 -BLM, and each intersection has a memory cell (not shown), which is used for storing a binary (i.e. “0” or “1”) bit information. The memory array 110 can select M-bit data according to one of the word lines WL 1 -WLN to perform a write/read/refresh operation. The word line decoder 420 receives and decodes a word line address WL to obtain one of the word lines WL 1 -WLN corresponding to the word line address WL. The signal comparator module 430 receives a refresh clock signal S clk and a clock enable signal S en during the refresh mode, so as to perform a comparison operation of stored data and a data charging operation to the M memory cells corresponding to the word line address WL.

Referring to FIG. 3 again, the refresh address module 310 receives an entry refresh signal S ref , so as to determine whether a computer system switches the DRAM unit 30 to the refresh mode, and the refresh address module 310 cyclically produces a refresh word line address WL during the refresh mode. In detail, the refresh address module 310 includes a refresh timing controller 120 and a word line address counter 130 . The refresh timing controller 120 generates the refresh clock signal S clk during the refresh mode. The word line address counter 130 is coupled to the refresh timing controller 120 , and receives the refresh clock signal S clk , so as to cyclically accumulate the word line address WL (which is also referred to as the refresh word line address WL in the present embodiment) according to the refresh clock signal S clk . In other words, the so-called “cyclically produce” refers to that the word line address counter 130 accumulates the refresh word line address WL by 1 according to each pulse of each refresh clock signal S clk , and when it is accumulated to a last word line address of the memory array 110 , the accumulation is restarted from a first word line address of the memory array 110 , so as to periodically perform data refreshing to the memory cells stored with data in the memory array 110 .

The refresh control module 320 of FIG. 3 is coupled to the memory array 110 and the refresh address module 310 . In the present embodiment, the refresh control module 320 includes a register unit 330 and an address interval determination unit 340 . The register unit 330 is used for storing start word line addresses WLstart 1 -WLstartP and stop word line addresses WLstop 1 -WLstopP. The start word line addresses WLstart 1 -WLstartP and the corresponding stop word line addresses WLstop 1 -WLstopP may form P memory word line address intervals, where P is a positive integer, and the memory word line address intervals are not mutually overlapped.

In the present embodiment, the address interval determination unit 340 of FIG. 3 is coupled to the register unit 330 , and the address interval determination unit 340 is used for determining whether the refresh word line address WL is within memory word line address intervals AR 1 and AR 2 . If the refresh word line address WL is within the memory word line address intervals AR 1 and AR 2 , the address interval determination unit 340 transmits the refresh word line address WL and the refresh enable signal S en to the memory array 110 , so as to perform the data charging operation to the memory cells corresponding to the refresh word line address WL. Moreover, to reduce a circuit area of the DRAM unit 30 , the address interval determination unit 340 of the present embodiment is implemented by a digital logic circuit, though the invention is not limited thereto.

To fully convey the spirit of the invention to those skilled in the art, a data refreshing method of the DRAM unit 30 is described below with reference of FIG. 5 and FIG. 6 . FIG. 5 is a flowchart of a data refreshing method of the DRAM unit 30 according to an embodiment of the invention, and FIG. 6 is a signal waveform diagram of the data refreshing method of the DRAM unit 30 according to an embodiment of the invention. Referring to FIG. 5 , in step S 510 , the DRAM unit 30 first obtains the start word line addresses WLstart 1 -WLstartP and the corresponding stop word line addresses WLstop 1 -WLstopP, so as to form the memory word line address intervals AR 1 and AR 2 . It is assumed that the computer system provides two memory word line address intervals AR 1 and AR 2 (i.e. P=2, which are illustrated on the memory block 410 of FIG. 4 ) to the refresh control module 320 of the DRAM unit 30 in advance. The first memory word line address interval AR 1 is from the address WLstart 1 (005 H ) to the address WLstop 1 (1FE H ), and the second memory word line address interval AR 2 is from the address WLstart 2 (200 H ) to the address WLstop 2 (2FF H ), wherein a number of the memory word line address intervals provided by the DRAM unit 30 for storage and comparison is determined by a capacity of the register unit.

Moreover, in the step S 510 , the obtained start word line addresses WLstart 1 -WLstartP and the corresponding stop word line addresses WLstop 1 -WLstopP can be preset by a special command of the computer system. In other words, the computer system may preset the required memory capacity, so that the computer system may only use the memory word line address intervals AR 1 and AR 2 to access data. Alternatively, in other embodiments, the DRAM unit 30 may self-detect the memory cells in the memory array 110 that have been stored with data, and store the start word line addresses and the stop word line addresses of the memory word line address intervals AR 1 and AR 2 to the register unit 330 , so as to achieve a purpose of refreshing the memory cells stored with data.

Referring to FIG. 5 again, when the refresh mode is entered, a step S 520 is executed, by which the refresh address module 310 cyclically produces the refresh word line address WL (as that shown in FIG. 6 ). Then, in step S 530 , the address interval determination unit 340 receives and determines whether the refresh word line address WL is within the memory word line address intervals AR 1 and AR 2 . If the refresh word line address WL is within the memory word line address intervals AR 1 and AR 2 (for example, the refresh word line address WL is between 005 H -0FE H or 200 H -2FF H ), a step S 540 is executed, by which the address interval determination unit 340 switches the refresh enable signal S en to an enable potential (for example, a high potential), so that the signal comparator module 430 (shown in FIG. 4 ) in the memory array 110 can perform the data charging operation to the memory cells corresponding to the refresh word line address WL.

Comparatively, if the refresh word line address WL is not within the memory word line address intervals AR 1 and AR 2 (for example, the refresh word line address WL is between 000 H -004 H , 0FF H -1FF H or 300 H -FFF H ), a step S 550 is executed, by which the address interval determination unit 340 switches the refresh enable signal S en to a disable potential (for example, a low potential), so that the signal comparator module 430 stops the data charging operation. Moreover, after the steps S 540 and S 550 are completed, the step S 530 is repeated to continually determine whether the refresh word line address WL is within the memory word line address intervals AR 1 and AR 2 .

Another embodiment of the invention is provided below with reference of FIG. 7 , FIG. 7 is a block diagram illustrating a DRAM unit according to another embodiment of the invention. Referring to FIG. 7 , a difference between the present embodiment and the above embodiment is that in the present embodiment, the register unit can be replaced by a plurality of start word line address registers 710 _ 1 - 710 _P and a plurality of stop word line address registers 720 _ 1 - 720 _P. Each start word line address register 710 — i may store one start word line address WLstarti, and the corresponding stop word line address register 720 — i stores one stop word line address WLstopi, wherein i is a positive integer, and 1≦i≦P. Other details of the present embodiment are similar to that of the aforementioned embodiment, and therefore detailed descriptions thereof are not repeated.

In summary, in the invention, commands of a computer system or self-detect result of the memory cell stored with data form the DRAM can be used to obtain the word line address intervals. Then, during the refresh mode, the refresh control module determines whether the refresh word line address is within the memory word line address intervals, so as to refresh the memory cells within the memory word line address intervals, or stop refreshing the memory cells outside the memory word line address intervals, so that power consumption of the DRAM during the refresh mode can be reduced. Moreover, by determining whether the memory cells in the DRAM have been stored with data, a plurality of the word line address intervals can be obtained, thus a purpose of only refreshing the memory cells stored with data can be achieved.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.